A Low Phase Noise Crystal Oscillator with a Fast Start-Up Bandgap Reference for WLAN Applications
Round 1
Reviewer 1 Report
The present manuscript commences with an investigation into the source of XO noise and subsequently leverages the low noise attributes of LDO power supplies to enhance XO phase noise performance. The proposed design showcases commendable results in relation to phase noise, area, and power consumption. However, to elevate the caliber of this manuscript, it is imperative to address the following considerations.
1. The manuscript lacks an explicit elucidation of the primary issues that currently afflict XO. Moreover, it does not adequately explicate the limitations of the conventional solution. The introduction to the structure of the paper is missing.
2. Fig.2 is too rough. It is recommended to indicate the power symbol and the connection relationship between input/output of each module in combination with transistor level circuit diagrams (Fig.3, 8, 11 and 12). For example, which port of the XO is connected with the output of the LDO(VLDO)?
3. In Fig.4, the positive temperature coefficient of tt and ss corner is greater than the negative temperature coefficient, while ff corner is the opposite. Temperature compensation deviates from room temperature, optimization recommended. In addition, it is necessary to give the temperature drift coefficient. In particular, when the mean value under ss corner is 1.215V, the temperature drift is too large (about 70 ppm/° C).
4. Slightly excessive static power consumption of the startup circuit. PM0 and NM2 can be regarded as an inverter, with PMOS in diode form connected in series above PM0 or to suppress the static power consumption of the startup circuit at nA level.
5. The feedback loop in Fig.6 and Fig.7 is incorrect. In Fig.7, the output of LDO(VLDO) is shorted to ground?! The subsequent noise analysis correspondingly occurred errors.
6. In Fig.7, is the Cload off chip? The manuscript lacks stability analysis for LDO. Is there a need for stability compensation, and if so, how can it be resolved?
7. Where do the PD and PU signals in Fig.11 come from? How does the PN in Fig.12 operate? If PN is used to turn off the LDO output, pulling up the input voltage of the power transistor is more important. Moreover, the BG output should be turned off synchronously.
8. Note the normative application of abbreviations. Pay attention to clerical errors. In line 92, the 1.4 mV should be modified to 14 mV. In line 157, Eq. (3) should be changed to Eq. (13). And modify the statement of line 166. The current flowing through Q1 is not Eq. (4). The formula itself is correct, but the description or formula form needs to be modified.
Author Response
Author's Reply to the Review Report (Reviewer 1)
1.The manuscript lacks an explicit elucidation of the primary issues that currently afflict XO. Moreover, it does not adequately explicate .
Answer: Thank you for your suggestion. The article is really missing the limitations of the traditional solution and the introduction of the structure of the paper. We have added relevant content to the article based on your suggestion.The details of the changes in the paper are to be checked in the Reply Word.
2.Fig.2 is too rough. It is recommended to indicate the power symbol and the connection relationship between input/output of each module in combination with transistor level circuit diagrams (Fig.3, 8, 11 and 12). For example, which port of the XO is connected with the output of the LDO(VLDO)?
Answer: Thank you for your suggestion. We have labeled the key ports in the block diagram to make the connections between the block diagrams more clear.The details of the changes in the paper are to be checked in the Reply Word.
3.In Fig.4, the positive temperature coefficient of tt and ss corner is greater than the negative temperature coefficient, while ff corner is the opposite. Temperature compensation deviates from room temperature, optimization recommended. In addition, it is necessary to give the temperature drift coefficient. In particular, when the mean value under ss corner is 1.215V, the temperature drift is too large (about 70 ppm/°C).
Answer: Thanks to your suggestion and reminder, we have also made some adjustments to the compensation of the bandgap reference. Since the Vbe of the diode deviates a little at different process corners and temperatures, which leads to a little offset in the compensation, making the voltage change a little with temperature. We found that the temperature drift of the voltage is larger at the ss process corner. To reduce this deviation, we increased the ratio of R2/R1 and adjusted the number of diodes. Finally, the maximum voltage variation with temperature is 1.9mV, and the temperature drift coefficient is calculated to be about 10ppm/°C at this time. The simulation results are shown below. The details of the changes in the paper are to be checked in the Reply Word.
4.Slightly excessive static power consumption of the startup circuit. PM0 and NM2 can be regarded as an inverter, with PMOS in diode form connected in series above PM0 or to suppress the static power consumption of the startup circuit at nA level.
Answer: Thank you very much for your suggestion, your suggestion can indeed bring some power consumption optimization. PM0 is actually designed with 4 W/L=0.5u/20u PMOS tubes connected in series, similar to your suggested PMOS design with series diode connection, all to increase its on-resistance and reduce current power consumption, which ends up being about 1uA. Our previous design, taking into account the noise and power consumption, we finally adopted this structure. Of course, our subsequent optimization can indeed refer to your suggestion to further reduce the current power consumption. The details of the changes in the paper are to be checked in the Reply Word.
5.The feedback loop in Fig.6 and Fig.7 is incorrect. In Fig.7, the output of LDO(VLDO) is shorted to ground?! The subsequent noise analysis correspondingly occurred errors.
Answer: I am sorry for this problem caused by my mistake when drawing the frame diagram. There is an NMOS tube connected to the output of the LDO and its gate input is PN. PN is the control signal of the system and is accessed via SPI. When the LDO output is normal, the PN signal is low and the NMOS tube is cut off to prevent the LDO output from shorting out. When the LDO output is turned off, the PN signal is high. When the LDO is operating, the noise contribution from this NMOS is very low and negligible. The details of the changes in the paper are to be checked in the Reply Word.
6.In Fig.7, is the Cload off chip? The manuscript lacks stability analysis for LDO. Is there a need for stability compensation, and if so, how can it be resolved?
Answer: Cload is actually DECAP, which is used to reduce the amplitude of LDO output oscillation caused by crystal oscillation. The zero and poles of the LDO are analyzed in 2.2.3 of the article. In order to ensure the stability of the LDO, we use Miller compensation for the EAMP and add a nulling resistor to increase its phase margin. As shown in the figure below, the phase margin of the LDO is finally 60.5 degrees. The details of the changes in the paper are to be checked in the Reply Word.
7.Where do the PD and PU signals in Fig.11 come from? How does the PN in Fig.12 operate? If PN is used to turn off the LDO output, pulling up the input voltage of the power transistor is more important. Moreover, the BG output should be turned off synchronously.
Answer: The PU and PD signals mentioned above come from the system and are used to control the switching of the crystal oscillator via SPI.PN is the control signal of the system and is accessed via SPI. When the LDO output is normal, the PN signal is low and the NMOS tube is cut off to prevent the LDO output from shorting out. When the LDO output is turned off, the PN signal is high. To keep the circuit diagram clear, we have omitted some of the switches and dummy tubes from the block diagram. From the actual circuit diagram, we can see that the switch signals used to control the LDO and Bandgap are coming from the system and are controlled via SPI. When the LDO is turned off, the bandgap reference is also turned off at the same time to save power. The details of the changes in the paper are to be checked in the Reply Word.
8.Note the normative application of abbreviations. Pay attention to clerical errors. In line 92, the 1.4 mV should be modified to 14 mV. In line 157, Eq. (3) should be changed to Eq. (13). And modify the statement of line 166. The current flowing through Q1 is not Eq. (4). The formula itself is correct, but the description or formula form needs to be modified.
Answer: Thank you very much for your reminder and I have revised the above irregular description accordingly. The details of the changes in the paper are to be checked in the Reply Word.
Author Response File: 
Author Response.docx
Reviewer 2 Report
Very nice and clearly written paper. It presents a significant piece of work on the design of a 40 MHz XO based on the 55 nm CMOS process. The background, design, results, and discussion are well written, and this is the first time I'm not finding a thing to improve while writing a review.
Author Response
Thank you very much for your affirmation and support. I will further study and improve on the basis of this design. Have a good time!
Reviewer 3 Report
Review of the article titled A low phase noise crystal oscillator with a fast start up bandgap reference.
This paper deals with an integrated electronics which is designed for generated a low noise voltage reference with a startup circuitry for an integrated crystal oscillator.
L49 -> Maybe you can add a reference to the historical paper to the motionnal modelisation of quartz crystal as you did with the Cady reference.
L91-94 -> I'm not sure to have understood the difference between the process tt, ss and ff. For me it's not clear and can be improved with a previous definition/explanation.
L106 -> NM2 turns on and so does PM0 turn off at the same time?
L109-110 -> If PM0 and NM2 are simultaneously ON, is it not a short circuit on the power ? Or is something missing?
L187-189 -> Are C1 and C4 on PCB and C2 and C3 integrated? I think there is a mistake in the text L188 with a confusion between red and green box?
- In the Fig. 8, you don't talk about the impedance matching in your oscillator design. Can it be a potential issue ?
- What is the typical unloaded quality factor of your used crystal? Have you an idea about the loaded quality factor of your crystal in the PI network of your oscillator? Is it something critical in this kind of design regarding the phase noise target?
- Table2 comparing results between several lab DUT, maybe it can be interesting to add a state-of-the-art commercial system result in this table.
Author Response
Author's Reply to the Review Report (Reviewer 3)
Q1.L49 -> Maybe you can add a reference to the historical paper to the motionnal modelisation of quartz crystal as you did with the Cady reference.
Answer: I have added relevant references to the description of the crystal model in the article, and have refined some of the model details. The details of the changes in the paper are to be checked in the Reply Word.
Q2.L91-94 -> I'm not sure to have understood the difference between the process tt, ss and ff. For me it's not clear and can be improved with a previous definition/explanation.
Answer: The idea of process corners is to limit the speed fluctuation range of NMOS and PMOS transistors to a rectangle defined by four corners. These four corners are: fast NFET and fast PFET, slow NFET and slow PFET, fast NFET and slow PFET, and slow NFET and fast PFET. for example, transistors with thinner gate oxygen and lower threshold voltage, are near the fast corner. Simulation of the circuit at various process corners and extreme temperature conditions is the basis for determining the yield. So the ss, tt, and ff process corners refer to the lower left corner, the center and the upper right corner, respectively. I have also added a brief explanation of the process corner to the appropriate paragraph. The details of the changes in the paper are to be checked in the Reply Word.
Q3/Q4.L106 -> NM2 turns on and so does PM0 turn off at the same time? L109-110 -> If PM0 and NM2 are simultaneously ON, is it not a short circuit on the power ? Or is something missing?
Answer: When NM2 is turned on, PM0 will also be turned on at the same time. However, PM0 adopts Reciprocal tube structure, of which gate length is much longer than the gate width, so its on-resistance is very large, which can effectively reduce the current between the power supply and ground (the current is about 1uA), but also to avoid power ground short circuit. The details of the changes in the paper are to be checked in the Reply Word.
Q5.L187-189 -> Are C1 and C4 on PCB and C2 and C3 integrated? I think there is a mistake in the text L188 with a confusion between red and green box?
Answer:We are very sorry for any misunderstanding we may have caused. The picture shows C1 and C4 integrated inside the chip, which are programmable capacitor arrays. By changing the number of capacitors on in the capacitor array, the load capacitance of the crystal oscillator circuit is fine-tuned, so as to fine-tune the crystal oscillator output frequency. C2 and C3 are the load capacitors that are soldered to the PCB along with the quartz crystal. To avoid this misunderstanding, I have adjusted the boxes in the picture. The details of the changes in the paper are to be checked in the Reply Word.
Q6. In the Fig. 8, you don't talk about the impedance matching in your oscillator design. Can it be a potential issue?
Answer: Thank you very much for the reminder. The output frequency of the crystal oscillation circuit is 40MHz, which is a relatively low frequency clock signal. In the low frequency circuit, we generally do not consider the transmission line matching problem, but only consider the situation between the signal source and the load, because the wavelength of the low frequency signal is long compared to the transmission line, the transmission line can be regarded as a "short line", and the reflection can be disregarded. The details of the changes in the paper are to be checked in the Reply Word.
Q7. What is the typical unloaded quality factor of your used crystal? Have you an idea about the loaded quality factor of your crystal in the PI network of your oscillator? Is it something critical in this kind of design regarding the phase noise target?
Answer: The quality factor is very important for low-noise crystal oscillator designs. But because its quality factor is so high (exceeding 10,000), the contribution to crystal oscillator noise is much lower than the contribution from power supply noise. Therefore, the main way of low-noise design in this paper is to reduce the impact of power supply noise on the crystal oscillator circuit. The details of the changes in the paper are to be checked in the Reply Word.
Q8.Table2 comparing results between several lab DUT, maybe it can be interesting to add a state-of-the-art commercial system result in this table.
Answer: Since crystal oscillation circuits are commonly used in industry to provide reference clocks for digital circuits and phase-locked loops. Industry keeps the detailed test results of crystal oscillator circuits confidential and generally does not disclose their detailed test results. Secondly, after the crystal oscillator circuit is integrated into the transceiver movement, it is more difficult to test its parameters. The details of the changes in the paper are to be checked in the Reply Word.
Author Response File: Author Response.docx
