Decoupled Control for Double-T Dc-Dc MMC Topology for MT-HVdc/MVdc Grids

Featured Application

The control method proposed in this work can be applied to power converters operating in multi-terminal high-voltage dc systems.

Abstract

This paper proposes a decoupled control of a dc-dc modular multilevel converter (MMC) based on a double-T topology intended for multi-terminal high voltage direct current (MT-HVdc) transmission systems or emerging distribution systems operating in medium voltage direct current (MVdc). The aim of the proposed control strategy is to obtain an input current with reduced harmonic content and to eliminate the output ac common-mode voltage, which is not allowed in MT-HVdc systems. The control strategy consists of injecting two circulating ac currents and two dc currents that allow the energy balance between the arms of the converter and the general energy balance of the topology. The dc and ac currents are decoupled and allow control over load variations and reference changes in the dc-links. The proposed topology is mathematically modeled and the control method is then derived. Simulation results are presented to validate the proposed system.

1. Introduction

A fundamental aspect of electric power systems is the efficiency of transmission lines from generation centers to consumption ones. This problem has led to important research and technological development in recent years [1,2,3]. Currently, most of the transmission grids in the world are based on high-voltage alternating current (HVac). However, HVac grids present serious limitations when it comes to transmitting at large distances [3,4,5,6,7,8], then power transmission in HVdc is the preferred alternative and has been largely implemented in different electrical systems around the world [9,10,11,12]. For instance, the $\pm$1100 kV Ultra-HVdc line transmission in China [11] or the $\pm$650 kV Kimal-Lo-Aguirre HVdc transmission line in Chile [13]. In the future, it is expected there will be an increase in the number of long-distance HVdc transmission systems [14,15,16]. On the other hand, an important configuration in HVdc grids is the multi-terminal connection grids (MT-HVdc) [17,18,19]. An MT-HVdc grid consists of the interconnection of three or more HVdc sub-stations with different voltage magnitudes (see Figure 1).

In MT-HVdc grids, there could be bidirectional power flows between the different terminals, therefore dc-dc converters are required to adapt the voltage levels of the individual substations, as shown in Figure 1 [20].

In recent years, research has been carried out on dc-dc converters for HVdc systems [21,22,23,24] and recently for MVdc grids [23]. Several power converter topologies for HVdc systems have been reported in the literature [25]. In particular, modular multilevel converters are very attractive for this type of application [26,27], since they offer bidirectional power flow capability and low distortion in the input and output currents. Variations of the standard MMC structure have also been proposed, such as the resonant MMC [28,29,30,31], or the novel double-Y and double-Pi topologies [32,33,34,35].

In this paper, a decoupled control strategy for a dc-dc converter intended for MT-HVdc applications is presented. The topology has been called double-T since it is built with two T-structures (see Figure 2). The proposed MMC operating with the presented control method exhibits the following features: no common-mode voltage at the converter output, the minimum number of cells to build the topology, and null ac components in the input current. The operating principle of the converter is described in detail as well as the proposed control strategy. Simulation results are presented to validate the control method and a sensitivity analysis is carried out to evaluate its performance under variations of the converter parameters.

The remainder of the paper is organized as follows. In Section 2 the mathematical model of the converter is presented. Section 3 describes the operating principle of the topology. The control strategy proposed is derived in Section 4 whereas the simulation results are presented in Section 5. In Section 6 Brief Sensitive Analysis is presented. Finally, the conclusions are stated in Section 7.

2. Converter Model

A schematic of the converter is shown in Figure 3. The converter is built with two T-structures ($T_1$ and $T_2$) with three arms each. In turn, each arm is built with an inductor $L$ and N cascaded H-bridges named series, derivation, and output stacks. The use of H-bridges in the stacks allows the possibility to operate with bidirectional power flow. Moreover, the inductors are required to couple the ac voltage components produced by each stack for current control purposes. The resistor $R$ represents the equivalent resistance of the inductor and each T-structure is grounded through a derivation stack.

Figure 4 shows the average model of the converter in terms of the voltages and currents in each arm of the topology. Time-varying voltages $v_{s{e}_{1,2}}\left(t\right)$, $v_{d{e}_{1,2}}\left(t\right)$, and $v_{o_{1,2}}\left(t\right)$ are produced by stacks series, derivation, and output, respectively. These time-varying voltages are dependent on the arm currents $i_{s{e}_{1,2}}\left(t\right)$, $i_{d{e}_{1,2}}\left(t\right)$, and $i_{o_{1,2}}\left(t\right)$, respectively. $V_i$ is the dc input voltage. $V_o$ is the converter output voltage which has a dc component and harmonics multiple of the switching frequency. In an MT-HVdc grid, $V_o$ is another terminal and can deliver power to $V_i$.

Applying voltage and current laws to the meshes, then the main equations defining the average model can be derived:

$$V_i=L\frac{d{i}_{se1}\left(t\right)}{dt}-L\frac{d{i}_{de1}\left(t\right)}{dt}+R\left(i_{se1}\left(t\right)-i_{de1}\left(t\right)\right)+v_{se1}\left(t\right)+v_{de1}\left(t\right)$$

(1)

$$V_i=L\frac{d{i}_{se2}\left(t\right)}{dt}-L\frac{d{i}_{de2}\left(t\right)}{dt}+R\left(i_{se2}\left(t\right)-i_{de2}\left(t\right)\right)+v_{se2}\left(t\right)+v_{de2}\left(t\right)$$

(2)

$$0=L\frac{d{i}_{de1}\left(t\right)}{dt}+L\frac{d{i}_{o1}\left(t\right)}{dt}+R\left(i_{de1}\left(t\right)+i_{o1}\left(t\right)\right)-v_{de1}\left(t\right)+v_{o1}\left(t\right)+V_o$$

(3)

$$0=L\frac{d{i}_{de2}\left(t\right)}{dt}+L\frac{d{i}_{o2}\left(t\right)}{dt}+R\left(i_{de2}\left(t\right)+i_{o2}\left(t\right)\right)-v_{de2}\left(t\right)+v_{o2}\left(t\right)+V_o$$

(4)

$$i_{de1}\left(t\right)=i_{o1}\left(t\right)-i_{se1}\left(t\right)$$

(5)

$$i_{de2}\left(t\right)=i_{o2}\left(t\right)-i_{se2}\left(t\right)$$

(6)

$$-i_i\left(t\right)-i_{de1}\left(t\right)-i_{de2}\left(t\right)+i_o\left(t\right)=0$$

(7)

The voltages $v_{s{e}_{1,2}}\left(t\right)$, $v_{d{e}_{1,2}}\left(t\right)$ and $v_{o_{1,2}}\left(t\right)$ are defined in (8)–(10) where $S_{i,s{e}_{1,2}}\left(t\right)$, $S_{i,d{e}_{1,2}}\left(t\right)$ and $S_{i,o_{1,2}}\left(t\right)$ are the switching functions of each sub-module (H-bridge) of each stack of the topology. The value of the switching functions can be either −1, 0, or 1. Finally, $C_i$ are the capacitors of each sub-module.

$$v_{s{e}_{1,2}}\left(t\right)={\displaystyle \sum }_{j=1}^2{\displaystyle \sum }_{i=1}^N\frac{1}{C_i}\int \left(i_{s{e}_j}\left(t\right)·S_{i,s{e}_j}\left(t\right)\right) dt$$

(8)

$$v_{d{e}_{1,2}}\left(t\right)={\displaystyle \sum }_{j=1}^2{\displaystyle \sum }_{i=1}^N\frac{1}{C_i}\int \left(i_{d{e}_j}\left(t\right)·S_{i,d{e}_j}\left(t\right)\right) dt$$

(9)

$$v_{o_{1,2}}\left(t\right)={\displaystyle \sum }_{j=1}^2{\displaystyle \sum }_{i=1}^N\frac{1}{C_i}\int \left(i_{o_j}\left(t\right)·S_{i,o_j}\left(t\right)\right) dt$$

(10)

From (1)–(7) it is possible to obtain the expressions for the instantaneous currents. Let $x\left(t\right)={\left[i_{o1}\left(t\right) i_{o2}\left(t\right) i_{se1}\left(t\right) i_{se2}\left(t\right)\right]}^T$ be the state vector of independent currents and $u\left(t\right)={\left[v_{se1}\left(t\right) v_{se2}\left(t\right) v_{de1}\left(t\right) v_{de2}\left(t\right) v_{o1}\left(t\right) v_{o2}\left(t\right)\right]}^T$ the control variables vector, the state-space model is given by:

$$\frac{d}{dt}\left[\begin{array}{c}{i}_{o1}\left(t\right)\\ i_{o2}\left(t\right)\\ i_{se1}\left(t\right)\\ i_{se2}\left(t\right)\end{array}\right]=-\frac{R}{L}\left[\begin{array}{c}{i}_{o1}\left(t\right)\\ i_{o2}\left(t\right)\\ i_{se1}\left(t\right)\\ i_{se2}\left(t\right)\end{array}\right]+\frac{1}{3L}\left[\begin{array}{cccccc}-1& 0& 1& 0& -2& 0\\ 0& -1& 0& 1& 0& -2\\ -2& 0& -1& 0& -1& 0\\ 0& -2& 0& -1& 0& -1\end{array}\right]\left[\begin{array}{c}{v}_{se1}\left(t\right)\\ v_{se2}\left(t\right)\\ v_{de1}\left(t\right)\\ v_{de2}\left(t\right)\\ v_{o1}\left(t\right)\\ v_{o2}\left(t\right)\end{array}\right]+\left[\begin{array}{c}{V}_i-2V_o\\ V_i-2V_o\\ 2V_i-V_o\\ 2V_i-V_o\end{array}\right]$$

(11)

3. Operating Principle

This work considers an approach based on the energy balance between the stacks of the converter. To achieve this balance ac and dc voltages and currents are employed to transfer energy to and from the different stacks. Figure 5 shows a simplified model using dc voltages $V_{s{e}_{1,2}},V_{d{e}_{1,2}},V_{o_{1,2}}$ and ac voltages $v_{s{e}_{1,2}},v_{d{e}_{1,2}},v_{o_{1,2}}$ that are produced by each stack, under steady-state operation. The dc voltages are obtained by applying voltage law to the arms of the topology; their values are $V_{s{e}_{1,2}}=(V_i-V_o)$ and $V_{d{e}_{1,2}}=V_o$. For control purposes the dc voltages of the output stacks are zero. If $V_{o_{1,2}}=0$, the energy transferred by the output stacks due to dc components is minimized, and it is associated mainly to ac voltages and currents.

The ac voltages $v_{se1,2},v_{d{e}_{1,2}},v_{o_{1,2}}$ have sinusoidal waveform as $\pm v_u=\pm V_u\sin \left(2\pi f_{c}t\right)$, where $f_c$ is a fundamental frequency. The sign of $V_u$ depends on the control objective and on the circulating current, in this case $v_{se1}=-v_u$, $v_{s{e}_2}=v_u$, $v_{d{e}_1}=+v_u$, $v_{d{e}_2}=+v_u$, $v_{o_1}=+v_u$ and $v_{o_2}=-v_u$ (see Figure 5). These ac voltages are intended to interact with the circulating ac currents $i_{u1}$ and $i_{u2}$ to achieve the energy balance of the converter.

The ac circulating currents can be expressed as $i_{u1}=I_{u1}\sin \left(2\pi f_{c}t\right)$ and $i_{u2}=I_{u2}\sin \left(2\pi f_{c}t\right)$. These currents are aimed to allow the energy balance of the derivation ($i_{u1}$) and output ($i_{u2}$) stacks. Additionally, dc currents $I_{se1,2}, I_{de1,2}, I_{o1,2}$ circulate in all arms of the topology. The dc currents $I_{se1,2}$ allow the energy balance of series stacks. Using expressions (1)–(7), neglecting the series equivalent resistance $R$ of the inductor $L$ and neglecting the product $\omega L$ which is comparatively small with respect to the product $VI$, it is possible to calculate the power equations of each stack as defined in (12)–(17). With the operating principle of the topology and the model defined in Section 2, the control strategy can now be derived as presented in Section 4.

$$P_{s{e}_1}=\frac{d{\overline{W}}_{s{e}_1}}{dt}=\int v_{se1}\left(t\right)·i_{se1}\left(t\right)dt=\left(V_i-V_o\right)I_{s{e}_1}-v_u i_u{}_1$$

(12)

$$P_{d{e}_1}=\frac{d{\overline{W}}_{d{e}_1}}{dt}=\int v_{de1}\left(t\right)·i_{de1}\left(t\right)dt=-V_o{I}_{d{e}_1}+v_u \left(i_u{}_1-i_u{}_2\right)$$

(13)

$$P_{o_1}=\frac{d{\overline{W}}_{o_1}}{dt}=\int v_{01}\left(t\right)·i_{o1}\left(t\right)dt=v_u i_u{}_2$$

(14)

$$P_{s{e}_2}=\frac{d{\overline{W}}_{s{e}_2}}{dt}=\int v_{se2}\left(t\right)·i_{se2}\left(t\right)dt=\left(V_i-V_o\right)I_{s{e}_2}-v_u i_u{}_1$$

(15)

$$P_{d{e}_2}=\frac{d{\overline{W}}_{d{e}_2}}{dt}=\int v_{de2}\left(t\right)·i_{de2}\left(t\right)dt=-V_o{I}_{d{e}_2}-v_u \left(-i_u{}_1+i_u{}_2\right)$$

(16)

$$P_{o_2}=\frac{d{\overline{W}}_{o_2}}{dt}=\int v_{o2}\left(t\right)·i_{o2}\left(t\right)dt=v_u i_u{}_2$$

(17)

4. Control of the Double-T Converter

The control strategy is based on the average energy balance of all arms of the converter. The control scheme is composed by three stages: average energy control on each stack; current control with references obtained in the energy control; and stack internal control for the equalization of the dc-link voltage in each submodule.

A. 

Energy Balance of Stacks

Using expressions (1)–(4) and (11) and knowing that the independent currents of the topology are four, the control system is designed. Taking into account the energy balance approach, the energy of the series stack is controlled by $I_{se}$ (see (12) and (15)) via a proportional–integral (PI) controller. For derivation stacks, the control action is performed by the ac current $i_{u1}$ whereas for output stacks, the energy control is carried out by the ac current $i_{u2}$. It should be noted in Figure 5 that $i_{u1}$ and $i_{u2}$ circulate through both T-structures. Therefore, for the energy control of the converter, there are four PI controllers.

To impose the dc currents $I_{s{e}_1}$ and $I_{s{e}_2}$ from energy series_1,2 controllers, another two PI controllers are used. As the energy control loops and the current control loops are nested, in this work they are decoupled using natural frequencies ${\omega }_n$ of the controllers in a ratio of 1/70. The natural frequency of the series_1,2 energy controllers is ${\omega }_{n_e}$ and the natural frequency of the current controllers is ${\omega }_{n_c}$, then ${\omega }_{n_c}/{\omega }_{n_e}=70$. Figure 6 shows the control scheme for the energy balance of the series stacks.

To impose alternating currents $i_{u1}$ and $i_{u2}$ from energy controllers in derivation stacks, proportional–resonant ($PR$) controllers are used. In this work, the frequency used for $i_{u1}$ and $i_{u2}$ is $f_c=500 \left[\mathrm{Hz}\right]$. This frequency should consider the “trade-off” between switching losses in the H-bridges and the dynamic response in the derivation energy balance controllers. Additionally, in this work, for the proposed operating point, the magnitude of $v_u$ is constant as $V_u=0.7V_o$. The value of $V_u$ is fundamental for the energy control of the derivation and output stacks. It is desired for $V_u$ to be high so that the dynamics of the control are fast, but it must not exceed the maximum output voltage to avoid overmodulation and the consequent voltage distortion. For the simulation study $V_u=9.1 \mathrm{kV}$. Since the output direct voltage is $V_o=13k{V}_{DC}$, then $V_{arm}=13 \mathrm{kV}+9.1 \mathrm{kV}=22.1 \mathrm{kV}$ is within the value that the converter arm can deliver. The maximum value to be delivered by the arm is $V_{ar{m}_{max}}=3 \mathrm{kV}·8=24 \mathrm{kV}$. Figure 7 shows the energy balance control scheme of the converter stacks.

B. 

Intra-Stacks Voltage Balance

The balance of the dc-links voltages of each stack is carried out by exchanging power between a quadrature current $i_q$ that circulates in addition to the energy balance currents. This current can be defined as $i_q=I_q\sin \left({\omega }_{c}t+\pi /2\right)$ and is phase-shifted 90° with respect to $i_{u1}$ and $i_{u2}$. Then, $i_{u1}+i_q$ and $i_{u2}+i_q$ are the currents circulating internally in the converter. Moreover, in each sub-module there is a voltage $v_{bal}=V_{bal}\sin \left({\omega }_{c}t+\pi /2\right)$ that is in phase with the current $i_q$. This allows exchanging power and generating the internal balance of the stacks keeping the dc-links of the N sub-modules with the same voltage. This voltage balance controller is based on a proportional (P) controller that receives the average value of the N dc-links voltages. The controller output is multiplied by $\sin \left({\omega }_{c}t+\pi /2\right)$ and $V_{ba{l}_N}$ is then generated. Finally, as $i_q$ is in quadrature with respect to the currents $i_{u1}$ and $i_{u2}$, the intra-stack balance acts decoupled with respect to the energy control.

C. 

Decoupling Energy Balance Control

According to Equations (12)–(14), if these expressions are added, then (18) is obtained. In the same way, if (15)–(17) are added, the expression (19) is obtained.

$$P_{s{e}_1}+P_{d{e}_1}+P_{o_1}=\left(V_i-V_o\right)I_{s{e}_1}-V_o{I}_{d{e}_1}$$

(18)

$$P_{s{e}_2}+P_{d{e}_2}+P_{o_2}=v_u i_u{}_2$$

(19)

Equations (18) and (19) are used to design the series stack energy controllers. The dc currents $I_{d{e}_{1,2}}$ are added to obtain a feedforward compensation (see Figure 7). This leads to an improved energy balance dynamic of the dc-links of the series stacks. In the same way for the design of the derivation stacks energy control loops, if the (13), (14), (16), and (17) are added, the result is (20). In Figure 7 the implementation of the control strategy can be seen. For the control design of output stacks energy loops ($outpu{t}_1$ and $outpu{t}_2$), as there is no power transfer of DC components, this decoupling principle does not apply.

$$P_{d{e}_1}+P_{o_1}+P_{d{e}_2}+P_{o_2}=2v_u{i}_{u_1}-V_o\left(I_{d{e}_1}+I_{d{e}_2}\right)$$

(20)

5. Simulations Results

Simulations are carried out considering the parameters in

Table 1. Simulation parameters.

Description	Value
Input voltage, $HVD{C}_1=V_{in}$	$23000 \left[\mathrm{V}\right]$
Output voltage, $HVD{C}_2=V_o$	$13000 \left[\mathrm{V}\right]$
Rated output power, $P_{out}$	$1.25 \left[\mathrm{MW}\right]$
Dc-links capacitors, $C_{s{e}_{1,2}}=C_{d{e}_{1,2}}=C_{o_{1,2}}$	$1 \left[\mathrm{mF}\right]$
Arm inductances, $L$	$2.5 \left[\mathrm{mH}\right]$
Series equivalent resistance of inductors, $R$	$50 \left[\mathrm{m}\Omega \right]$
Dc-links reference voltage	$3000 \left[\mathrm{V}\right]$
Frequency of ac circulating currents	$500 \left[\mathrm{Hz}\right]$
Number of H-bridges per stack	$8$
Number of arms	$6$
Switching frequency, $f_{sw}$	$2 \left[\mathrm{kHz}\right]$

. Since 8 sub-modules per stack are used, the topology comprises a total of 48 H-bridges. The input and output voltage values have been defined for a typical MVdc distribution system.

Since the focus of this paper is on the control strategy for the double-T topology, the design aspects of the converter are not addressed in detail. However, general design procedures reported in [32,34,35] were followed.

Regarding the nomenclature used to show the results, the capacitor of the first H-bridge of the series_1,2, derivation_1,2, and output_1,2 stacks will be called $v_{c{1}_{se1,2}}$, $v_{c{1}_{de1,2}}$ and $v_{c{1}_{o1,2}}$, respectively.

In the first test, simulations for load changes applied at t = 0.4 s, t = 0.8 s, and t = 1.2, are performed. Figure 8a shows one dc-link voltage per stack. As can be seen, the energy balance controller responds satisfactorily and very small variations in the dc-link voltages are obtained when the load changes. The voltage reference for all the dc-links has been set to 3 kV. Figure 8b shows the output power. From 0.8 to 1.2 s the output power is nominal.

Figure 9 shows the 24 voltage waveforms of the dc-links of the $T_1$ structure whereas Figure 10 shows the dc-link voltages associated with the $T_2$ structure. An accurate response of the control scheme can be appreciated, with a minimum variation on the dc-link voltages when the load varies.

The converter output voltage and input current are shown in Figure 11, both presenting very low ripple. The spectra associated to these waveforms are shown in Figure 12. In both waveforms, the THD is lower than 1% with respect to the fundamental frequency, which in this case is 0 Hz. The average voltage value is $V_{o_{0Hz}}=13 \mathrm{kV}$ and the average current is $I_{i{n}_{0Hz}}=53 \mathrm{A}$. As the number of sub-modules per stack are 8 and the switching frequency is $2 \mathrm{kHz}$, the harmonic components appear around $32 \mathrm{kHz}$ (since the H-bridge doubles the equivalent switching frequency).

Figure 13 shows the currents of each converter arm. The currents in the series and derivation stacks are shown in Figure 13a,b, respectively. It can be noted that these currents have both ac and dc components. On the other hand, the current in the output stacks in Figure 13c is mainly dc with a small ac component. It is important to note that the currents $i_{se1}$ and $i_{se2}$ must be phase-shifted 180° so that the converter input current $I_{in}$ has negligible ac component (see Figure 11b).

Figure 14 shows results for power variation and changes in the dc-link voltage reference. One dc-link voltage per stack is shown in Figure 14a and the output power is presented in Figure 14b. At t = 0.5 s a change in the reference of the dc-link voltages from 3 kV to 3.6 kV is applied. The opposite change is applied at t = 0.8 s. Good dynamic response of the dc-link voltages in every stack can be observed.

Figure 15 shows results for variations in the input and output voltages. In the case of the output voltage, the control reference is varied. Figure 15a shows the waveforms of one dc-link voltage per stack. Changes in the output voltage reference take place at t = 0.4 s and t = 0.8 s, whereas a change in the input voltage is applied at t = 0.6 s. In every input/output voltage variation applied, the fast and accurate response of the dc-link voltage control system can be observed.

6. Brief Sensitivity Analysis

A study to validate the performance of the control system under changes in parameters of the converters is carried out. Variations of the capacitances and inductances of the converters are considered, and the parameters of the controllers are not changed.

6.1. Case 1

The value of the capacitors are set to $C_{s{e}_1}=1 \mathrm{mF}$, $C_{s{e}_2}=0.99 \mathrm{mF}$, $C_{d{e}_1}=1 \mathrm{mF}$, $C_{d{e}_2}=1.01 \mathrm{mF}$, $C_{o_1}=1 \mathrm{mF}$, and $C_{o_2}=1.01 \mathrm{mF}$. It should be mentioned that all the capacitors in a single arm are equal. The dc-link voltage reference is $3 \mathrm{kV}$ and the converter operates with nominal load.

Figure 16 shows the dc-link voltages obtained. As can be seen, the control response is still accurate reaching the reference in short time and without error in steady state.

6.2. Case 2

In this second analysis, the values of the capacitors are: $C_{s{e}_1}=0.98 \mathrm{mF}$, $C_{s{e}_2}=1.02 \mathrm{mF}$, $C_{d{e}_1}=1 \mathrm{mF}$, $C_{d{e}_2}=1.02 \mathrm{mF}$, $C_{o_1}=0.98 \mathrm{mF}$, and $C_{o_2}=1.02 \mathrm{mF}$. The results are shown in Figure 17. Again, a good response of the control system and zero steady-state error are obtained.

6.3. Case 3

In this third analysis, the capacitor values are: $C_{s{e}_1}=0.9 \mathrm{mF}$, $C_{s{e}_2}=1.1 \mathrm{mF}$, $C_{d{e}_1}=0.95 \mathrm{mF}$, $C_{d{e}_2}=1.05 \mathrm{mF}$, $C_{o_1}=0.9 \mathrm{mF}$, and $C_{o_2}=1 \mathrm{mF}$. The dc-link voltage waveforms obtained are shown in Figure 18. In this case, the variation of the parameters has been in some arms more than 10% of the original value and certain steady-state errors can now be observed.

In the following cases 4, 5, and 6, the effect on the control system due to variations in the inductances is analyzed.

6.4. Case 4

In this first inductance variation scenario, the values of the inductors are set to $L_{s{e}_1}=2.51 \mathrm{mH}$, $L_{s{e}_2}=2.5 \mathrm{mH}$, $L_{d{e}_1}=2.49 \mathrm{mH}$, $L_{d{e}_2}=2.51 \mathrm{mH}$, $L_{o_1}=2.49 \mathrm{mH}$, and $L_{o_2}=2.5 \mathrm{mH}$. The dc-link voltages are presented in Figure 19 where a proper dynamic response and null steady-state error are appreciated.

6.5. Case 5

The values of the inductors are: $L_{s{e}_1}=2.45 \mathrm{mH}$, $L_{s{e}_2}=2.55 \mathrm{mH}$, $L_{d{e}_1}=2.46 \mathrm{mH}$, $L_{d{e}_2}=2.54 \mathrm{mH}$, $L_{o_1}=2.47 \mathrm{mH}$, and $L_{o_2}=2.5 \mathrm{mH}$, and the dc-link voltages are presented in Figure 20. Once again, the control responds properly and there is no error in the steady state.

6.6. Case 6

Finally, the inductor values are defined as: $L_{s{e}_1}=2.3 \mathrm{mH}$, $L_{s{e}_2}=2.65 \mathrm{mH}$, $L_{d{e}_1}=2.4 \mathrm{mH}$, $L_{d{e}_2}=2.45 \mathrm{mH}$, $L_{o_1}=2.6 \mathrm{mH}$, and $L_{o_2}=2.7 \mathrm{mH}$. For this condition, the results are shown in Figure 21 where a response similar to cases 4 and 5 is obtained.

On the other hand, variations of the inductor equivalent resistance of up to 10% of its original value have also been simulated, but the results showed no variations in the dc-link voltages, then they are not presented in this work.

7. Conclusions

The control strategy presented in this work allows us to balance the energy of the converter arms by means of circulating ac and dc currents. The ac currents circulate only inside the converter not being reflected in the input or output of the topology. The ac current flow through $T_2$-structure is the same that in $T_1$-structure, this allows us to obtain an input current with minimum harmonic content. Moreover, due to the control strategy, the output voltage has also a very low ripple. These characteristics are fundamental in HVdc systems since they are not designed to manage ac variables.

On the other hand, the sensitivity analysis shows that small variations of the converter parameters do not affect the performance of the control system.

The decoupling of the control allows us to reduce the impact of power changes on the output, as seen in the results. The presented topology operating with the proposed control strategy exhibits no common-mode alternating voltage component, which is an advantage and validates its possible use in HVdc or MVdc systems.