Variable Multiple Interleaved Bi-Directional DC/DC Converter with Current Ripple Optimization

Abstract

In order to reduce the current ripple and improve the power density of the system, the multiple structure design is generally adopted by the traditional bidirectional DC/DC converter. However, the fixed multiplicity design can’t make the DC/DC power converter always output the smallest current ripple under different duty ratios. Through this research, it is found that the current ripple is related to duty cycle and parallel multiplicity, and then a variable multiplicity bidirectional DC/DC power converter is proposed. Firstly, the relationship between the current ripple and parallel multiplicity and duty cycle is deduced, and the basic topology of variable multiplicity bidirectional DC/DC power converter is determined; Secondly, the average value model and AC small signal model of the system are established based on the topological structure, and then the state equation is obtained. Thirdly, the current compensation control method is designed based on the state equation. Finally, the experimental platform of variable multiplicity bidirectional DC/DC power converter is built.

1. Introduction

Energy storage systems have been widely used to improve the power distribution between renewable power generation, large power grids, and user loads [1,2,3]. As the power transmission channel between the DC bus and the energy storage system, the bidirectional DC/DC converter can realize bidirectional energy flow and improve energy distribution efficiency [4,5,6]. However, the DC/DC converter may introduce a large current ripple to the DC bus, which affects the quality of the power supply [7,8].

Many researchers have proposed different methods to reduce the current ripple, each of which has its adpply [7,8].

Many researchers have proposed different methods to reduce the current ripple, each of which has its advantages [9,10,11]. At present, the current ripple optimization methods of DC/DC converter mainly include: input parallel output series (IPOS) DC/DC converter, ripple current injection DC/DC converter, resonant ripple absorption DC/DC converter, DC/DC converter using coupled inductor technology, multiple DC/DC converter, etc. Reference [12] studied an IPOS DC/DC converter, which could offset the current ripple to a certain extent, but has the problem of low voltage gain. The DC/DC converter with ripple current injection proposed in [13] artificially injects ripple current at both ends of the inductor to eliminate the ripple current. The ripple suppression effect is good, but the circuit is more complicated. Reference [14] proposed a resonant ripple absorption DC/DC converter that uses the LC devices to generate resonance to optimize the current ripple, but the ripple suppression capability for dynamic loads is poor due to the fixed system parameters. The DC/DC converter with coupled inductor technology [15] replaces the inductor in the traditional DC/DC converter with a coupled inductor. When the coupling coefficient of the coupled inductor is selected reasonably, a better ripple suppression effect can be achieved, however, the switching stress is larger due to the influence of leakage inductance. The multiple DC/DC converter adopts multiple structure and has high power grade. The increase in converter multiplicity can reduce the current ripple, reduce the switching stress, improve the equivalent switching speed, improve the dynamic performance, and then improve the power quality [16,17,18,19,20,21,22,23].

The above current ripple optimization methods of DC/DC converters mainly have the problems of large switching stress and low voltage gain, so they are difficult to be applied to high power energy storage systems, while the traditional multiple DC/DC converters can not only reduce switching stress, but also achieve better current ripple suppression through continuous improvement, so they are widely used in high power energy storage systems [18,19]. Energy storage systems (especially battery energy storage systems) are highly sensitive to current ripples, and excessive current ripples will affect the service life of the system. Reducing the current ripple of the converter is of great significance for improving the quality of the power supply, prolonging the service life of the system. However, the existing research mostly studies improving the circuit structure of the multiplexed DC/DC converter to optimize the current ripple, such as using the coupled inductor instead of the traditional inductor [15] and using the new SiC device [24], the working model of the multiplexed converter is also limited to the fixed multiplicity model, and there are few studies on the influence of changing the parallel multiplicity on the current ripple. In fact, related researches find the multiplicity of parallel circuits also has an important influence on the magnitude of current ripple, and there is always a parallel multiplicity corresponding to the minimum current ripple under different duty cycle [20,21,22,23]. The main contribution of this paper is to propose a current ripple optimization method for bidirectional DC/DC converters by changing the multiplicity of parallel circuits. In reference [25], increasing the switching frequency can reduce the current ripple, but this will inevitably increase the loss and reduce the efficiency. The biggest feature of the method in this paper is that the actual operating multiplicity of the multiplexed DC/DC converter will be dynamically changed according to the duty cycle, as a result, the current ripple is optimized without changing the switching frequency. The improvements are shown as follows: Firstly, the relationship between the current ripple and parallel multiplicity and duty cycle is studied. Secondly, a control method that can change the parallel multiplicity of the DC/DC converter to optimize the current ripple is proposed. Thirdly, considering there are many similar circuits in the multiplex DC/DC converter, there will be the problem of uneven current distribution due to the differences in devices. Although automatic master control overcomes the vulnerability of the master-slave method, where the master is auto-selected by the maximum, it can trigger larger fluctuations in the output current [26]. In this paper, automatic master control and current compensation control are combined, compared with the single automatic master control, this method can better realize the current balance distribution and optimize fluctuations on the output current when the parallel multiple is switching.

This paper is organized as follows: In Section 2, the relationship between the current ripple and parallel multiplicity and duty cycle is deduced, and the basic topology of variable multiplicity bidirectional DC/DC power converter is determined. In Section 3, the average value model and AC small signal model of the system are established. In Section 4, the current compensation control is designed. In Section 5, the simulation model and the experimental platform of variable multiplicity interleaving bidirectional DC/DC power converter is built. The simulation and experiment results show that the optimization of the current ripple of the variable multiplicity bidirectional DC/DC converter is obvious.

2. The Principle of Current Ripple Optimization

Assuming that the bidirectional DC/DC converter operates in Buck mode, the topology of the converter is shown in Figure 1.

The relationship among load-side voltage U_Load, DC bus voltage, and duty cycle D is shown as follows:

$$V_{\mathrm{Load}}=D{V}_{\mathrm{DC}}$$

(1)

For inductance L, the slope of the current rising phase is defined as k_up, and the slope of the current decreasing phase is defined as k_down.

$$\left\{\begin{array}{l}{k}_{\mathrm{up}}=\frac{V_{\mathrm{DC}}-V_{\mathrm{Load}}}{L}\\ k_{\mathrm{down}}=\frac{V_{\mathrm{Load}}}{L}\end{array}\right.$$

(2)

In same-phase driving mode, i_L1, i_L2, i_L3, i_L4, and so on are exactly equal, then the peak-to-peak value of the ripple of total current can be shown as:

$$\Delta i_{\mathrm{Ls}}=\Delta i_{\mathrm{L}1}+\Delta i_{\mathrm{L}2}+\dots +\Delta i_{\mathrm{Ln}}=nD{k}_{\mathrm{up}}T$$

(3)

In the phase-shift control, the relationship between the current and time is established by setting the current i_L1 as the zero point at the initial time of a switching cycle [0,T]. The current i_L1, i_L2, i_L3, i_L4, and so on are shown in Figure 2.

Assuming that the slope of n_down-fold inductor current at the initial stage is k_down, and satisfies n_down + n_up =n. Then the following relationship can be obtained.

$$\left\{\begin{array}{l}⌈\left(1-D\right)n-1⌉=n_{\mathrm{down}}\hfill \\ ⌊Dn+1⌋=n_{\mathrm{up}}\hfill \end{array}\right.$$

(4)

Then, the duty cycle has the following relationship: $1-\frac{n_{\mathrm{down}}+1}{n}\le D\le 1-\frac{n_{\mathrm{down}}}{n}$. Assuming that D is 50%, and $n_{\mathrm{down}}=\frac{n}{2}$ or $n_{\mathrm{down}}=\frac{n-1}{2}$ can be obtained according to the parity of n.

The expression of the first inductance current is shown as:

$$\left\{\begin{array}{ll}{i}_{\mathrm{L}1}=k_{\mathrm{up}}t\hfill & t\in \left[0,DT\right]\hfill \\ i_{\mathrm{L}1}=k_{\mathrm{down}}\left(t-T\right)\hfill & t\in \left[DT,T\right]\hfill \end{array}\right.$$

(5)

The expression of the second inductance current can be shown as:

$$\left\{\begin{array}{ll}{i}_{\mathrm{L}2}=k_{\mathrm{down}}·\left(t-\frac{T}{n}\right)\hfill & t\in \left[0,\frac{T}{n}\right]\hfill \\ i_{\mathrm{L}2}=k_{\mathrm{up}}·\left(t-\frac{T}{n}\right)\hfill & t\in \left[\frac{T}{n},DT+\frac{T}{n}\right]\hfill \\ i_{\mathrm{L}2}=k_{\mathrm{down}}·\left(t-\frac{n+1}{n}T\right)\hfill & t\in \left[DT+\frac{T}{n},T\right]\hfill \end{array}\right.$$

(6)

The expression of the third inductance current can be shown as:

$$\left\{\begin{array}{ll}{i}_{\mathrm{L}3}=k_{\mathrm{down}}·\left(t-\frac{2T}{n}\right)\hfill & t\in \left[0,\frac{2T}{n}\right]\hfill \\ i_{\mathrm{L}3}=k_{\mathrm{up}}·\left(t-\frac{2T}{n}\right)\hfill & t\in \left[\frac{2T}{n},DT+\frac{2T}{n}\right]\hfill \\ i_{\mathrm{L}3}=k_{\mathrm{down}}·\left(t-\frac{n+2}{n}T\right)\hfill & t\in \left[DT+\frac{2T}{n},T\right]\hfill \end{array}\right.$$

(7)

The expression of the n-th inductance current can be shown as:

$$\left\{\begin{array}{ll}{i}_{\mathrm{Ln}}=k_{\mathrm{up}}·\left(t+\frac{T}{n}\right)\hfill & t\in \left[0,DT-\frac{T}{n}\right]\hfill \\ i_{\mathrm{Ln}}=k_{\mathrm{down}}·\left(t-\frac{n-1}{n}T\right)\hfill & t\in \left[DT-\frac{T}{n},\frac{n-1}{n}T\right]\hfill \\ i_{\mathrm{L}3}=k_{\mathrm{up}}·\left(t-\frac{n-1}{n}T\right)\hfill & t\in \left[\frac{n-1}{n}T,T\right]\hfill \end{array}\right.$$

(8)

According to Kirchhoff’s law, the expression of the i_L in a switching cycle can be obtained and can be extended to the n-th cycle, which is shown in (9).

$$\left\{\begin{array}{ccc}\hfill i_{\mathrm{L}}& =\left(n_{\mathrm{up}}{k}_{\mathrm{up}}+n_{\mathrm{down}}{k}_{\mathrm{down}}\right)t+\frac{n_{\mathrm{up}}{k}_{\mathrm{up}}T}{2n}\left(n_{\mathrm{up}}-1\right)\hfill & \hfill \\ \hfill & -\frac{n_{\mathrm{down}}{k}_{\mathrm{down}}T}{2n}\left(n_{\mathrm{down}}+1\right)\hfill & t\in \left[0,DT-\frac{n_{\mathrm{up}}-1}{n}T\right]\hfill \\ \hfill i_{\mathrm{L}}& =\left(\left(n_{\mathrm{up}}-1\right)k_{\mathrm{up}}+\left(n_{\mathrm{down}}+1\right)k_{\mathrm{down}}\right)t\hfill & \hfill \\ \hfill & +\frac{k_{\mathrm{up}}\left(n_{\mathrm{up}}-1\right)\left(n_{\mathrm{up}}-2\right)}{2n}T-\frac{k_{\mathrm{down}}\left(n_{\mathrm{down}}+1\right)\left(n_{\mathrm{down}}+2\right)}{2n}T\hfill & t\in \left[DT-\frac{n_{\mathrm{up}}-1}{n}T,\frac{T}{n}\right]\hfill \\ \hfill i_{\mathrm{L}}& =\left(\left(n_{\mathrm{up}}-1\right)k_{\mathrm{up}}+\left(n_{\mathrm{down}}+1\right)k_{\mathrm{down}}\right)t\hfill & \hfill \\ \hfill & +\frac{k_{\mathrm{up}}\left(n_{\mathrm{up}}-1\right)\left(n_{\mathrm{up}}-4\right)}{2n}T-\frac{k_{\mathrm{down}}\left(n_{\mathrm{down}}+1\right)\left(n_{\mathrm{down}}+4\right)}{2n}T\hfill & t\in \left[DT-\frac{n_{\mathrm{up}}-2}{n}T,\frac{2T}{n}\right]\hfill \\ \hfill & ⋮\hfill & \hfill \\ \hfill i_{\mathrm{L}}& =\left(n_{\mathrm{up}}{k}_{\mathrm{up}}+n_{\mathrm{down}}{k}_{\mathrm{down}}\right)t\hfill & \hfill \\ \hfill & +\frac{n_{\mathrm{up}}{k}_{\mathrm{up}}T}{2n}\left(n_{\mathrm{up}}-2n+1\right)-\frac{n_{\mathrm{down}}{k}_{\mathrm{down}}T}{2n}\left(n_{\mathrm{down}}+2n-1\right)\hfill & t\in \left[\frac{n-1}{n}T,DT+\frac{n_{\mathrm{down}}T}{n}\right]\hfill \\ \hfill i_{\mathrm{L}}& =\left(\left(n_{\mathrm{up}}-1\right)k_{\mathrm{up}}+\left(n_{\mathrm{down}}+1\right)k_{\mathrm{down}}\right)t\hfill & \hfill \\ \hfill & +\frac{k_{\mathrm{up}}\left(n_{\mathrm{up}}-1\right)\left(n_{\mathrm{up}}-2n\right)}{2n}T-\frac{k_{\mathrm{down}}\left(n_{\mathrm{down}}+1\right)\left(n_{\mathrm{down}}+2n\right)}{2n}T\hfill & t\in \left[DT+\frac{n_{\mathrm{down}}T}{n},T\right]\hfill \end{array}\right.$$

(9)

According to (5)–(9) and Figure 2, when phase shift control is applied to the n-fold DC/DC converter, the total ripple of the current flowing through the inductor L is shown in (10):

$$\begin{array}{ll}\Delta i_{\mathrm{Lm}}& =\left(n_{\mathrm{up}}{k}_{\mathrm{up}}+n_{\mathrm{down}}{k}_{\mathrm{down}}\right)·\left(DT-\frac{n_{\mathrm{up}}-1}{n}T\right)\\ & =\frac{T{V}_{\mathrm{DC}}}{L}·\frac{\left[\left(1-D\right)\left(⌊Dn+1⌋\right)-D\left(⌈\left(1-D\right)n-1⌉\right)\right]·\left[Dn-\left(⌊Dn+1⌋\right)+1\right]}{n}\end{array}$$

(10)

Define k_Lm as the ripple coefficient, which is shown in (11).

$$k_{\mathrm{Lm}}=\frac{\left[\left(1-D\right)\left(⌊Dn+1⌋\right)-D\left(⌈\left(1-D\right)n-1⌉\right)\right]·\left[Dn-\left(⌊Dn+1⌋\right)+1\right]}{n}$$

(11)

The expression of (11) can be rewritten to.

$$\Delta i_{\mathrm{Lm}}=\frac{T{V}_{\mathrm{DC}}}{L}·k_{\mathrm{Lm}}$$

(12)

It can be seen from (11) that the ripple coefficient k_Lm is affected by the duty cycle D and the number of parallel multiplicity n. When the bidirectional DC/DC converter operates in Buck mode, the relationship between the ripple coefficient k_Lm, the duty cycle D, and the number of parallel channel multiplicity n is shown in Figure 3. It can be seen from Figure 3 that there is a point where the ripple coefficient k_Lm is 0 when different numbers of parallel multiplicity n and different duty cycle D are taken.

According to (11), the relationship between ripple coefficient k_Lm and duty cycle D can be obtained, shown in Figure 4, when the number of multiplicities is different. It can be seen from Figure 4 that there are n−1 points where the ripple coefficient is zero for the n-multiplicity bidirectional DC/DC power converter.

As can be seen from Figure 4, under the condition of different duty cycles, it is not that the more parallel multiplicity, the smaller the current ripple coefficient. Although the ripple coefficient generally decreases with the increase of parallel multiplicity, considering that too many parallel multiplicities will increase the complexity of the circuit; and more when the number of parallel multiplicities is greater than six, the increase of parallel multiplicity has no obvious effect on the reduction of current ripple. The principle of the variable multiplicity bidirectional DC/DC power converter is to automatically select the working number of parallel multiplicities according to the current duty cycles of the system. The number of parallel multiplicities that should be used for the minimum current ripple when the duty cycle is in the range of 0.1–0.9 is shown in

Table 1. The number of parallel multiplicities corresponding to different duty cycles.

Range of Duty Cycles	Number of Parallel Multiplicities
0.1000~0.1835	6
0.1835~0.2254	5
0.2254~0.2887	4
0.2887~0.3675	6
0.3675~0.4772	5
0.4772~0.5528	6
0.5528~0.6324	5
0.6324~0.7113	6
0.7113~0.7746	4
0.7746~0.8165	5
0.8165~0.9000	6

. For example, when the duty cycle of the system is 0.25, the quadruple parallel structure should be adopted, and the controller outputs four PWM signals with a 90-degree phase shift in each multiplicity.

Figure 5 shows the number of parallel multiplicities that should be taken to minimize the current ripple. For example, when the duty cycle is 0.2, a five-fold parallel structure should be adopted, and the current ripple is the smallest; when the duty cycle is 0.25, a four-fold parallel structure should be adopted. Thus, a curve with the smallest current ripple can be obtained in Figure 5. By calculating the intersection point of the minimum current ripple carve in Figure 5, the corresponding relationship between the parallel multiplicity and the duty range can be obtained, as shown in Table 1.

3. The Model of Variable Multiplicity Interleaving Bidirectional DC/DC Power Converter

3.1. The Mean Value Model

In Figure 6, V_DC is DC side voltage, i_DC is DC side current, i_Lk (1 ≤ k ≤ n) is inductor current, R_k (1 ≤ k ≤ n) is the resistance of the inductor, V_L is inductor voltage, V_Load is load-side voltage, i_Load is load-side current, and D is duty cycle.

The DC side current is shown as:

$$i_{\mathrm{DC}}={\displaystyle \sum _{k=1}^n{D}_{\mathrm{k}}{i}_{\mathrm{Lk}}}$$

(13)

When the lower arm is turned off and the upper arm is turned on, the voltages at both ends of each inductance can be shown as:

$$\left\{\begin{array}{c}{V}_{\mathrm{L}1}=L_1\frac{d{i}_{\mathrm{L}1}}{dt}=V_{\mathrm{DC}}-V_{\mathrm{Load}}-i_{\mathrm{L}1}{R}_1\\ V_{\mathrm{L}2}=L_2\frac{d{i}_{\mathrm{L}2}}{dt}=V_{\mathrm{DC}}-V_{\mathrm{Load}}-i_{\mathrm{L}2}{R}_2\\ ⋮\\ V_{\mathrm{Ln}}=L_{\mathrm{n}}\frac{d{i}_{\mathrm{Ln}}}{dt}=V_{\mathrm{DC}}-V_{\mathrm{Load}}-i_{\mathrm{Ln}}{R}_{\mathrm{n}}\end{array}\right.$$

(14)

When the lower arm is turned on and the upper arm is turned off, the voltages at both ends of each inductance can be shown as:

$$\left\{\begin{array}{c}{V}_{\mathrm{L}1}=L_1\frac{d{i}_{\mathrm{L}1}}{dt}=-V_{\mathrm{Load}}-i_{\mathrm{L}1}{R}_1\\ V_{\mathrm{L}2}=L_2\frac{d{i}_{\mathrm{L}2}}{dt}=-V_{\mathrm{Load}}-i_{\mathrm{L}2}{R}_2\\ ⋮\\ V_{\mathrm{Ln}}=L_{\mathrm{n}}\frac{d{i}_{\mathrm{Ln}}}{dt}=-V_{\mathrm{Load}}-i_{\mathrm{Ln}}{R}_{\mathrm{n}}\end{array}\right.$$

(15)

Because the switching period T_s is very small, it can be considered that V_DC and V_Load are continuous and constant in a switching period. They can be expressed by their average values in a period.

$$\left\{\begin{array}{l}{V}_{\mathrm{DC}}={〈V_{\mathrm{DC}}〉}_{T_{\mathrm{s}}}\\ V_{\mathrm{Load}}={〈V_{\mathrm{Load}}〉}_{T_{\mathrm{s}}}\end{array}\right.$$

(16)

According to the volt-ampere characteristics and volt-second balance principle of the inductor, the average voltage of the inductor shown in (17) in a switching cycle can be obtained by dealing with Equations (14)–(16).

$$\left\{\begin{array}{c}{〈v_{\mathrm{L}1}\left(t\right)〉}_{T_{\mathrm{s}}}=\frac{1}{T_{\mathrm{s}}}\left[{\int }_0^{D_1{T}_{\mathrm{s}}}{v}_{\mathrm{L}1}\left(t\right)dt+{\int }_{D_1{T}_{\mathrm{s}}}^{T_{\mathrm{s}}}{v}_{\mathrm{L}1}\left(t\right)dt\right]=D_1{〈V_{\mathrm{DC}}〉}_{T_{\mathrm{s}}}-{〈V_{\mathrm{Load}}〉}_{T_{\mathrm{s}}}-{〈i_{\mathrm{L}1}〉}_{T_{\mathrm{s}}}{R}_1\\ {〈v_{\mathrm{L}2}\left(t\right)〉}_{T_{\mathrm{s}}}=\frac{1}{T_{\mathrm{s}}}\left[{\int }_0^{D_2{T}_{\mathrm{s}}}{v}_{\mathrm{L}2}\left(t\right)dt+{\int }_{D_2{T}_{\mathrm{s}}}^{T_{\mathrm{s}}}{v}_{\mathrm{L}2}\left(t\right)dt\right]=D_2{〈V_{\mathrm{DC}}〉}_{T_{\mathrm{s}}}-{〈V_{\mathrm{Load}}〉}_{T_{\mathrm{s}}}-{〈i_{\mathrm{L}2}〉}_{T_{\mathrm{s}}}{R}_2\\ ⋮\\ {〈v_{\mathrm{Ln}}\left(t\right)〉}_{T_{\mathrm{s}}}=\frac{1}{T_{\mathrm{s}}}\left[{\int }_0^{D_{\mathrm{n}}{T}_{\mathrm{s}}}{v}_{\mathrm{Ln}}\left(t\right)dt+{\int }_{D_{\mathrm{n}}{T}_{\mathrm{s}}}^{T_{\mathrm{s}}}{v}_{\mathrm{Ln}}\left(t\right)dt\right]=D_{\mathrm{n}}{〈V_{\mathrm{DC}}〉}_{T_{\mathrm{s}}}-{〈V_{\mathrm{Load}}〉}_{T_{\mathrm{s}}}-{〈i_{\mathrm{Ln}}〉}_{T_{\mathrm{s}}}{R}_{\mathrm{n}}\end{array}\right.$$

(17)

According to the volt-ampere characteristics of the capacitor and Kirchhoff’s current law, the average current flowing through the load capacitor in a switching cycle can be obtained.

$$\begin{array}{ll}{〈i_{\mathrm{Load}}\left(t\right)〉}_{T_{\mathrm{s}}}& =C\frac{d{〈v_{\mathrm{Load}}\left(t\right)〉}_{T_{\mathrm{s}}}}{dt}\\ & ={〈i_{\mathrm{L}1}\left(t\right)〉}_{T_{\mathrm{s}}}+{〈i_{\mathrm{L}2}\left(t\right)〉}_{T_{\mathrm{s}}}+\cdots +{〈i_{\mathrm{Ln}}\left(t\right)〉}_{T_{\mathrm{s}}}\end{array}$$

(18)

The characteristic equation of inductance after averaging treatment is.

$$\left\{\begin{array}{c}{〈v_{\mathrm{L}1}\left(t\right)〉}_{T_{\mathrm{s}}}=L_1\frac{d{〈v_{\mathrm{L}1}\left(t\right)〉}_{T_{\mathrm{s}}}}{dt}\\ {〈v_{\mathrm{L}2}\left(t\right)〉}_{T_{\mathrm{s}}}=L_2\frac{d{〈v_{\mathrm{L}2}\left(t\right)〉}_{T_{\mathrm{s}}}}{dt}\\ ⋮\\ {〈v_{\mathrm{Ln}}\left(t\right)〉}_{T_{\mathrm{s}}}=L_{\mathrm{n}}\frac{d{〈v_{\mathrm{Ln}}\left(t\right)〉}_{T_{\mathrm{s}}}}{dt}\end{array}\right.$$

(19)

Substitute Equation (19) into Equation (17), and the following Equation (20) can be obtained.

$$\left\{\begin{array}{c}{L}_1\frac{d{〈v_{\mathrm{L}1}\left(t\right)〉}_{T_{\mathrm{s}}}}{dt}=D_1{〈V_{\mathrm{DC}}〉}_{T_{\mathrm{S}}}-{〈V_{\mathrm{Load}}〉}_{T_{\mathrm{S}}}-{〈i_{\mathrm{L}1}〉}_{T_{\mathrm{S}}}{R}_1\\ L_2\frac{d{〈v_{\mathrm{L}2}\left(t\right)〉}_{T_{\mathrm{s}}}}{dt}=D_2{〈V_{\mathrm{DC}}〉}_{T_{\mathrm{s}}}-{〈V_{\mathrm{Load}}〉}_{T_{\mathrm{s}}}-{〈i_{\mathrm{L}2}〉}_{T_{\mathrm{s}}}{R}_2\\ ⋮\\ L_{\mathrm{n}}\frac{d{〈v_{\mathrm{Ln}}\left(t\right)〉}_{T_{\mathrm{s}}}}{dt}=D_{\mathrm{n}}{〈V_{\mathrm{DC}}〉}_{T_{\mathrm{s}}}-{〈V_{\mathrm{Load}}〉}_{T_{\mathrm{s}}}-{〈i_{\mathrm{Ln}}〉}_{T_{\mathrm{s}}}{R}_{\mathrm{n}}\end{array}\right.$$

(20)

According to Equations (18) and (20), the average value model of the variable multiplicity bidirectional DC/DC power converter in Buck mode can be obtained, as shown in Figure 7.

3.2. The AC Small Signal Model

Equations (17) and (18) obtained in the mean value model are nonlinear equations, so it is complex to solve them directly. However, there are DC components and low-frequency small signal components in the variable, which can be solved in approximate ways. The specific idea is to study the state of the DC/DC power converter near the steady-state working point, where the linearization is satisfied, and the equation can be linearized to separate the DC components and small signal components [27]. Conditions are as follows: the interleaved bidirectional DC/DC power converters should satisfy the low-frequency assumption, small ripple assumption, and small signal assumption in the process of modeling the AC small signal model [27,28].

$$\left|\widehat{x}\left(t\right)\right|\ll \left|X\right|$$

(21)

In Equation (21) [27], $\left|\widehat{x}\left(t\right)\right|$ is the amplitude of the AC component, while $\left|X\right|$ is the amplitude of the DC component.

In a switching cycle, any variable can be divided into DC components and AC small signal components, which is shown in (22).

$$\left\{\begin{array}{cc}{〈i_{\mathrm{Lk}}〉}_{T_{\mathrm{s}}}=I_{\mathrm{Lk}}+{\widehat{i}}_{\mathrm{Lk}}\left(t\right)& \\ {〈D_{\mathrm{k}}〉}_{T_{\mathrm{s}}}=D_{\mathrm{k}}+{\widehat{d}}_{\mathrm{k}}\left(t\right)& \\ {〈v_{\mathrm{Load}}〉}_{T_{\mathrm{s}}}=V_{\mathrm{Load}}+{\widehat{v}}_{\mathrm{Load}}\left(t\right)& \left(1\le k\le 6,k \mathrm{is} \mathrm{integer}\right)\\ {〈v_{\mathrm{DC}}〉}_{T_{\mathrm{s}}}=V_{\mathrm{DC}}+{\widehat{v}}_{\mathrm{DC}}\left(t\right)& \\ {〈i_{\mathrm{Load}}〉}_{T_{\mathrm{s}}}=I_{\mathrm{Load}}+{\widehat{i}}_{\mathrm{Load}}\left(t\right)& \end{array}\right.$$

(22)

Equation (22) being brought into Equation (20) can get (23).

$$\left\{\begin{array}{c}{L}_1\frac{d\left[I_{\mathrm{L}1}+{\widehat{i}}_{\mathrm{L}1}\left(t\right)\right]}{dt}=\left[D_1+{\widehat{d}}_1\left(t\right)\right]\left[V_{\mathrm{DC}}+{\widehat{v}}_{\mathrm{DC}}\left(t\right)\right]-\left[V_{\mathrm{Load}}+{\widehat{v}}_{\mathrm{Load}}\left(t\right)\right]-\left[I_{\mathrm{L}1}+{\widehat{i}}_{\mathrm{L}1}\left(t\right)\right]R_1\\ L_2\frac{d\left[I_{\mathrm{L}2}+{\widehat{i}}_{\mathrm{L}2}\left(t\right)\right]}{dt}=\left[D_2+{\widehat{d}}_2\left(t\right)\right]\left[V_{\mathrm{DC}}+{\widehat{v}}_{\mathrm{DC}}\left(t\right)\right]-\left[V_{\mathrm{Load}}+{\widehat{v}}_{\mathrm{Load}}\left(t\right)\right]-\left[I_{\mathrm{L}2}+{\widehat{i}}_{\mathrm{L}2}\left(t\right)\right]R_2\\ ⋮\\ L_{\mathrm{n}}\frac{d\left[I_{\mathrm{Ln}}+{\widehat{i}}_{\mathrm{Ln}}\left(t\right)\right]}{dt}=\left[D_{\mathrm{n}}+{\widehat{d}}_{\mathrm{n}}\left(t\right)\right]\left[V_{\mathrm{DC}}+{\widehat{v}}_{\mathrm{DC}}\left(t\right)\right]-\left[V_{\mathrm{Load}}+{\widehat{v}}_{\mathrm{Load}}\left(t\right)\right]-\left[I_{\mathrm{Ln}}+{\widehat{i}}_{\mathrm{Ln}}\left(t\right)\right]R_{\mathrm{n}}\end{array}\right.$$

(23)

Ignoring the DC components and the second-order AC small signal components in Equation (23), the above equation can be transformed into the following form.

$$\left\{\begin{array}{c}{L}_1\frac{d{\widehat{i}}_{\mathrm{L}1}\left(t\right)}{dt}=D_1{\widehat{v}}_{\mathrm{DC}}\left(t\right)+V_{\mathrm{DC}}{\widehat{d}}_1\left(t\right)-{\widehat{v}}_{\mathrm{Load}}\left(t\right)-{\widehat{i}}_{\mathrm{L}1}\left(t\right)R_1\\ L_2\frac{d{\widehat{i}}_{\mathrm{L}2}\left(t\right)}{dt}=D_2{\widehat{v}}_{\mathrm{DC}}\left(t\right)+V_{\mathrm{DC}}{\widehat{d}}_2\left(t\right)-{\widehat{v}}_{\mathrm{Load}}\left(t\right)-{\widehat{i}}_{\mathrm{L}2}\left(t\right)R_2\\ ⋮\\ L_{\mathrm{n}}\frac{d{\widehat{i}}_{\mathrm{Ln}}\left(t\right)}{dt}=D_{\mathrm{n}}{\widehat{v}}_{\mathrm{DC}}\left(t\right)+V_{\mathrm{DC}}{\widehat{d}}_{\mathrm{n}}\left(t\right)-{\widehat{v}}_{\mathrm{Load}}\left(t\right)-{\widehat{i}}_{\mathrm{Ln}}\left(t\right)R_{\mathrm{n}}\end{array}\right.$$

(24)

Solving Equations (22) and (18) simultaneously, the following equation can be obtained.

$${\widehat{i}}_{\mathrm{Load}}\left(t\right)=C\frac{d{\widehat{i}}_{\mathrm{Load}}\left(t\right)}{dt}={\widehat{i}}_{\mathrm{L}1}\left(t\right)+{\widehat{i}}_{\mathrm{L}2}\left(t\right)+\cdots +{\widehat{i}}_{\mathrm{Ln}}\left(t\right)$$

(25)

According to Equations (24) and (25), the AC small signal model of the variable multiplicity bidirectional DC/DC power converter in Buck mode can be obtained, which is shown in Figure 8.

4. The Design of Control Strategy for the Variable Multiplicity Interleaving Bidirectional DC/DC Power Converter

4.1. The Analysis of the Open-Loop Characteristic of the Variable Multiplicity Interleaving Bidirectional DC/DC Power Converter

In order to simplify the analysis, it is assumed that the parameters of each corresponding component in the variable multiplicity interleaving bidirectional DC/DC power converter are entirely equal.

$$\left\{\begin{array}{l}{L}_1=L_2=\cdots =L_{\mathrm{n}}=L_{}\hfill \\ L_{\mathrm{L}1}=L_{\mathrm{L}2}=\cdots =L_{\mathrm{Ln}}=L_{\mathrm{L}}\hfill \\ D_1=D_2=\cdots =D_{\mathrm{n}}=D\hfill \\ R_1=R_2=\cdots =R_{\mathrm{n}}=R\hfill \end{array}\right.$$

(26)

The equation of the frequency domain is obtained by the Laplace transform of Equations (24) and (25).

$$\left\{\begin{array}{l}sL{\widehat{i}}_{\mathrm{L}}\left(s\right)=D{\widehat{v}}_{\mathrm{DC}}\left(s\right)+V_{\mathrm{DC}}\widehat{d}\left(s\right)-{\widehat{v}}_{\mathrm{Load}}\left(s\right)-{\widehat{i}}_{\mathrm{L}}\left(s\right)R\\ {\widehat{i}}_{\mathrm{Load}}\left(s\right)=sC{\widehat{v}}_{\mathrm{Load}}\left(s\right)=n{\widehat{i}}_{\mathrm{L}}\left(s\right)\end{array}\right.$$

(27)

In order to control the load voltage V_Load, the input can be assumed to be the ideal voltage source,${\widehat{v}}_{\mathrm{DC}}\left(s\right)=0$. Then, the transfer function G_id(s) between duty cycle d(s) and inductance current i_L(s) can be obtained by simplifying Equation (27).

$$G_{\mathrm{id}}\left(s\right)={\left.\frac{{\widehat{i}}_{\mathrm{L}}\left(s\right)}{\widehat{d}\left(s\right)}\right|}_{{\widehat{v}}_{\mathrm{DC}}\left(s\right)=0}=\frac{sC{V}_{\mathrm{DC}}}{s^{2}LC+sCR+n}$$

(28)

The transfer function G_vd(s) between duty cycle d(s) and load voltage V_Load (s) can be obtained.

$$G_{\mathrm{vd}}\left(s\right)={\left.\frac{{\widehat{v}}_{\mathrm{Load}}\left(s\right)}{\widehat{d}\left(s\right)}\right|}_{{\widehat{v}}_{\mathrm{DC}}\left(s\right)=0}=\frac{n{V}_{\mathrm{DC}}}{s^{2}LC+sCR+n{V}_{\mathrm{DC}}}$$

(29)

The transfer function G_vi(s) between inductance current i_L(s) and load voltage V_Load (s) can be obtained according to Equations (28) and (29).

$$G_{\mathrm{vi}}\left(s\right)=\frac{G_{\mathrm{vd}}\left(s\right)}{G_{\mathrm{id}}\left(s\right)}=\frac{n\left(s^{2}LC+sCR+n{V}_{\mathrm{DC}}\right)}{s^3{C}^{2}L+s^2{C}^{2}R+nsC{V}_{\mathrm{DC}}}$$

(30)

Bring the data in

Table 2. Parameters of variable multiplicity interleaving bidirectional DC/DC converter.

Parameter	Value
DC voltage VDC	30 V
Switching period TS	0.0001 s (10 kHz)
Inductance L	3 mH
Inductance resistance R	0.1 $\mathsf{\Omega }$
Load capacitance C	0.06 F
Initial voltage of load capacitor $V_{\mathrm{C}0}$	5 V
Load current ILoad	6 A
Maximum number of parallel channels $N$	6

into Equation (28), and the transfer function G_id(s) can be obtained.

$$G_{\mathrm{id}}\left(s\right)=\frac{sC{V}_{\mathrm{DC}}}{s^{2}LC+sCR+n}=\frac{6s}{1.8\times {10}^{-4}{s}^2+6\times {10}^{-3}s+n}$$

(31)

The Bode diagram corresponds to G_id(s) when the working multiples are 4, 5, and 6 respectively, as shown in Figure 9. It can be seen from the figure that the shapes of the Bode diagrams under different multiplicities are the same, so the transfer function of the five multiplicities is selected as the research object, and the current compensation network is designed.

As can be seen from Figure 9, the amplitude-frequency characteristic curve is rising in the low-frequency band, there is a large steady-state error in the system. In the middle-frequency band, the crossover frequency is very high, and the system may be affected by switching frequency, harmonics, parasitic oscillation, and so on, unable to work stably. The high-frequency band declines slowly, and the system is vulnerable to high-frequency noise [29].

4.2. The Design of the Current Compensation Network

Due to the output current of variable multiplicity interleaving bidirectional DC/DC power converter being constant, the single current closed-loop control can be adopted, and the control strategy diagram is shown in Figure 10.

When the converter is operating in Buck mode, and the number of working multiplicities is 5, then the transfer function of the current-loop-controlled object can be shown as.

$$G_{\mathrm{id}}\left(s\right)=\frac{6s}{1.8\times {10}^{-4}{s}^2+6\times {10}^{-3}s+5}$$

(32)

Through the analysis of the above Bode diagram, it can be seen that there are at least two integral links in the compensation link so that the amplitude-frequency characteristic curve can decrease at the slope of −20 dB/dec in the low-frequency band. In order to make the system have a strong ability to suppress high-frequency noise, the high-frequency band of the amplitude-frequency characteristic curve should decrease at the slope of 40 dB/dec [29].

The transfer function of the current compensation network is:

$$G_{\mathrm{idc}}\left(s\right)=\frac{K\left(s+{\omega }_{\mathrm{Z}1}\right)\left(s+{\omega }_{\mathrm{Z}2}\right)}{s^2\left(s+{\omega }_{\mathrm{p}}\right)}$$

(33)

The aim of introducing two integral links into the above formula is to make the amplitude-frequency characteristic curve decrease at the slope of −20 dB/dec in the low-frequency band. ${\omega }_{\mathrm{Z}1}$ and ${\omega }_{\mathrm{Z}2}$ are introduced to offset the two conjugate poles in the original transfer function. The ω_p can ensure that the corrected system has enough phase angle margin, at the same time, the amplitude-frequency characteristic curve can decrease at the slope of −40 dB/dec in the high-frequency band to suppress the high-frequency noise [29].

The transfer function of the current compensation link is:

$$G_{\mathrm{idc}}\left(s\right)=\frac{3\times {10}^6\times \left(1.8\times {10}^{-4}{s}^2+6\times {10}^{-3}s+5\right)}{s^2\times \left(s+4500\right)}$$

(34)

The Bode diagram of the current compensation link is shown in Figure 11.

The open-loop transfer function of the corrected system is shown as.

$$G_{\mathrm{A}}\left(s\right)=G_{\mathrm{id}}\left(s\right)G_{\mathrm{idc}}\left(s\right)=\frac{1.8\times {10}^7}{s\left(s+4500\right)}$$

(35)

The open-loop amplitude-frequency characteristic curve of the corrected system is shown in Figure 12. It can be seen from the figure that, after correction, the amplitude-frequency characteristic curve of the corrected system decreases at the slope of 20 dB/dec in the low-frequency band, and the steady-state error of the system is zero; The phase angle margin in the middle-frequency band is 54.2°, which meets the stability requirement. The crossing frequency is $3.24\times {10}^3\mathrm{rad}/\mathrm{s}$ ($f_{\mathrm{c}}\approx 515.7\mathrm{Hz}$). The amplitude-frequency characteristic curve of the corrected system decreases at the slope of −40 dB/dec in the high-frequency band, and the system has a good ability to suppress the high-frequency noise. To sum up, the corrected system meets the design requirements.

4.3. The Simulation of the Variable Multiplicity Interleaving Bidirectional DC/DC Power Converter

Based on the analysis of the previous chapters, the simulation model is built, and then the parameters in Table 2 are brought into the model. The simulation model is operated to extract the current ripples of different parallel numbers when the duty cycle is 0.25, 0.33, 0.40, and 0.5, which are shown in Figure 13, Figure 14, Figure 15 and Figure 16 (In each Figure, a is the current ripples in four parallel multiplicities; b is the current ripples in five parallel multiplicities; c is the current ripples in six parallel multiplicities.). Figure 13 shows the output current ripples when the duty cycle is 0.25, and the current ripple is the smallest when the parallel number is four; Figure 14 shows the output current ripples when the duty cycle is 0.33, and the current ripple is the smallest when the parallel number is six; Figure 15 shows the output current ripples when the duty cycle is 0.4, and the current ripple is the smallest when the parallel number is five; Figure 16 shows the output current ripples when the duty cycle is 0.50, and the current ripple is the smallest when the parallel number is six. The above simulation results are consistent with the conclusion in Table 1, which is obtained from the previous analysis, this is when the duty cycle is different, the number of parallel multiplicities with the smallest current ripples is different, and so the DC/DC converter needs to flexibly choose to turn on or turn off some parallel branches according to the current ripple optimization law.

5. The Experiment and Results

5.1. Experimental Platform

The experimental platform is shown in Figure 17, it can be divided into a control module, power module, output module, power supply, and programmable load. The TMS320F28377 microcontroller is used to control the whole system, and the XC3S500E-PQ208 is used to generate the PWM signal with the specific phase shift angle. The PWM signal is transmitted to the power module through the optical fiber. In the experiment, the 30 V bus voltage is generated by the DC stabilized power supply, the load capacitance C is replaced by a programmable load, the switching frequency is set to 10 KHz, the value of filter inductance is 3 mH, the output current is 6 A.

5.2. The Experimental Results of the Current Ripple Optimization in Variable Channel Interleaving Bidirectional DC/DC Power Converter

The current ripples of the 6 A output current of the DC-DC converter are shown in Figure 18. Figure 18a–l represents the current ripples which are corresponding to different multiplicities in parallel when the duty cycles are 0.25, 0.33, 0.4, and 0.5, respectively. As can be seen in Figure 18a–c, when the duty cycle is 0.25, the maximum current ripples are 80 mA, 100 mA, and 120 mA when the number of parallel multiplicities is 4, 5, and 6, respectively. As can be seen in Figure 18d–f, when the duty cycle is 0.33, the maximum current ripples are 160 mA, 145 mA, and 65 mA, when the number of parallel multiplicities is 4, 5, and 6, respectively. As can be seen in Figure 18g–y, when the duty cycle is 0.4, the maximum current ripples are 200 mA, 90 mA, and 100 mA, when the number of parallel multiplicities is 4, 5, and 6, respectively. As can be seen in Figure 18j–l, when the duty cycle is 0.5, the maximum current ripples are 130 mA, 140 mA, and 120 mA when the number of parallel multiplicities is 4, 5, and 6, respectively.

All optimization results of current ripples under different duty cycles and parallel multiplicities in Figure 18 are identical to not only the simulation results above but also the analytical results in Table 1, which demonstrate that the optimization method proposed in this paper is precise and practical.

The three pictures of the same line in Figure 18 clearly show the size of the current ripple under a different number of parallel channels with the same duty cycle. By extracting the data in Figure 18,

Table 3. Output current ripples of DC-DC converter with different duty cycles under the same output current.

Duty Cycles	The Maximum Current Ripple of the Number of N Multiple Parallel Channels/mA			The Number of Parallel Channels to Be Used
	N = 4	N = 5	N = 6
0.25	80	100	120	4
0.33	160	145	65	6
0.40	200	90	100	5
0.50	130	140	120	6

can be obtained. Compared with Figure 18, Table 3 is more intuitive and convincing in numerical representation. Table 3 intuitively illustrates the number of parallel branches that should be taken to minimize the current ripple under experimental conditions.

In order to simplify the analysis process, only the current ripples corresponding to duty cycles 0.25 and 0.5 are adopted. Figure 19a–f shows the current ripples of the first three channels when the parallel multiplicity is 4, 5, and 6. It can be seen that the larger the duty cycle, the longer the rise time and the shorter the fall time, the peak value of the ripple peak of a single brand is also increasing, and the total output current ripple is composed of multiple brand parallel outputs, so the total output current ripple cannot be judged only by the size of a single brand current ripple. The current of each channel is not completely coincident, mainly due to the measurement error of the sensor. Even if the current sharing control method is taken, the current imbalance caused by the inconsistent parameters of each channel cannot be fully compensated.

6. Conclusions

The main contribution of this paper is to propose a variable multiplicity control method of multiple interleaving bidirectional DC/DC power converters to optimize the current ripple, that is, dynamically adjust the number of parallel multiplicities in the actual operation of the circuit according to the duty cycles, so that the output current ripple is as small as possible. First, the relationship between the current ripple and the number of parallel multiplicities and the duty cycle is analyzed and deduced and the switching logic that can generate the minimum current ripple is designed. Second, the average value model and the AC small signal model of variable multiplicity interleaving bidirectional DC/DC power converter are established, and the transfer function of the system is obtained. Third, according to the transfer function of the system, the control system of the converter is designed. Simulation and experimental results show that the control method proposed in this paper can effectively further reduce the current ripple of the traditional multiple DC/DC converter, and to a certain, reduce the switching loss caused by a blind increase of switching frequency to optimize current ripple, so it is of great significance. All in all, the current ripple optimization algorithm proposed in this paper is suitable for occasions that require low current ripple, such as battery energy storage systems, electric vehicles, etc. However, due to multiple interleaving DC/DC converters using more parallel branches, the cost is relatively high. Further research on improving reliability and reducing costs is needed in the future.