An Efficient Algorithm and Architecture for the VLSI Implementation of Integer DCT That Allows an Efficient Incorporation of the Hardware Security with a Low Overhead

Abstract

In this paper, we propose a new hardware algorithm for an integer based discrete cosine transform (IntDCT) that was designed to allow an efficient VLSI implementation of the discrete cosine transform using the systolic array architectural paradigm. The proposed algorithm demonstrates multiple benefits specific to integer transforms with efficient hardware implementation and sufficient precision in approximating irrational transform coefficients for practical applications. The proposed integer DCT algorithm can be efficiently restructured into five regular and modular computational structures of lengths of four and one of length two called pseudo-cycle convolutions which translate into efficient VLSI implementations using systolic arrays. Moreover, besides an efficient VLSI implementation with high-speed performances due to the parallel decomposition of the proposed integer DCT algorithm, the proposed VLSI architecture uses a tag control mechanism that facilitates the integration of an obfuscation technique that significantly improves the hardware security with low overheads, maintaining all the implementation performances.

1. Introduction

Multimedia applications involve processing a huge amount of data at a high-speed, thus introducing important challenges to research, especially in mobile devices where the resource usage is constrained. In this context, important research areas that have been developed include image compression, data transmission or Internet of Things, and more. These challenges increase even more for real-time applications, characterized by difficult-to-meet constraints on area, speed, throughput, and power. Audio and video conferencing platforms, digital libraries and archives, remote assistance, and telemedicine are typical applications that push for important developments in this research area. For real-time multimedia applications to support the exigent requirements regarding area, power, and speed performances, the efficient use of the VLSI technology based on reconfigurable FPGA circuits or application-specific integrated circuits (ASICs) is becoming mandatory.

An ubiquitously used transform in data compression and transmission, due to it representing a good approximation of the statistically optimal Karhunen–Loeve transform [1], is the discrete cosine transform (DCT). To accommodate the computationally intensive forward DCT (DCT II) for use in real-time applications, the development of new algorithms or the reformulation of existing ones has become a necessity.

To develop efficient VLSI algorithms, it is important to take into consideration the data flow in the algorithm in the design of new algorithms or the reformulation of existing ones. The performances of a VLSI algorithm are determined even more by the communication complexity and structure and then by its arithmetic complexity. Hence, using regular and modular computational structures can lead to good hardware implementation solutions for the discrete transforms [2,3,4,5,6,7] using systolic arrays [8] or distributed arithmetic [9]. As can be seen, this approach offers reduced hardware complexity with low I/O cost and high speed with good topological features.

It was shown that the VLSI implementation advantages specific to circular correlation or cycle convolution can be extended to other related structures such as pseudo-cycle convolution, band-correlation, skew-circular, and pseudo-circular correlations.

The main VLSI implementations’ advantages of these regular and modular computational structures stem from their particular data flow management, consisting of efficient input/output and data transfer operations, which are successfully utilized in distributed arithmetic systems and systolic arrays.

One important problem in the VLSI implementation of the DCT is that some elements of the transform kernel are irrational, which increases the computational cost and may cause a mismatch between the encoder and decoder as well as drifting errors.

Integer discrete cosine transform (Int-DCT) [10,11] was designed to solve this problem and has been adopted in the recent coding standards such as H.264/Advanced Video Coding (AVC) [12], Audio and Video Streaming (AVS) [13], Video Codec-1 (VC-1) [14], and high-efficiency video coding (HEVC) [15], which uses 4-point to 32-point Int-DCT.

Several 8-point approximated DCTs are proposed in [16,17,18] with different techniques to derive efficient transforms with a lower number of required additions. Larger transforms such as 16-point DCT can offer better performances as more coding gains compared with 4-point or 8-point transforms [19,20,21].

The importance of protecting designs and products has increased nowadays such that the search for measures to protect intellectual property (IP) from counterfeit, malicious alteration, or reverse engineering using hardware security techniques has intensified.

While there are several hardware security solutions, one of the most efficient solutions for improving hardware security is the obfuscation [22,23,24,25,26,27,28].

In this paper, we describe a new integer algorithm for DCT suitable for an efficient hardware implementation of DCT. One aspect of the obtained VLSI algorithm is the possibility to have only multiplications with small integer constants that have low complexity of signed digit representations and can be realized with adders and shift operations. The proposed integer algorithm was decomposed into five pseudo-cycle convolutions of length $N=4$ and one pseudo-cycle convolution of length $N=2$ that can be computed in parallel, leading to a reduced hardware complexity with high processing speeds. The obtained computational structures present the advantages of the cyclic convolution and circular correlation structures-based VLSI. Moreover, the particular tag control mechanism facilitates the efficient integration of the obfuscation technique based on the method introduced in [27].

The main contributions of the paper can be summarized as follows:

• A new Integer DCT matrix is defined which has a high precision and can be efficiently implemented in VLSI;
• The proposed algorithm can be reformulated in a such way that it can be decomposed into five pseudo-cycle convolutions of length four and one of length two;
• It was shown that the derived computational structures can be efficiently implemented using systolic arrays;
• The proposed VLSI algorithm and architecture can efficiently incorporate the obfuscation technique with low overheads and with no impact on the speed performances.

The rest of the paper is organized as follows: in Section 2 we present a new algorithm for Integer DCT with a reduced computational complexity that is using a regular and modular computational structure called pseudo-cycle convolution that is well adapted for an efficient VLSI implementation with similar advantages as cycle-convolution. In Section 3, we present the derived VLSI architecture that emphasizes the advantages of the new Integer DCT algorithm from a VLSI implementation point of view. In Section 4, we discuss the obtained results and it has been shown that a significant reduction in the hardware complexity can be obtained using the proposed Integer DCT algorithm and that it allows the incorporation of the obfuscation technique with low overheads. In Section 5, we are presenting the conclusions.

2. A New VLSI Algorithm for Integer DCT

The 1-D discrete cosine transform (DCT) for a real input sequence $x\left(i\right),i=\overline{0,N-1}$ is defined as:

$$Y\left(k\right)=\sqrt{\frac{2}{N}}\cdot {\sum }_{i=0}^{N-1}x\left(i\right)\cdot \mathit{cos}[(2i+1)k\alpha ], \mathrm{for} k=\overline{0,N-1}$$

(1)

$$\mathrm{with} \alpha =\frac{\pi }{2N}$$

(2)

The multiplication with the constant $\sqrt{\frac{2}{N}}$ can be performed at the end of the VLSI array. An even better solution is to integrate this multiplier in the final design into the quantization stage. For the rest of this work, the multiplication constant will not be taken into consideration.

Using ideas such as those in [10,11], the matrix used for integer DCT is:

$${\mathrm{T}}_{16}=\left[\left.\begin{array}{rrrrrrrr}64& 64& 64& 64& 64& 64& 64& 64\\ 90& 87& 80& 70& 57& 43& 25& 9\\ 89& 75& 50& 18& -18& -50& -75& -89\\ 87& 57& 9& -43& -80& -90& -70& -25\\ 83& 36& -36& -83& -83& -36& 36& 83\\ 80& 9& -70& -87& -25& 57& 90& 43\\ 75& -18& -89& -50& 50& 89& 18& -75\\ 70& -43& -87& 9& 90& 25& -80& -57\\ 64& -64& -64& 64& 64& -64& -64& 64\\ 57& -80& -25& 90& -9& -87& 43& 70\\ 50& -89& 18& 75& -75& -18& 89& -50\\ 43& -90& 57& 25& -87& 70& 9& -80\\ 36& -83& 83& -36& -36& 83& -83& 36\\ 25& -70& 90& -80& 43& 9& -57& 87\\ 18& -50& 75& -89& 89& -75& 50& -18\\ 9& -25& 43& -57& 70& -80& 87& -90\end{array}\right|\begin{array}{rrrrrrrr}64& 64& 64& 64& 64& 64& 64& 64\\ -9& -25& -43& -57& -70& -80& -87& -90\\ -89& -75& -50& -18& 18& 50& 75& 89\\ 25& 70& 90& 80& 43& -9& -57& -87\\ 83& 36& -36& -83& -83& -36& 36& 83\\ -43& -90& -57& 25& 87& 70& -9& -80\\ -75& 18& 89& 50& -50& -89& -18& 75\\ 57& 80& -25& -90& -9& 87& 43& -70\\ 64& -64& -64& 64& 64& -64& -64& 64\\ -70& -43& 87& 9& -90& 25& 80& -57\\ -50& 89& -18& -75& 75& 18& -89& 50\\ 80& -9& -70& 87& -25& -57& 90& -43\\ 36& -83& 83& -36& -36& 83& -83& 36\\ -87& 57& -9& -43& 80& -90& 70& -25\\ -18& 50& -75& 89& -89& 75& -50& 18\\ 90& -87& 80& -70& 57& -43& 25& -9\end{array}\right]$$

(3)

We have designed a new integer DCT that can be efficiently implemented using the systolic array architectural paradigm given by the following equation:

$$\begin{array}{l}{\left[\begin{array}{cccccccccccccccc}Y\left(0\right)& Y\left(1\right)& Y\left(2\right)& Y\left(3\right)& Y\left(4\right)& Y\left(5\right)& Y\left(6\right)& Y\left(7\right)& Y\left(8\right)& Y\left(9\right)& Y\left(10\right)& Y\left(11\right)& Y\left(12\right)& Y\left(13\right)& Y\left(14\right)& Y\left(15\right)\end{array}\right]}^T\\ =\frac{1}{128}\times \left[\left.\begin{array}{rrrrrrrr}128& 128& 128& 128& 128& 128& 128& 128\\ 127& 122& 113& 100& 81& 60& 37& 13\\ 125& 106& 71& 25& -25& -71& -106& -125\\ 122& 81& 13& -60& -113& -127& -100& -37\\ 118& 48& -48& -118& -118& -48& 48& 118\\ 113& 13& -100& -122& -37& 81& 127& 60\\ 106& -25& -125& -71& 71& 125& 25& -106\\ 100& -60& -122& 13& 127& 37& -113& -81\\ 90& -90& -90& 90& 90& -90& -90& 90\\ 81& -113& -37& 127& -13& -122& 60& 100\\ 71& -125& 25& 106& -106& -25& 125& -71\\ 60& -127& 81& 37& -122& 100& 13& -113\\ 48& -118& 118& -48& -48& 118& -118& 48\\ 37& -100& 127& -113& 60& 13& -81& 122\\ 25& -71& 106& -125& 125& -106& 71& -25\\ 13& -37& 60& -81& 100& -113& 122& -127\end{array}\right|\begin{array}{rrrrrrrr}128& 128& 128& 128& 128& 128& 128& 128\\ -13& -37& -60& -81& -100& -113& -122& -127\\ -125& -106& -71& -25& 25& 71& 106& 125\\ 37& 100& 127& 113& 60& -13& -81& -122\\ 118& 48& -48& -118& -118& -48& 48& 118\\ -60& -127& -81& 37& 122& 100& -13& -113\\ -106& 25& 125& 71& -71& -125& -25& 106\\ 81& 113& -37& -127& -13& 122& 60& -100\\ 90& -90& -90& 90& 90& -90& -90& 90\\ -100& -60& 122& 13& -127& 37& 113& -81\\ -71& 125& -25& -106& 106& 25& -125& 71\\ 113& -13& -100& 122& -37& -81& 127& -60\\ 48& -118& 118& -48& -48& 118& -118& 48\\ -122& 81& -13& -60& 113& -127& 100& -37\\ -25& 71& -106& 125& -125& 106& -71& 25\\ 127& -122& 113& -100& 81& -60& 37& -13\end{array}\right]\\ \cdot {\left[\begin{array}{cccccccccccccccc}x\left(0\right)& x\left(1\right)& x\left(2\right)& x\left(3\right)& x\left(4\right)& x\left(5\right)& x\left(6\right)& x\left(7\right)& x\left(8\right)& x\left(9\right)& x\left(10\right)& x\left(11\right)& x\left(12\right)& x\left(13\right)& x\left(14\right)& x\left(15\right)\end{array}\right]}^T\end{array}$$

(4)

To obtain Equation (4), a multi-criterial optimization must be used. A linear integer optimization has been used to search an optimum solution according to the following criteria:

• closeness to the original DCT;
• orthogonality of the basis vector;
• low implementation costs.

These criteria have also been applied in [29,30], but in our case the optimization process was guided to obtain a solution suitable for a systolic array implementation. We have only considered the solution that can lead to a systolic array implementation and we have disregarded the other possible solutions during the optimization process. Naturally, this part of the optimization process cannot be conducted automatically and the know-how of a designer with strong expertise in systolic array architectures is required.

As it can be seen from Equation (4), the matrix coefficients have specific properties, such as symmetric and anti-symmetric properties, that can be exploited for efficient VLSI implementation using systolic arrays.

The obtained integer transform has good accuracy that even outperforms the standard form described by Equation (3), as can be seen in Figure 1.

Figure 1 illustrates the ability of the proposed transform to retain the important features of an image (Lena in our tests) by computing the peak signal-to-noise ratio (PSNR) between the original and the reconstructed image. By varying the number of retained coefficients from low (corresponding to the best image compression) to high (corresponding to the best image quality), one can find the optimum trade-off between compression and quality. For the representation in Figure 1, the same test image and number of bits were used in the simulations to compute the PSNR for the two transforms from Equations (3) and (4).

As shown in Figure 1, the PSNR resulting from using the proposed IntDCT transform, as defined in (4), is identical to the PSNR resulting from using the transform from (3) when the number of retained coefficients is small. This can be explained by the fact that most of the energy is concentrated at low frequencies, for which both Equations (3) and (4) produce identical results. On the other hand, by taking all the coefficients into consideration when reconstructing the original image, the proposed transform in (4) achieves better results with a PSNR of 68 dB compared to 63 dB for the IntDCT from [10], as described by Equation (3).

To obtain an efficient VLSI algorithm, we reformulated (4) by appropriately restructuring and permuting the input and output sequences. Thus, we obtained a parallel form of the algorithm that uses 5 quasi-cycle convolution structures that can operate concurrently.

We introduce the following notations:

$$\begin{gathered} x_p\left(i\right)=x\left(i\right)+x\left(N-1-i\right),i=\overline{0,N/2-1} \\ {x}_m\left(i\right)=x\left(i\right)-x\left(N-1-i\right),i=\overline{0,N/2-1} \\ {x}_{pp}\left(i\right)=x_p\left(i\right)+x_p\left(N/2-1-i\right),i=\overline{0,N/4-1} \\ {x}_{pm}\left(i\right)=x_p\left(i\right)-x_p\left(N/2-1-i\right),i=\overline{0,N/4-1} \end{gathered}$$

(5)

Thus, we can write Equation (4) in a matrix–vector product as follows:

$$\left[\begin{array}{l}{Y}_a\left(1\right)\\ Y_a\left(9\right)\\ Y_a\left(15\right)\\ Y_a\left(7\right)\end{array}\right]=\left[\begin{array}{rrrr}{x}_m\left(0\right)& x_m\left(4\right)& x_m\left(7\right)& x_m\left(3\right)\\ x_m\left(3\right)& x_m\left(0\right)& -x_m\left(4\right)& x_m\left(7\right)\\ -x_m\left(7\right)& -x_m\left(3\right)& x_m\left(0\right)& x_m\left(4\right)\\ x_m\left(4\right)& -x_m\left(7\right)& x_m\left(3\right)& x_m\left(0\right)\end{array}\right]\cdot \left[\begin{array}{r}127\\ 81\\ 13\\ 100\end{array}\right]$$

(6)

$$\left[\begin{array}{l}{Y}_b\left(1\right)\\ Y_b\left(9\right)\\ Y_b\left(15\right)\\ Y_b\left(7\right)\end{array}\right]=\left[\begin{array}{rrrr}{x}_m\left(1\right)& x_m\left(2\right)& x_m\left(6\right)& x_m\left(5\right)\\ -x_m\left(5\right)& -x_m\left(1\right)& -x_m\left(2\right)& x_m\left(6\right)\\ x_m\left(6\right)& -x_m\left(5\right)& -x_m\left(1\right)& x_m\left(2\right)\\ -x_m\left(2\right)& -x_m\left(6\right)& x_m\left(5\right)& -x_m\left(1\right)\end{array}\right]\cdot \left[\begin{array}{r}122\\ 113\\ 37\\ 60\end{array}\right]$$

(7)

By scaled summing the results of the auxiliary sequences $Y_a\left(k\right)$ and $Y_b\left(k\right)$ with $k\in \{1,9,15,7\}$ from Equations (6) and (7), a subset of the output sequence is obtained:

$$\left[\begin{array}{l}Y\left(1\right)\\ Y\left(9\right)\\ Y\left(15\right)\\ Y\left(7\right)\end{array}\right]=\frac{1}{128}\times \left[\begin{array}{l}{Y}_a\left(1\right)\\ Y_a\left(9\right)\\ Y_a\left(15\right)\\ Y_a\left(7\right)\end{array}\right]+\left[\begin{array}{l}{Y}_b\left(1\right)\\ Y_b\left(9\right)\\ Y_b\left(15\right)\\ Y_b\left(7\right)\end{array}\right]$$

(8)

$$\left[\begin{array}{l}{Y}_a\left(3\right)\\ Y_a\left(5\right)\\ Y_a\left(13\right)\\ Y_a\left(11\right)\end{array}\right]=\left[\begin{array}{rrrr}-x_m\left(5\right)& x_m\left(1\right)& x_m\left(2\right)& -x_m\left(6\right)\\ x_m\left(6\right)& x_m\left(5\right)& x_m\left(1\right)& -x_m\left(2\right)\\ x_m\left(2\right)& -x_m\left(6\right)& x_m\left(5\right)& -x_m\left(1\right)\\ -x_m\left(1\right)& x_m\left(2\right)& x_m\left(6\right)& x_m\left(5\right)\end{array}\right]\cdot \left[\begin{array}{r}127\\ 81\\ 13\\ 100\end{array}\right]$$

(9)

$$\left[\begin{array}{l}{Y}_b\left(3\right)\\ Y_b\left(5\right)\\ Y_b\left(13\right)\\ Y_b\left(11\right)\end{array}\right]=\left[\begin{array}{rrrr}{x}_m\left(0\right)& -x_m\left(4\right)& -x_m\left(7\right)& -x_m\left(3\right)\\ -x_m\left(3\right)& x_m\left(0\right)& -x_m\left(4\right)& -x_m\left(7\right)\\ x_m\left(7\right)& -x_m\left(3\right)& x_m\left(0\right)& x_m\left(4\right)\\ -x_m\left(4\right)& -x_m\left(7\right)& x_m\left(3\right)& x_m\left(0\right)\end{array}\right]\cdot \left[\begin{array}{r}122\\ 113\\ 37\\ 60\end{array}\right]$$

(10)

In a similar manner, another subset of the output sequence is obtained by combining the auxiliary results from Equations (9) and (10):

$$\left[\begin{array}{l}Y\left(3\right)\\ Y\left(5\right)\\ Y\left(13\right)\\ Y\left(11\right)\end{array}\right]=\frac{1}{128}\times \left[\begin{array}{l}{Y}_a\left(3\right)\\ Y_a\left(5\right)\\ Y_a\left(13\right)\\ Y_a\left(11\right)\end{array}\right]+\left[\begin{array}{l}{Y}_b\left(3\right)\\ Y_b\left(5\right)\\ Y_b\left(13\right)\\ Y_b\left(11\right)\end{array}\right]$$

(11)

The subset $Y\left(k\right)$ with $k\in \{2,6,14,10\}$ of the output sequence is obtained directly from the matrix vector product below:

$$\left[\begin{array}{l}Y\left(2\right)\\ Y\left(6\right)\\ Y\left(14\right)\\ Y\left(10\right)\end{array}\right]=\frac{1}{128}\times \left[\begin{array}{rrrr}{x}_{pm}\left(0\right)& x_{pm}\left(1\right)& x_{pm}\left(3\right)& x_{pm}\left(2\right)\\ -x_{pm}\left(2\right)& x_{pm}\left(0\right)& -x_{pm}\left(1\right)& -x_{pm}\left(3\right)\\ -x_{pm}\left(3\right)& x_{pm}\left(2\right)& x_{pm}\left(0\right)& -x_{pm}\left(1\right)\\ -x_{pm}\left(1\right)& x_{pm}\left(3\right)& x_{pm}\left(2\right)& x_{pm}\left(0\right)\end{array}\right]\cdot \left[\begin{array}{r}125\\ 106\\ 25\\ 71\end{array}\right]$$

(12)

The particular structure of the matrices in Equations (6), (7), (9), (10) and (12), where all the elements along the main diagonal of the matrix or parallel to the main diagonal of the matrix are the same with the exception of the sign, is called a quasi-cycle convolution. This computational structure has an important advantage from a VLSI implementation point of view as it can be efficiently implemented using the systolic array architectural paradigm. As already known, this architecture is very appropriate for efficient VLSI implementation.

The elements $Y\left(4\right)$ and $Y\left(12\right)$ of the output sequence are obtained as follows:

$$\left[\begin{array}{l}Y\left(4\right)\\ Y\left(12\right)\end{array}\right]=\frac{1}{128}\times \left[\begin{array}{rr}118& 48\\ 48& -118\end{array}\right]\cdot \left[\begin{array}{r}{x}_{pp}\left(0\right)-x_{pp}\left(3\right)\\ x_{pp}\left(1\right)-x_{pp}\left(2\right)\end{array}\right]$$

(13)

The matrix–vector product from Equation (13) has the same specific form of Equations (6), (7), (9), (10) and (12) but at half the length.

Finally, we can compute $Y\left(0\right)$ and $Y\left(8\right)$ using the following equation:

$$\left[\begin{array}{l}Y\left(0\right)\\ Y\left(8\right)\end{array}\right]=\frac{1}{128}\times \left[\begin{array}{rr}128& 128\\ 90& -90\end{array}\right]\cdot \left[\begin{array}{r}{x}_{pp}\left(0\right)+x_{pp}\left(3\right)\\ x_{pp}\left(1\right)+x_{pp}\left(2\right)\end{array}\right]$$

(14)

or, written explicitly:

$$Y\left(0\right)=x_{pp}\left(0\right)+x_{pp}\left(3\right)+x_{pp}\left(1\right)+x_{pp}\left(2\right)$$

(15)

$$Y\left(8\right)=\frac{45}{64}\times \left\{x_{pp}\left(0\right)+x_{pp}\left(3\right)-\left[x_{pp}\left(1\right)+x_{pp}\left(2\right)\right]\right\}$$

(16)

Therefore, beside the advantages of integer algorithms stemming from efficient implementations of the multipliers, the proposed reformulation allows for an efficient hardware implementation using systolic arrays. Moreover, the obtained algorithm based on quasi-cycle convolution structures and its associated VLSI architecture facilitates the integration of the obfuscation technique.

3. The Proposed VLSI Architecture for the New Integer DCT Algorithm

3.1. Designing the VLSI Architecture

Using the method presented in [31], based on the data dependence graph and the control mechanism described in [32] based on tag bits, Equations (6), (7), (9), (10) and (12) can be mapped to five linear systolic arrays consisting of four processing elements. Furthermore, Equation (13) can be mapped on a similar systolic array that has only two processing elements. The data dependence graph (DDG) was used as the main tool in our design flow together with an appropriate control mechanism based on control tags.

Figure 2 presents the operation of the processing elements of the implemented systolic arrays. All the processing elements have the same functionality, which is an important advantage from a VLSI implementation point of view. Each processing element contains a multiplier by a constant and an adder/subtracter. In Figure 2, sign is a tag control bit that selects the sign of the operation.

The linear systolic arrays from Figure 3, Figure 4, Figure 5, Figure 6 and Figure 7 implement four pseudo-cycle convolution structures with the same structure and which have the same length $N=4$. The linear systolic array from Figure 8 also implements a pseudo-cycle convolution of length $N=2$. It can be observed that each processing element contains one multiplier with a small constant that can be implemented using only two adders and shifters, with only one exception where three adders are used to implement the multiplication with such small constants. Thus, the complexity of the processing elements and the delay introduced by these multipliers are significantly reduced.

Equation (6) was mapped on the systolic array from Figure 3. It can be seen that the systolic array from Figure 3 computes the auxiliary input sequences $x_m\left(3\right)$, $x_m\left(7\right)$, $x_m\left(4\right),$ and $x_m\left(0\right)$ and the auxiliary outputs $Y_a\left(1\right)$, $Y_a\left(9\right)$, $Y_a\left(15\right)$, and $Y_a\left(7\right)$.

Equation (7) was mapped on the systolic array from Figure 4. The systolic array from Figure 4 uses the auxiliary input sequences $x_m\left(5\right)$, $x_m\left(6\right)$, $x_m\left(2\right)$, and $x_m\left(1\right)$ to compute the auxiliary outputs $Y_b\left(1\right)$, $Y_b\left(9\right)$, $Y_b\left(15\right)$, and $Y_b\left(7\right)$.

Equation (9) was mapped on the systolic array from Figure 5. The systolic array from Figure 5 uses the auxiliary input sequences $x_m\left(6\right)$, $x_m\left(2\right)$, $x_m\left(1\right)$, and $x_m\left(5\right)$ to compute the auxiliary outputs $Y_a\left(3\right)$, $Y_a\left(5\right)$, $Y_a\left(13\right)$, and $Y_a\left(11\right)$.

Equation (10) was mapped on the systolic array from Figure 6. The systolic array from Figure 6 uses the auxiliary input sequences $x_m\left(3\right)$, $x_m\left(7\right)$, $x_m\left(4\right)$, and $x_m\left(0\right)$ to compute the auxiliary outputs $Y_b\left(3\right)$, $Y_b\left(5\right)$, $Y_b\left(13\right)$, and $Y_b\left(11\right)$.

Equation (12) was mapped on the systolic array from Figure 7. The systolic array from Figure 7 uses the auxiliary input sequences $x_{pm}\left(2\right)$, $x_{pm}\left(3\right)$, $x_{pm}\left(1\right)$, and $x_{pm}\left(0\right)$ to compute the output sequences $Y\left(2\right)$, $Y\left(6\right)$, $Y\left(14\right)$, and $Y\left(10\right)$.

Equation (13) was mapped on the systolic array from Figure 7. The systolic array from Figure 7 consists of two processing elements and uses the auxiliary input sequences $x_{pp}\left(0\right)-x_{pp}\left(3\right)$ and $x_{pp}\left(1\right)-x_{pp}\left(2\right)$ to generate the output sequences $Y\left(4\right)$ and $Y\left(12\right)$.

In addition to the hardware core consisting of the systolic arrays from Figure 3, Figure 4, Figure 5, Figure 6, Figure 7 and Figure 8, we use two auxiliary stages that perform pre-processing and post-processing of the data. The first stage computes the auxiliary input sequences $x_m\left(i\right)$, $x_p\left(i\right)$, $x_{pm}\left(i\right)$, and $x_{pp}\left(i\right)$, as defined in Equations (3), $x_{pp}\left(0\right)+x_{pp}\left(3\right)$, $x_{pp}\left(1\right)+x_{pp}\left(2\right)$ $x_{pp}\left(0\right)-x_{pp}\left(3\right)$, and $x_{pp}\left(1\right)-x_{pp}\left(2\right)$. The second stage is used to compute the output sequence $Y\left(k\right)$ using Equations (8) and (11) and $Y\left(0\right)$ and $Y\left(8\right)$ using Equations (15) and (16). All the multipliers in Equations (6), (7), (9), (10) and (12)–(14) have one constant integer operand and have been implemented with additions/subtractions only.

3.2. The Obfuscation Technique Used in the Proposed Design

The implemented obfuscation strategy is a mode-based obfuscation technique [24,27]. To produce the correct result, each processing element of the implemented systolic chains has to be fed the correct sign bit at the appropriate moment in time. Therefore, in the entire design that implements the IntDCT, there are 22 sign bit inputs to the 22 PEs of the systolic chains, denoted $sgn\left(i\right),i\in \overline{\mathrm{1,22}}$, corresponding to the PEs in the following order:

• $sgn\left(1\right)\dots sgn\left(4\right)$ are the sign bit inputs to PE₁ $\dots$ PE₄ of Figure 3;
• $sgn\left(5\right)\dots sgn\left(8\right)$ are the sign bit inputs to PE₁ $\dots$ PE₄ of Figure 4;
• $sgn\left(9\right)\dots sgn\left(12\right)$ are the sign bit inputs to PE₁ $\dots$ PE₄ of Figure 5;
• $sgn\left(13\right)\dots sgn\left(16\right)$ are the sign bit inputs to PE₁ $\dots$ PE₄ of Figure 6;
• $sgn\left(17\right)\dots sgn\left(20\right)$ are the sign bit inputs to PE₁ $\dots$ PE₄ of Figure 7;
• $sgn\left(21\right)\dots sgn\left(22\right)$ are the sign bit inputs to PE₁, PE₂ of Figure 8.

For obfuscation purposes, we consider three permutations, ${\pi }_1,{\pi }_2$, and ${\pi }_3$ of the $\{1,2,\dots ,22\}$ set:

$${\pi }_1=\left(\begin{array}{rrrrrrrrrrrrrrrrrrrrrr}1& 2& 3& 4& 5& 6& 7& 8& 9& 10& 11& 12& 13& 14& 15& 16& 17& 18& 19& 20& 21& 22\\ 17& 14& 16& 1& 10& 20& 21& 5& 13& 22& 2& 11& 4& 18& 3& 8& 12& 7& 9& 19& 15& 6\end{array}\right)$$

(17)

$${\pi }_2=\left(\begin{array}{rrrrrrrrrrrrrrrrrrrrrr}1& 2& 3& 4& 5& 6& 7& 8& 9& 10& 11& 12& 13& 14& 15& 16& 17& 18& 19& 20& 21& 22\\ 12& 5& 18& 11& 8& 22& 13& 1& 2& 20& 7& 4& 16& 9& 17& 10& 6& 3& 14& 21& 15& 19\end{array}\right)$$

(18)

$${\pi }_3=\left(\begin{array}{rrrrrrrrrrrrrrrrrrrrrr}1& 2& 3& 4& 5& 6& 7& 8& 9& 10& 11& 12& 13& 14& 15& 16& 17& 18& 19& 20& 21& 22\\ 3& 22& 17& 4& 19& 2& 15& 5& 1& 10& 6& 12& 7& 13& 20& 8& 21& 11& 14& 16& 9& 18\end{array}\right)$$

(19)

To produce the obfuscated sign bit, $\widehat{sgn}\left(i\right)$, for a particular PE, we use a four-way multiplexer as illustrated in Figure 9, where $K[2i+1:2i]$ are the selection bits of the multiplexer $i$, taken from the de-obfuscation key $K[0:43]$ at indices $2i+1$ and $2i$, with $i\in \overline{\mathrm{0,21}}$.

In case of the incorrect key, $\tilde{K}[0:43]$ is applied at the selection inputs of the four-way multiplexers; the output sign bits will represent a selection of the permuted original sign bits, which will lead to an incorrect computation of the output results. Only when the correct key, $K[0:43]$, is presented at the inputs of the four-way multiplexers, the output results computation is performed correctly. In our implementation, we have considered $K=0\mathrm{x}\mathrm{C}153\mathrm{A}00583\mathrm{A}$ (base 16 representation).

3.3. VLSI Implementation

The RTL description of the IntDCT was performed using SystemVerilog. An example simulated operation of the IntDCT core implementation is illustrated in Figure 10, Figure 11 and Figure 12. The operation of the IntDCT core was exemplified for 2 batches of 16 input samples: $x$ = 121, 106, 92, 79, 67, 56, 37, 29, 22, 16, 11, 7, 4, 2, and 1, immediately followed by $x$ = 10, 20, 30, 40, 50, 60, 70, 80, 80, 70, 60, 50, 40, 30, 20, and 10.

The first output sample is produced after 32 samples, therefore the latency of the implemented IntDCT core is $32T_{clk}$.

The expected unscaled output sequence for the first input batch is $y$ = 89,088, 53,000, 13,144, 5784, 3216, 2024, 1368, 1192, 720, 488, 424, 360, 208, −8, 104, and 152, which is produced by the implementation, as can be observed in Figure 10, Figure 11 and Figure 12.

In the figures, the first input sample batch is highlighted with blue and the second input samples batch is highlighted with green. The first output samples batch is highlighted with magenta and the second output samples batch is highlighted with yellow. The partial results produced by the systolic chains are highlighted with the color corresponding to the outputs which they contribute to.

For characterization purposes, we have synthesized the IntDCT core using Cadence Genus 21.14 with Nangate OpenCell Library and NCSU’s 15 nm FreePDK15. We have considered an 8 bits width for the input samples and an 18 bits width for the unscaled output samples.

Table 1. Summary of synthesis results of the IntDCT core.

Constrained Clock Period/ Frequency	Critical Path Delay + Setup Time [ps]	Interconnect Area [µm2]	Combinational Area [µm2]	Flop Area [µm2]	Total Area [µm2]	Equivalent Gates Count	Static Power [µW]	Dynamic Power at Constrained Clock Frequency [mW]
50 ns/20 MHz	419	1004.41	1593.46	2095.45	4693.32	232,833.79	132.1	0.2 at 20 MHz
10 ns/100 MHz	419	1004.41	1593.46	2095.45	4693.32	232,833.79	132.1	1.0 at 100 MHz
1 ns/1 GHz	418	998.11	1584.27	2095.45	4677.83	232,065.29	131.4	9.5 at 1 GHz
300 ps/3.33 GHz	300	1052.21	1786.48	2095.45	4934.14	244,780.93	138.8	33.6 at 3.33 GHz
250 ps/4 GHz	250	1316.08	2063.89	2095.45	5475.42	271,633.60	161.0	48.0 at 4 GHz
240 ps/4.17 GHz	240	1380.77	2135.07	2095.65	5611.48	278,383.74	167.3	52.1 at 4.17 GHz

summarizes the synthesis results in terms of area, power, and delay for the IntDCT. It can be observed that the minimum constrained clock period for which the synthesis tool is able to find a solution is 4.17 GHz. At this frequency, the dynamic power is 52.1 mW.

The proposed solution has further potential for optimization by early scaling the partial results (currently, the output needs to be divided by 128, i.e., the least 7 significant bits can be discarded) along the systolic chains. Another means to increase the operating frequency is to add a pipeline stage for the computation of the auxiliary inputs in Equation (5).

4. Discussion

We have obtained a new integer algorithm for type II DCT that has good approximation properties and allows efficient VLSI implementation. Moreover, it allows an efficient integration of the obfuscation technique with low overheads. The involved overhead of incorporating the obfuscation technique is low and consists of 22 four-way, one-bit multiplexers. The area overhead of the multiplexers is under 1% of the total chip area, while the impact on the speed of the DCT core operation is minimal because the multiplexers are not on the critical data path of the systolic arrays.

For the proposed integer algorithm, a new systolic array-based VLSI architecture has been obtained. It consists of five linear arrays, each having four processing elements, and one array with two processing elements, all working in parallel. Due to the fact that the proposed integer algorithm is using only small integers and each processing element contains a multiplier with a small constant implemented with two adders (with two exceptions where we use three adders), the hardware complexity was significantly reduced and, at the same time, the speed performances were increased due to the fact that in the systolic chains the delay on the critical path is mostly $3T_a$, where $T_a$ is the delay of one adder. Thus, we can use only adders/subtracters and shift operations to implement the proposed VLSI architecture. As it can be seen from

Table 2. Representation of the constant multiplication coefficients used in the PEs.

$\mathbf{Coefficient} \left(\mathit{C}\right)$	Representation	Number of Adders/Subtractors
127	$2^7-2^0$	1
81	$2^6+2^4+2^0$	2
13	$2^4-2^1-2^0$	2
100	$2^6+2^5+2^2$	2
122	$2^7-2^2-2^1$	2
113	$2^7-2^4+2^0$	2
37	$2^5+2^2+2^0$	2
60	$2^6-2^2$	1
125	$2^7-2^1-2^0$	2
106	$2^6+2^5+2^3+2^1$	3
25	$2^4+2^3+2^0$	2
71	$2^6+2^3-2^0$	2
48	$2^5+2^4$	1
118	$2^7-2^3-2^1$	2
128	$2^7$	0
90	$2^6+2^4+2^3+2^1$	3

, to implement the constant multipliers we mostly need only 2 adders and shift operations, with 2 exceptions, where for coefficients 106 and 90 we use 3 adders.

Due to the fact all five systolic arrays are working in parallel and due to the use of the pipelining mechanism, where the critical path has a delay of mostly $3T_a$, we can obtain high speed performances at a significantly reduced hardware cost due to the use of only adders to implement the proposed VLSI architecture. Moreover, the proposed solution can efficiently integrate the hardware security technique with a slight increase in the hardware complexity with only 22 MUXs, without affecting the speed performance.

Furthermore, the proposed solution has similar advantages to other systolic array VLSI implementations of type II DCT, such as efficient VLSI implementation and low I/O cost.

In

Table 3. Comparison of hardware performances.

	TSDCT [33]	RICT [34]	ACCESS [29]	TCAD 2022 [30]	Proposed
Area [µm2]	55,486	27,414	9835	10,813	4693
Improvement [%]	91.5	82.9	52.3	56.6	-
Critical Path [ns]	6.04	6.16	6.69	6.73	0.419
Improvement [%]	93.1	93.2	93.7	93.8	-
Power [mW]	4.56	5.06	2.20	3.25	1.132
Improvement [%]	75.2	77.6	48.6	65.2	-

, a comparison in terms of area, power, and speed performance is presented. The proposed IntDCT solution is compared to similar solutions from the literature.

All the referenced designs in Table 3 were mapped to a 45 nm standard cell library using Synopsys Design-Compiler, whereas our design was mapped to Nangate’s OpenCell Library based on NCSU’s 15 nm FreePDK15 using Cadence Genus 21.14.

As can be seen from Table 3, a considerable reduction in power consumption has been obtained for the proposed solution due to a reduced hardware complexity based on as few as 29 adders to implement the hardware core with 5 linear systolic arrays.

One of the most important advantages of using the systolic array architectural paradigm is a significant reduction in the delay on the critical path, as emphasized in Table 3, where an improvement of more than 93% was obtained as compared to the referenced designs. This has allowed for a significant increase in speed performances in our solution by using a clock frequency of up to 4.17 GHz, as illustrated in Table 1.

Another noticeable advantage of the proposed solution based on the systolic array paradigm consists of the efficient incorporation of an obfuscation technique with a small overhead.

5. Conclusions

In this paper, a new hardware algorithm for an integer based discrete cosine transform (IntDCT) was proposed that provides a good approximation of the discrete cosine transform and at the same time offers an efficient VLSI implementation using the systolic array architectural paradigm. Using a multi-objective optimization, the proposed integer transforms searches for an efficient IntDCT matrix which has the coding performance as close as possible to the DCT transform but implemented with reduced hardware/power and high-speed performances obtaining using pipelining and parallelism. The proposed integer DCT algorithm has been efficiently restructured into five regular and modular computational structures of lengths of four and one of length two called pseudo-cycle convolutions. These regular and modular computational structures allow for an efficient VLSI implementation using systolic arrays. Moreover, besides an efficient VLSI implementation with high speed, the proposed integer DCT algorithm and its VLSI architecture allow for efficient incorporation of the obfuscation technique that significantly improves the hardware security with a low overhead which maintains all the implementation performances.