Tena-Sánchez, E.; Potestad-Ordóñez, F.E.; Jiménez-Fernández, C.J.; Acosta, A.J.; Chaves, R.
Gate-Level Hardware Countermeasure Comparison against Power Analysis Attacks. Appl. Sci. 2022, 12, 2390.
https://doi.org/10.3390/app12052390
AMA Style
Tena-Sánchez E, Potestad-Ordóñez FE, Jiménez-Fernández CJ, Acosta AJ, Chaves R.
Gate-Level Hardware Countermeasure Comparison against Power Analysis Attacks. Applied Sciences. 2022; 12(5):2390.
https://doi.org/10.3390/app12052390
Chicago/Turabian Style
Tena-Sánchez, Erica, Francisco Eugenio Potestad-Ordóñez, Carlos J. Jiménez-Fernández, Antonio J. Acosta, and Ricardo Chaves.
2022. "Gate-Level Hardware Countermeasure Comparison against Power Analysis Attacks" Applied Sciences 12, no. 5: 2390.
https://doi.org/10.3390/app12052390
APA Style
Tena-Sánchez, E., Potestad-Ordóñez, F. E., Jiménez-Fernández, C. J., Acosta, A. J., & Chaves, R.
(2022). Gate-Level Hardware Countermeasure Comparison against Power Analysis Attacks. Applied Sciences, 12(5), 2390.
https://doi.org/10.3390/app12052390