Improvement of Heat Transfer Properties through TiO₂ Nanosphere Monolayer Embedded Polymers as Thermal Interface Materials

Abstract

A thermal interface material (TIM) is a substance that reduces the thermal resistance between a heat source and heat sink, which facilitates heat conduction towards the outside. In this study, a TiO₂ nanosphere (NS)-filler based TIM was fabricated via facile processes such as spin-coating and icing methods. Thermal conductivity of the fabricated TiO₂ NS-based TIM was enhanced by increasing the loading contents of the TiO₂ NS-filler and successfully cooling down the GPU chipset temperature from 62 °C to 50 °C. Moreover, the TIM with the TiO₂ NS-monolayer additionally lowered the GPU temperature by 1–7 °C. The COMSOL simulation results show that the TiO₂ NS-monolayer, which was in contact with the heat source, boosts the heat transfer characteristics from the heat source toward the inside of the TIM. The suggested metal oxide monolayer-based TIM is an effective structure that reduces the temperature of the device without an additional filler loading, and it is expected to have a wide range of applications for the thermal management of advanced devices.

1. Introduction

For several decades, the integration of electronic devices to improve system performance has accelerated rapidly. Due to the resulting miniaturization of semiconductor devices, thermal management issues related to electronic components have become increasingly important [1,2]. Especially in small electronic devices, the generated heat significantly affects the efficiency degradation, lifetime, and overall performance. A previous study reported that even a small temperature rise of 10–15 °C in electronic devices reduces the life expectancy by 50% and decreases system reliability [3]. Therefore, heat dissipation control techniques are becoming more important than ever.

In particular, to prevent abnormal temperature rises in such devices, it is necessary to lower the thermal resistance at the contact interface between a chip and heatsink by applying a thermal interface material (TIM). Such a material should have a high thermal conductivity, which decreases the thermal resistance between the chip and heat sink [4,5,6,7,8]. The primary requirements for TIM are high thermal conductivity and stability and low electric conductivity. Among them, high thermal conductivity is the most important parameter, and generally requires using a small loading fraction of fillers, which is becoming important for low-cost and high-efficiency devices [9]. Recently, polymer materials are widely used as TIMs because of their easy processing, light weight, and low cost. However, polymers generally have low thermal conductivity (~0.16 Wm⁻¹K⁻¹) due to the random arrangement of their macromolecular chains [10]. Recently, various research has been conducted to enhance the thermal conductivity of polymer [10,11,12,13,14,15]. For example, Ouyang. et al. used a metal oxide (Al₂O₃) filler to enhance the thermal conductivity and explained the importance of using a nanosphere filler and nanosphere’s morphology to reduce the phonon scattering between the fillers on an uneven surface [16]. Ma. et al. enhanced the thermal conductivity of polymer (~2.84 Wm⁻¹K⁻¹) using one-dimensional carbon fiber to make a thermal path [17]. However, current polymer-based TIMs do not satisfy the demands of various advanced devices due to the high loading fraction of fillers (>50 wt%), which can degrade the original electrical insulation while increasing the thermal conductivity [14]. Therefore, it is necessary to develop novel structures consisting of materials with low electrical conductivity to achieve efficient heat conduction with low loading of fillers.

Among the generally used fillers, metal oxides such as alumina (Al₂O₃), copper oxide (CuO), and titanium-dioxide (TiO₂) are cheaper and more stable with a lower electrical conductivity than other metals [16,18]. Thus, they are less likely to cause electrical problems in electronic devices after the packaging process. In particular, TiO₂ not only has a low electrical conductivity due to its wide bandgap (~3.2 eV at room temperature), but also relatively high thermal conductivity [18,19]. Although these advantages showcased TiO₂ as a potential candidate for TIM filler, few studies have been reported.

In this study, we demonstrate the effective improvement of thermal conductivity of TIM by constructing a TiO₂ nanosphere (NS)-monolayer structure in a polymer. COMSOL Multiphysics simulations were conducted to explain the thermal conductivity enhancing effect of the monolayer structure, considering complex heat transfer such as conduction, convection, and thermal resistance. The thermal conductivity of the fabricated TiO₂ NS-based TIM was enhanced with an increasing loading fraction of the TiO₂ NS-filler, and the GPU chipset temperature was lowered from 62 °C to 50 °C. In addition, when the TiO₂ NS-monolayer was additionally embedded in TIM, it lowered the GPU temperature by an additional 1–7 °C. In particular, the TiO₂ NS-monolayer TIM shows a similar cooling effect to that of the 30 wt% TiO₂ NS-filler for the GPU’s temperature. In COMSOL, the reason for the device temperature decrease was confirmed as being due to the large heat absorption by the monolayer. Consequently, the TiO₂ NS-monolayer could maintain the chipset at a much lower temperature at the same loading fraction via effective heat absorption from the heat source. These results show that the fabricated TiO₂ NS-filler/monolayer structure in polymers is widely applicable in TIMs.

2. Materials and Methods

2.1. Materials

To synthesize TiO₂ NSs and form the monolayer, Titanium(IV) isopropoxide (≥97.0%, Sigma Aldrich, St. Louis, MO, USA), methyl amine solution (40 wt% in H₂O, Sigma Aldrich), acetonitrile (≥99.8%, Daejung, Siheung, Korea), ethyl alcohol anhydrates (≥99.5%, Daejung), and polydimethylsiloxane (PDMS, Dow Corning, Midland, MI, USA) were used without further purification processes.

2.2. Synthesis of TiO₂ NSs

The TiO₂ NS-filler was synthesized using a solution-based synthesis method and two types of solutions were prepared [20,21]. The first solution was prepared by injecting 108 μL of DI water and 5 μL of methylamine solution into a solvent consisting of 80 mL of acetonitrile and 10 mL of ethyl alcohol, and the second solution was prepared by injecting 10 mL of ethanol into 412 μL of titanium (IV) isopropoxide. Both solutions were stirred for 5 min. Then, the first solution was poured into the second solution and stirred quickly for 1 h. After separating and cleaning the formed sediment using a centrifuge, the solution was dried in a 70 °C oven to obtain amorphous TiO₂ NS-powder. Then, to obtain anatase TiO₂ NS-powder from the as-synthesized amorphous TiO₂ NS-powder, heat-treatment at 450 °C for 4 h (heating speed: about 1.8 °C/min) was conducted [22].

2.3. Characterization

To investigate the crystal structures of the synthesized TiO₂, X-ray diffraction (XRD) patterns were obtained from the TiO₂ NS-powder and analyzed. As shown in Figure 1, there were no XRD peaks for the as-synthesized TiO₂ NSs, but after heat treatment, XRD peaks were clearly shown and well-corresponded with the crystal planes of (101), (004), (200), (105), (211), (204), (116), (220), (215), and (303) of anatase TiO₂ (JCPDS No. 21-1272) [23]. Consequently, we confirmed that the synthesized amorphous structure of the TiO₂ NS was successfully crystallized to an anatase structure after heat treatment.

2.4. TIM Fabrication Process

Figure 2 shows the TIM fabrication processes using the obtained anatase TiO₂ NS-powder. To transfer the TiO₂ NS-monolayer to the supporting substrates, the icing technique was used. At first, a fixed amount of DI water was dropped on the cleaned supporting substrates. Then, the TiO₂ NS-monolayer prepared on the PDMS via the unidirectional rubbing method was attached to the supporting substrates and kept at low temperature under 0 °C to freeze the DI water [22]. The frozen DI water can hold the TiO₂ NS-monolayer in place for the supporting substrates. After detaching the PDMS from the TiO₂ NS-monolayer, the DI water was evaporated on a hotplate at 70 °C. At the same time, the 20 wt%, 30 wt%, and 40 wt% TiO₂ NS-powders were mixed in solution with PDMS and curing agent at a mass ratio of 10:1. The obtained mixtures were spin-coated on the TiO₂ NS-monolayer transferred supporting substrates at 500 rpm for 10 s and 1000 rpm for 20 s, successively. These spin-coated substances on the supporting substrates were hardened in a 70 °C oven for 1.5 h, then the cured substances were detached from the supporting substrates to complete the fabrication process of the TIM.

2.5. Simulation

The heat conduction simulations of the TiO₂ NS-filler/monolayer in PDMS composite were performed using COMSOL Multiphysics 5.6. The selected physics of the heat transfer in the solids and the study was stationary. The TiO₂ NS-fillers were built using random functions in the application builders of the development functions to represent the randomly mixed form of the fillers. The thicknesses of the TIMs were 3 µm, the sizes of the spheres were set from 360 nm to 400 nm in diameter, and the numbers of NSs were set to match with the loading fraction of the TiO₂ NS-fillers of 20 wt%, 30 wt%, and 40 wt%. The material used for the chipset and heat sink was aluminum. As a boundary condition, a 10⁻⁵W quantity of heat was applied to the bottom of the chipset, the initial temperature and ambient temperature were both 20 °C, and 1.5 m/s of air flow was applied along the walls of the heat sink and TIM. The rest interfaces were set to insulation conditions. Additionally, an equivalent thin layer of thermal contact for the given thermal resistance conditions was placed between the substances. The thermal resistance values were 10⁻⁷ Km²W⁻¹ between TiO₂ and PDMS and 2 × 10⁻⁵Km²W⁻¹ between PDMS and aluminum.

2.6. Measurement and Analysis Conditions

Crystalline structural analysis of the synthesized TiO₂ NSs was performed via X-ray diffraction (XRD, Flex600) with a CuKα (λ = 1.5406 Å) light source, and surface images were taken using a scanning electron microscope (FESEM, S-4800). All temperature measurements were conducted at room temperature at about 40% relative humidity conditions.

3. Results and Discussion

To fabricate the new TIM structure, we used a PDMS matrix, TiO₂ NS-filler, and TiO₂ NS-monolayer. The detailed experimental condition and fabrication processes are described in the materials and methods section. To verify the morphology of the synthesized anatase TiO₂ NS, field emission scanning electron microscope (FESEM) measurements were conducted. The synthesized anatase TiO₂ NSs showed a spherical shape with diameters of several hundreds of nanometers, as shown in Figure 3a. The diameter distribution of the synthesized TiO₂ NSs is shown in Figure 3b, and the average diameter from the diameter distribution is about 352.25 ± 20.7 nm, showing that the synthesized TiO₂ NSs have uniform sizes.

To observe the morphology changes of TiO₂ NS-based TIMs, FESEM measurements were conducted with various directions of the fabricated TIM samples, as shown in Figure 4. Figure 4a shows the transferred TiO₂ NS-monolayer on the rigid support substrate. Figure 4b,c shows the bottom view of PDMS with and without the TiO₂ NS-monolayer, respectively. As shown in Figure 4c, it can be confirmed that the TiO₂ NS-monolayer was successfully embedded in PDMS, which is clearly seen from Figure 4b. The loading fractions of the TiO₂ NS-filler in PDMS were adjusted to 20 wt%, 30 wt%, and 40 wt%, which can be converted to 5.3 vol%, 8.8 vol%, and 13.2 vol% as volume ratios, respectively. Figure 4d–f shows the FESEM cross-sectional images of the fabricated TIMs with different TiO₂ NS contents, and the occupancy of TiO₂ NS particles according to the change of loading fraction in PDMS can be roughly classified. From the cross-sectional views of the SEM, it should be noted that TiO₂ NSs are uniformly distributed inside the PDMS for all embedded conditions.

The fabricated TIMs consisting of the TiO₂ NS-filler/monolayer embedded PDMS were attached to the actual GPU chipset to investigate the heat dissipation characteristics. Figure 5a shows the optical photographs of the GPU chipset, fabricated TIMs, heat sink, and cooling fan for the heat dissipation characteristic measurements.

The heat dissipation characteristics of the fabricated TiO₂ NS-based TIMs applied in the GPU chipset were compared by increasing the loading fraction of the TiO₂ NS-filler from 0 wt% to 20 wt%, 30 wt%, and 40 wt%, with and without the TiO₂ NS-monolayer. As shown in Figure 5b, the temperatures of the GPU chipset were gradually decreased with increasing loading fractions of the TiO₂ NS-filler from 0 wt% to 40 wt%. In addition, in all cases with the same filler loading fraction, the temperatures of the GPU chipset with the TiO₂ NS-monolayer embedded TIM were much lower than those of GPU TIMs without the embedded TiO₂ NS-monolayer. In all samples, the thermal conductivities of the TIMs were enhanced by the TiO₂ NS-filler, resulting in a lowered GPU chipset temperature from 62 °C to 55 °C with increasing loading fraction of the TiO₂ NS-filler from 0 wt% to 40 wt%. More improvements of the thermal dissipation were accomplished by additional embedding of the TiO₂ NS-monolayer, lowering the GPU chipset’s temperature by 1–7 °C. Note that only the TiO₂ NS-monolayer embedded in PDMS exhibited similar thermal dissipation effects compared with the 30 wt% TiO₂ NS-filler. Moreover, 30 wt% TiO₂ NS-filler/monolayer embedded in PDMS exhibited almost the same heat dissipation characteristics as the 40 wt% TiO₂ NS-filler. It is noteworthy that the loading fraction of the TiO₂ in NS-monolayers is only 0.314 wt%. These results indicate that the TiO₂ NS-monolayer not only effectively enhances the thermal conductivity of TIM but is also a cost-effective way to achieve a high thermal conductivity of TIM without additional filler loading. Figure 5c shows the working time-dependent temperature variation of the GPU chipset from 0 to 500 s with the fabricated TIMs attached. In all samples, there were abrupt increases in temperature during the initial stages, which then became saturated about 140 s later. In addition, the maximum measured temperatures of the GPU chipset decreased as the loading fraction of the TiO₂ NS-filler in the PDMS increased, with a tendency to decrease further in the presence of the TiO₂ NS-monolayer.

To theoretically investigate the thermal conductivity enhancement of TIMs by a TiO₂ NS-monolayer, a computer simulation was used with COMSOL Multiphysics 5.6. The simulations were conducted on the premise that the lowest saturation temperature model has the highest thermal conductivity. The quantity of heat applied to the chipset and the air flow speed applied to the heat sink were fixed considering typical cooling fan speeds (Ø150 mm, 1200 rpm) and detailed values are described in the materials and methods Section 2.3. For more accurate analysis, the thermal resistances between the PDMS, TiO₂ NSs, chipset, and heat sink should be considered based on the contact interface conditions [24]. The thermal resistances between the chipset and TIM and the TIM and heat sink were set to relatively high values of 2 × 10⁻⁵ Km²W⁻¹ because they have solid-solid contact interfaces with air gaps due to the surface roughness [25,26]. TiO₂ NSs and PDMS form relatively stable interfaces because they are mixed and hardened in a liquid state [27]. Thus, the thermal resistance between TiO₂ NSs and PDMS was 10⁻⁷ Km²W⁻¹, a relatively low value [28]. Figure 6a shows the heat conduction characteristics of TIMs with bare PDMS, 20 wt% TiO₂ NS-filler in PDMS, and 20 wt% TiO₂ NS-filler/monolayer in PDMS at the same temperature scale. The heat conduction enhancement due to the NS-monolayer was clearly observed by comparing the average temperatures of the chipset and TIM. The ratio of the temperature difference between the two substances forming an interface can be described as follows:

$$\mathrm{Temperature}\mathrm{difference}\mathrm{ratio}=\frac{{\mathrm{T}}_{\mathrm{heat}\mathrm{source}}-{\mathrm{T}}_{\mathrm{TIM}}}{{\mathrm{T}}_{\mathrm{TIM}}}\times 100[\%],$$

(1)

where T_{heat source} and T_TIM are the steady-state temperature of the heat source (chipset) and TIM, respectively. The large temperature difference indicates that there is a large contact resistance, which can impede heat conductions between the chipset and TIM, causing heat to be trapped in the heat source. The case of bare PDMS without any TiO₂ NS embedded shows that the temperatures of the chipset and TIM were 67.18 °C and 44.83 °C, respectively, which is about a 50% temperature difference ratio between them. This means that the applied heat could not be easily transferred from the chipset to TIM due to the heat trapped inside the chipset because of the high thermal resistance between them. In the case of TIM with the 20 wt% TiO₂ NS-filler in PDMS, the temperatures of the chipset and TIM were lowered to 58.19 °C and 44.83 °C, respectively, with a temperature difference ratio of about 37.7% between the chipset and TIM. Meanwhile, TIM with the 20 wt% TiO₂ NS- filler/monolayer in PDMS maintained a chipset temperature of 45.18 °C and TIM temperature of 40.58 °C, which were not only the lowest temperatures among the samples but exhibited a reduced temperature difference of only 11.3%. These smallest temperature differences indicate that the TiO₂ NS-monolayer results in low interface thermal resistance and efficient heat conduction, as shown in Figure 6a. Based on these results, simulations were conducted successively by changing of the TiO₂ NS-filler loading fraction from 0 wt% to 20 wt%, 30 wt%, and 40 wt%, with and without the TiO₂ NS-monolayer. The thermal conductivities of fabricated TIMs were enhanced, which lowered the chipset temperature by about 20.3% (from 59 °C to 47 °C) with increasing loading fractions of the TiO₂ NS-filler from 0% to 40 wt%; additional heat dissipation enhancement via inclusion of the TiO₂ NS-monolayer lowered the chipset temperature by an additional 10–15% compared to TIMs without the TiO₂ NS-monolayer. The increased thermal conductivity was affected by the TiO₂ NS-monolayer for all filler loading fractions, as evidenced through the lowered chipset temperatures and experimental results.

The detailed heat transfer processes between the chipset and TIM with TiO₂ NS-filler/monolayer are considered in Figure 7. The increase in thermal conductivity and reduction in thermal resistance at the interface due to the TiO₂ NS-monolayer can be attributed to how the embedded TiO₂ NSs can maximize the effects of heat absorption from the heat source. In the case of TiO₂ NSs embedded in PDMS TIMs without a TiO₂ NS-monolayer, the heat absorption from the heat source is not easily observed due to the high thermal resistance of uneven contact points between the chipset and TIM, as well as the poor thermal conductivity of PDMS [29]. Moreover, the relatively small area for heat conduction from the chipset to TIM due to the limited contact interface between them hindered effective heat dissipation [30]. However, the TiO₂ NS-monolayer with TIM can absorb large quantities of heat with higher thermal conductivity than PDMS. In this way, the absorbed heat can be released into the TIM through a large surface contact area with the TiO₂ NS-monolayer. The released heat is transferred outside following the heat path formed by the TiO₂ NS-filler, which can result in strong cooling effects on electronic devices without additional loading fraction changes of the TiO₂ NS-filler [31]. Consequently, the suggested facile TiO₂ monolayer embedding method is an effective way to fabricate a low-cost and high-performance TIM, which has enormous potential for heat dissipation technology.

4. Conclusions

In summary, TiO₂ NS-filler/monolayer-based TIMs were fabricated by spin-coating a TiO₂ NS/PDMS mixture on a TiO₂ NS-monolayer with transfer via the icing method. The thermal conductivities of the TIMs were enhanced by increasing the loading fractions of the TiO₂ NS-fillers in PDMS from 0 wt% to 40 wt%, which lowered the GPU chipset temperature from 62 °C to 50 °C. In all TiO₂ NS/PDMS fillers with different loading fractions, it was found that an additional TiO₂ NS-monolayer improved the thermal conductivity of TIM and lowered the GPU chipset temperature by about 1–7 °C compared to TIMs without an NS-monolayer. The interesting thing is that including only the TiO₂ NS-monolayer in PDMS (0 wt% filler) achieved dramatic heat conduction improvement, similar to that for the 30 wt% TiO₂ NS-filler in PDMS. The thermal conductivity enhancement via the TiO₂ NS-monolayer was analyzed using simulations via COMSOL Multiphysics 5.6. The TiO₂ NS-monolayer can effectively absorb larger quantities of heat from the heat source than polymers with small thermal resistance, and can effectively dissipate the absorbed heat to the outside because of the large surface areas of the spheres. Based on our results and considering that the TiO₂ NS-monolayer’s loading fraction is only 0.314 wt%, the TIM consisting of TiO₂ NSs and an NS-monolayer provides an efficient way to achieve higher thermal conductivity with low additional filler loading. Our proposed metal oxide NS-monolayer structure has great potential for improving TIM performance.