Fast Performance Evaluation for Switched-Capacitor Converter Based on Convolutional Neural Networks

Abstract

Switched-capacitor converters (SCCs) have been developed for decades and applied successfully in many applications thanks to their merits of high power density, high efficiency, and low cost. Existing SCC evaluation methods do not provide an efficient and effective way to estimate their performance. This paper proposes a new evaluation performance method for SCCs that transforms the topology optimization issue into a more typical non-linear regression problem. The SCC topologies are described by the adjacent matrix. A CNN model is then selected to solve the regression problem. Experimental results confirm that this CNN model greatly shortens the calculation time while performing better than other machine learning algorithms.

1. Introduction

With the power consumption of data centers soaring rapidly, the sharp contradiction between computational performance and thermal limitations in the motherboard has become a major bottleneck confronting designers [1]. High power density and high-efficiency designs are extremely valuable for onboard DC–DC converters such as voltage regulator modules (VRMs) and point of load (POL) converters. Among various DC–DC converters, soft-switching solutions have greatly reduced switching losses under the irreversible trend of high frequency compared to conventional switching converters. Undesirably, they are difficult to integrate due to bulky inductive items. Furthermore, the inductor-based converter design suffers from second-order effects introduced by the nonlinear characteristics of magnetic materials.

As one of most vital branches of DC–DC converters, switched-capacitor converters (SCCs) can be easily embedded on the motherboard, and are regarded as a promising solution [2,3] for balancing performance and cooling. Currently, SCCs are widely used in chip power supply, energy buffering, LED driving, portable device fast charging, and data center power supply. SCCs are composed exclusively of capacitors and switches, and can efficiently generate a step-up or step-down output voltage of the same polarity with two or more phases. One of the most well-known switched capacitor circuits is the Dickson Charge Pump (DCP) [4]. Lacking magnetic elements [5], SCCs have an overwhelming advantage in reliability, integration level, control complexity, and power density compared with the conventional switching-mode power supply (SMPS) and soft-switching converter [6].

In order to cover existing and emerging application requirements, SCCs featuring diverse characteristics are in demand. Hence, continuous academic efforts have been directed towards SCC topology exploration, resulting in the rapid expansion of topologies of SCCs [7]. In general, there are three traditional approaches concerning topology derivation, namely, modular structure extension [8,9], iterative combination [10], and systematic generation [11]. SCC topology design is a rather complicated issue due to the integration and comprehensive effects of various parameters, such as power consumption, switch characteristics, and operation frequency [12,13].

Conventionally, the selection of an SCC topology from the large variety of derived topologies is an extremely laborious process which requires iterative synthesis, simulation, evaluation, and optimization [14,15]. This can significantly extend the development cycle due to repetitive efforts [11]. For the sake of economic cost, designers often fall into stereotypical solutions such as Dickson or Doubler without considering specific requirements, which can easily lead to non-optimal system design.

Therefore, performance evaluation methods for new converter topologies are highly valued in switched-capacitor research. In [16], a new architecture for a charge pump and its design specifications for battery-powered applications were proposed, and a simplified RC model was built for mathematical analysis. However, this method can only be applied to simple topologies. Two models were proposed by H. Lin et al. in [17] for a charge pump circuit design with a PMOS charge pump. The charge balance method and dynamic charge transfer waveforms were used to improve the output voltage and power conversion efficiency. In [18], the authors proposed a conduction loss model of an SCC based on the average-current model, with the conduction loss calculated using the total loop equivalent resistance. However, the current waveforms were obtained by approximation at the expense of accuracy. In general, complex topology, computational efficiency, and accuracy cannot all be achieved at the same time.

With the advent of machine learning techniques, state-of-the-art AI approaches can open a door for creative means of SCC performance evaluation. In this paper, we present a new performance evaluation algorithm for SCCs. The comprehensive analysis and evaluation framework provided here are novel and enlightening. Following a review of SCC analysis, the architecture of the proposed method is presented and explained; the approach is easy to implement. The effectiveness of the algorithm is tested for 48V-to-12V SCCs, and experimental results are presented. The method proposed in this paper is compared with other methods in terms of the applicable topology, calculation efficiency, and accuracy. See

Table 1. Comparison with existing methods.

	Topology	Efficiency	Accuracy
M.Navidi et al. [16]	Simple	High	Medium
H.Lin et al. [17]	Complicated	Low	High
M.Makowski et al. [18]	Medium	High	Low
This paper	Complicated	High	High

, it is shown that the proposed method outperforms the alternatives in the existing literature. The structure of this paper is organized as follows. Section 2 describes the problem of analysing the power loss and efficiency of SCCs. In Section 3, a novel mathematical model based on the adjacent matrix is proposed. In Section 4, the proposed performance evaluation method based on CNN is illustrated in detail. Finally, the experimental results are presented in Section 5.

2. Power Loss and Efficiency Analysis of Switched-Capacitor DC/DC Converters

SCC converts a voltage to another by means of changing rapidly between the capacitors using switches. For simplicity, the following assumptions are made:

• All switches share identical electrical characteristics, such as on-resistance $R_{ds\left(on\right)}$, etc.
• All internal (energy transfer) capacitors handling the same voltage share an identical capacitance C and equivalent series resistance $ESR$.
• The dead time of the converter is neglected.

The power loss of an SCC can be divided into three parts: conduction loss, switching loss, and gate driving loss. As is evident in Equation (1), the gate driving loss can be calculated using the switching period $T_s$, gate charge $Q_g$, and gate driving voltage $V_{gs}$

$$P_{\mathrm{gate}}=\sum _{Q_i}\frac{V_{gs}{Q}_g}{T_s}$$

(1)

where $Q_i$ denotes the ith switch. Switching loss can be expressed as

$$P_{SW}=\sum _{Q_i}\frac{\frac{1}{2}{I}_{DS}{V}_{DS}\left(t_{on}+t_{off}\right)}{T_S}$$

(2)

where $I_{DS}$ and $V_{DS}$ are the current and voltage across the MOSFET at switching moment, respectively. The conduction loss, which is generated from charging and discharging between energy-transfer capcitors, plays a major part in high current applications such as data center power supply and mobile phone quick charging. The conduction loss is composed of power dissipation in the ESR of the capacitor and the $R_{ds\left(on\right)}$ of MOSFET.

$$P_{conduction}=\sum _{{\mathrm{C}}_i}{\int }_0^{T_s}\frac{i{\left(t\right)}^2{R}_{ESR}dt}{T_s}+\sum _{Q_i}{\int }_0^{d{T}_s}\frac{i{\left(t\right)}^2{R}_{ds\left\{on\right\}}dt}{T_s}$$

(3)

However, the current waveform of an SCC is difficult to obtain, making $P_{SW}$ and $P_{conduction}$ hard to calculate. The conventional performance evaluation method is based on the well-known equivalent circuit, as shown in Figure 1, which is expressed by a cascade connection of an ideal DC transformer and an output impedance route. The conversion ratio M of the DC transformer is equal to the input and output voltage ratio $V_{out}/V_{in}$ at no load, and is only determined by the topology configuration. The output resistance $R_{out}$ is correlated with the operation efficiency. The most longstanding SCC evaluation method is based on the analysis of output resistance, $R_{out}$.

Referring to the conventional practices in inductor-based power converters, academic efforts have focused on obtaining the output resistance using state equations to analyse the instantaneous equivalent circuits of all phases. However, the element number of the state vector is equal to the number of charge-transfer capacitors in an SCC. In more complex topologies, it is not feasible to solve high-order differential equation to obtain the analytical expression of the output resistance. Confronted with the analytic calculation challenge, several approximation methods have been proposed. The fast switching limit (FSL) and slow switching limit (SSL) approach is the most versatile of the approximate approaches for SCC performance evaluation [19]. The FSL is prominent at high switching frequencies. The FSL impedance is calculated supposing that the voltage of each capacitor and sources are constant. In the FSL, current flow occurs in a frequency-independent constant pattern. The total output impedance of the converter is a combination of the conduction resistance of the switches as well as the ESR of the capacitors. As for low switching frequency, SSL plays an important part in performance evaluation. The SSL impedance is calculated with the following three assumptions:

• The switches and all other conductive interconnects are ideal.
• The current flowing between the input and output are impulsive.
• The voltage of each capacitor and all sources are constant.

SSL is used to describe the capacitor charging and discharging losses. The output impedance of an SCC can be analyzed through the synergy between FSL and SSL. These assumptions can only be applied to SCCs, not to other circuits, because of their substantive characteristics. SCCs feature high-order state equations and few operation phases, which makes their analytical expression difficult to obtain. Moreover, the capacitor voltage is approximately constant because the capacitor value is large enough, while the capacitor voltage in other types of circuits is time-varying. The core idea behind the FSL and SSL approach is the decoupling of voltage and current by assuming that the voltage of each capacitor and source is constant without being affected by current condition. These assumptions simplify the high-order differential equations to linear equations based on Kirchhoff’s current law (KCL) and Kirchhoff’s voltage law (KVL), overcoming the existing analytical calculation problem. Hence, the charge flow condition can be described by the charge transfer vector (CTV). The CTV corresponds to the charge flow in each respective phase of the SCC. Each element in the vector corresponds to a specific capacitor or independent voltage source, and describes the charge flow normalized by the output charge in one switching cycle $q_{out}$. CTV can be defined as

$$a^1=[q_{out}^1{q}_1^1\dots q_n^1{q}_{in}^1]$$

(4)

where superscript means that the charge transfer occurs in phase 1 of the switching period. The acquisition of output impedance is on the basis of charge flow condition presented by CTV. Unfortunately, the calculation of CTV is not as simple as expected [18]. The volt–ampere characteristic of the element is lost due to the assumption that the voltages are constant, making it impossible to calculate each element by CTV in certain topologies; these are called ill-posed SCCs. Contrary to mainstream opinion, the charge flow condition in ill-posed circuits is both determined by the configuration and influenced by electrical parameters such as the switching frequency, capacitor value, etc. As shown in Figure 2, the simplest ill-posed SCC is the interleaved Doubler. It is evident that an interleaved Doubler is composed of two identical subcircuits which operate in complementary mode to down-convert a DC voltage to half, as shown in Figure 2. In order to obtain the CTV of an interleaved Doubler, the node current equation can be presented using Kirchhoff’s current law (KCL), as follows:

$$\begin{array}{cc}\hfill & a_{out1}+a_{out2}=1\hfill \\ \hfill & a_{c1}=a_{out1}-a_{c2}\hfill \\ \hfill & a_{c2}=a_{out2}-a_{c1}\hfill \end{array}$$

(5)

where $a_{out1}$ and $a_{out2}$ are the output charge coefficient in phase 1 and phase 2, respectively. After a simple calculation, we can obtain

$$\begin{array}{c}{a}_{out1}=a_{out2}=\frac{1}{2}\\ a_{c2}+a_{c1}=\frac{1}{2}\end{array}$$

(6)

From the above calculation, we can only obtain the sum of capacitor charge coefficients $a_{c1}$ and $a_{c2}$ instead of each precise value. It is interesting that the two capacitors are parallel equivalently without sharing the same voltage in two phases. This type of circuit is classified as an ill-posed SCC, as the number of independent capacitors is more the number of KCL equations derived from the topology. In the case of voltage and current decoupling, it is not possible to find the flow condition of the charge on the capacitors. In order to analyze the charge flow condition, the equivalent series resistance (ESR) of the capacitor must be taken into consideration as well. The equivalent circuit in each phase is shown in Figure 3. The state equation for phase 1 can be calculated as

$$\left\{\begin{array}{c}{R}_1{C}_1\frac{d{V}_{c1}}{dt}=V_{in}-V_{out}-V_{c1}\hfill \\ R_2{C}_2\frac{d{V}_{c2}}{dt}=V_{out}-V_{c2}\hfill \\ R_3{C}_3\frac{d{V}_{c3}}{dt}=V_{out}-V_{c3}\hfill \\ I_{out}=C_2\frac{d{V}_{c2}}{dt}-C_1\frac{d{V}_{c1}}{dt}-C_3\frac{d{V}_{c3}}{dt}\hfill \end{array}\right.$$

(7)

The state equation for phase 2 can be calculated as

$$\left\{\begin{array}{c}{R}_1{C}_1\frac{d{V}_{c1}}{dt}=V_{out}-V_{c1}\hfill \\ R_2{C}_2\frac{d{V}_{c2}}{dt}=V_{in}-V_{out}-V_{c2}\hfill \\ R_3{C}_3\frac{d{V}_{c3}}{dt}=V_{out}-V_{c3}\hfill \\ I_{out}=C_2\frac{d{V}_{c2}}{dt}-C_1\frac{d{V}_{c1}}{dt}-C_3\frac{d{V}_{c3}}{dt}\hfill \end{array}\right.$$

(8)

Supposing $V_{in}=48 \mathrm{V},I_{out}=10 \mathrm{A}$, we can analyze the effect of capacitor value and ESR difference on charge flow condition. Switching frequency, capacitance, and ESR all influence the charge flow condition. Specifically, the resistance and charge transfer ratio on the branch are approximately inversely proportional, while the capacitance and charge transfer ratio are approximately proportional, as shown in Figure 4. It is obvious that the charge is not distributed equally in the two subcircuits when they are asymmetrical. As is apparent from the foregoing discussion, the traditional performance evaluation method based on output impedance cannot be applied to ill-posed circuits.

3. Mathematical Model of SCC Topologies

Due to the high switching frequency and large capacitance of energy-transfer capacitors in SCCs, the voltage of the capacitor can be viewed as constant in the steady state, in keeping with long-standing opinion. The voltage waveform of each node in the two-phase SCC can be viewed as a square wave composed of two levels when the circuit’s parasitic parameters are neglected. For example, The voltage waveform of node P in a 2-to-1 Doubler is shown in Figure 5. In phase 1, the voltage of node P is equal to $V_{DD}$, as $Q_1$ is conducted, while node P is connected to the output terminal in phase 2, because $Q_2$ is conducted.

Based on the analysis above, the voltage waveform of node P can be expressed by a two-dimensional array $[V_{DD},V_{OUT}]$, which presents each voltage level in its respective phase.

The optional range of the node voltage level is a particular set of positive integers that can be divisible by the maximum common factor of the input and output voltage. For example, if the SCC converts voltage from 48 V to 12 V, the node voltage levels are then selected from the set (0 V, 12 V, 24 V, 36 V, 48 V). For simplicity, the voltage conversion ratio can be rewritten as 4-to-1, while the selectable voltage level set can be represented as (0,1,2,3,4). The proposed two-dimensional array can label each node in the SCC topology uniquely; the nodes with same label share identical voltage waveforms in operation, which means that they can be connected. Therefore, the input terminal and output terminal in a 4-to-1 SCC can be expressed as $[4,4]$ and $[1,1]$, respectively. Furthermore, the two-dimension array $[V_1,V_2]$ can be transferred into a decimal number k by

$$k=V_1\ast M+V_2$$

(9)

where M is the maximum common factor of the input and output voltage and $V_1$ and $V_2$ are the node voltage in phase 1 and phase 2, respectively.

From the mathematical perspective, an SCC topology can be considered as a graph. The adjacent matrix [20] can be used to describe the SCC topology after every node is marked uniquely. As shown in Figure 6, the matrix element is 1 if there is a switch or a capacitor between the corresponding node, otherwise the element is 0. Additionally, the dimension of the adjacent matrix is equal to the N, which is equal to ${(M+1)}^2$, as the two elements range from $[0,M]$. Obviously, the obtained adjacent matrix is a symmetric matrix, as the equation Adj[i][j]=Adj[j][i] always exists.

4. Efficiency Prediction Based on Convolutional Neural Network

The proposed performance evaluation method aims to use the existing topology database to provide an efficient SCC topology for different kinds of applications under fixed input and output condition. This method can greatly reduce the time and cost of the design cycle. The evaluation scheme is illustrated in this section.

4.1. Data Collection and Preprocess

Different SCC topologies are input to a CNN model in the form of their adjacent matrix, as shown in Figure 6. The model randomly selects 36,000 different 4-to-1 SCC topologies, then their full-load efficiency $\eta$ is acquired by parallel simulation (Matlab/Simulink) and normalized. After complicated simulation and data processing based on the model shown in Figure 7, the efficiency data corresponding to each topology is obtained. Conduction loss, switch loss, and driving loss are taken into consideration.

Table 2. Simulation Parameters.

Parameter	Value
Input Voltage $V_{in}$	48 V
Output Voltage $V_{out}$	12 V
Switching frequency $f_{sw}$	1 MHz
Rated output power $P_{out}$	120 W
ESR of capacitor $R_{esr}$	2 mΩ

shows the detailed simulation parameters. As shown in Figure 7, the normalized data were divided into a training set and a testing set at a ratio of 5:1 after random sorting to remove data correlation.

4.2. Convolutional Neural Network Construction

A convolutional neural network (CNN) is a supervised deep learning algorithm that differs from typical neural networks in using convolution as an activation function. It is superior at dealing with matrix information or image processing, applied here to learning the underlying relationship between the adjacent matrices of SCC topologies and the conversion efficiency $\eta$. Figure 8 shows the structure of the applied CNN model, which was composed of a feature extraction part and a regression analysis part [21]. The former consisted of convolution layers, while the later consisted of fully connected hidden layers in which a non-linear activation function was employed in the neurons for nonlinear regression. Finally, the prediction efficiency was realized through the output layer. The loss function was defined as the mean absolute percentage error (MAPE), calculated as follows:

$$\mathrm{MAPE}=\frac{\sum \frac{|A-F|}{A}\times 100}{N}$$

(10)

The hyperparameters of the CNN model were adjusted by observing the convergence in the loss function of the training set. Finally, the Rectified Linear Unit (ReLU) was defined as the activation function of the hidden layer, and Sigmoid was selected as the activation function of the output layer. The number of epochs was set to as 50 and the Adam optimizer was selected. The details of the the CNN model structure are shown in

Table 3. Details of the CNN model.

Layer	CNN Model Parameter
Input layer	25 neurons
Conventional layer	Eight 3 × 3 conv2d padding = 1
Fully connected layer 1	128 neurons
Dropout layer	0.5
Fully connected layer 2	Eight neurons
Dropout layer	0.5
Fully connected layer 3	One neuron

.

5. Result and Analysis

Compared to hours of parallel simulation, the CNN algorithm can greatly shorten the calculation time and only needs several minutes to obtain the evaluation result of six thousand topologies. The convergence curve of the CNN model is shown in Figure 9. After 30 iterations, the error function gradually became constant. A comparative experiment with alternative artificial neural network (ANN) and linear regression approaches was designed to verify the outstanding performance of the CNN model. The details on the artificial neural network model are shown in

Table 4. Details of the ANN model.

Layer	ANN Model Parameter
Input layer	25 neurons
Fully connected layer 1	128 neurons (ReLU)
Dropout layer	0.5
Fully connected layer 2	Eight neurons (ReLU)
Dropout layer	0.5
Fully connected layer 3	One neurons (Sigmoid)

. The hyperparameters of the ANN were coordinated with those of the CNN, while the linear regression model can be expressed by

$$\widehat{y}=\mathbf{W}·x+\mathbf{b}$$

(11)

The prediction result of the different methods are shown in Figure 10. The red line represents the real efficiency data, while the blue line shows the prediction results. All the methods were able to predict the results to an extent, which proves the relationship between the topology and conversion efficiency. Prediction accuracy is the most intuitive evaluation indicator of model performance. Compared with linear regression and ANN, CNN is superior in prediction accuracy, as expected. The convolution algorithm can extract topology feature effictively and predict the operation performance based on its conversion structure.

Table 5. Comparison of implemented CNN model, ANN, and linear regression.

	MSE	MAPE	Calculation Time (s)
CNN	0.0072	0.013	403
ANN	0.0168	0.032	139
Linear Regression	0.0323	0.070	72

shows the prediction error of each method. The MAPE of the CNN model is 0.013, while for linear regression it is 0.07 and for ANN it is 0.03. Although the convergence speed of CNN is slower than the other two methods, it nonetheless saves a great deal of time compared with parallel simulation and manual evaluation, which can accelerate the design process compared to the current state-of-the-art.

These results show that the CNN model clearly outperforms the other two models. CNN can better fit the efficiency trend of different topologies, which clearly indicates it as a preferred choice for performance prediction of SCCs.

6. Conclusions and Future Work

This paper proposes a new evaluation performance method for SCCs by transforming the topology optimization issue into a typical nonlinear regression problem. Under the assumption that each capacitor value is same, an SCC can be described by means of its adjacent matrix. The method proposed in this paper outperforms existing evaluation methods in finding the most applicable topology, as well as in calculation efficiency and accuracy. A CNN model was selected to solve the regression problem. Our experimental results confirm that the CNN model greatly shortens the calculation time and that its prediction accuracy is within expectations. In our future work, we intend to continue our performance evaluation research using other machine learning methods, such as Graph Neural Network (GNN) and XGboost. Additional research efforts will be directed towards the efficiency evaluation of SCCs with parasitism and soft-switching converters, which could further facilitate the application of SCCs in industry.