SLLB-DEVS: An Approach for DEVS Based Modeling of Semiconductor Lithography Load Balance
Abstract
:1. Introduction
2. Methodology
2.1. The Legacy Load Balancer Model
2.2. Load Balancer Policy
- The scalability problemMost of the computation workload performs parallel processing on multiple computing nodes for fast processing. However, due to the saturation core point, performance does not increase linearly according to the number of computing nodes. Then saturation core point is easily reached. An E-beam job has the same limitations as a computation workload, and the allocation of computation nodes above the saturation core point causes an unnecessary waste of computing resources [16].
- The overspecification problemIf the load balancer operates ineffectively, the architecture designer favors the system hardware power over necessary performance. In this case, there is an advantage of providing a quick response, compared to the expected response time of the user. However, as a result, the actual usage time of the system is very low compared to the total time, which incurs unnecessary costs.
2.2.1. The Saturation Point Policy
2.2.2. The Mission Time Policy
2.3. Default DEVS Model Design
- The generatorThe generator creates E-beam jobs according to the distribution of jobs generated in the E-beam cluster. The E-beam job includes the attribute of the value of density. The density attribute value follows the Gaussian distribution. The load balancing simulation experiment for the E-beam job applies an empirical model, which requires a higher TAT for higher-density jobs. In order to facilitate the delay analysis in the experiment, each job density attribute should follow a Gaussian distribution.
- The load BalancerThe load balancer queues the job and observes the status of the idle server. It then performs the task of allocating the queued task to the appropriate server.
- The serverThe server performs the actual processing of the incoming job. Processing time follows the Gaussian distribution according to the number of core allocations and the density of the job. When the task is finished and becomes idle, it relays the current status to the load balancer.
- The reportThe report collects jobs that have finished working, and collects statistical information such as the TAT, the wait time, and the time to job completion in all assigned servers.
2.4. The Simulation Architecture
- First, various tasks with different characteristics are created and requested from the load balancer.
- The load balancer schedules a work order based on the current work, the idle resources of the server cluster, and the saturation point model.
- When the resources of the server cluster reach the scheduling condition, the next task is requested from the server cluster.
- The server cluster simulates the corresponding task and records the result in the form of a database or file.
- The result is analyzed using an analyzing tool.
3. Results and Discussion
3.1. The Default DEVS Model Simulation
3.2. Multi-Input DEVS Model Simulation
- Core 100
- Core 500
- Core 1500
- Core 2000
4. Conclusions
Author Contributions
Funding
Institutional Review Board Statement
Informed Consent Statement
Data Availability Statement
Conflicts of Interest
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Type | TAT (Hours) | Min Density | Max Density | Count |
---|---|---|---|---|
JOB_A | 3 | 5 | 30 | 100 |
JOB_B | 6 | 30 | 50 | 100 |
JOB_C | 12 | 50 | 70 | 100 |
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Han, Y.S.; Kwon, B.S.; Nam, C.S.; Lee, J.S. SLLB-DEVS: An Approach for DEVS Based Modeling of Semiconductor Lithography Load Balance. Appl. Sci. 2021, 11, 4235. https://doi.org/10.3390/app11094235
Han YS, Kwon BS, Nam CS, Lee JS. SLLB-DEVS: An Approach for DEVS Based Modeling of Semiconductor Lithography Load Balance. Applied Sciences. 2021; 11(9):4235. https://doi.org/10.3390/app11094235
Chicago/Turabian StyleHan, Young Shin, Bo Seung Kwon, Choon Sung Nam, and Jong Sik Lee. 2021. "SLLB-DEVS: An Approach for DEVS Based Modeling of Semiconductor Lithography Load Balance" Applied Sciences 11, no. 9: 4235. https://doi.org/10.3390/app11094235
APA StyleHan, Y. S., Kwon, B. S., Nam, C. S., & Lee, J. S. (2021). SLLB-DEVS: An Approach for DEVS Based Modeling of Semiconductor Lithography Load Balance. Applied Sciences, 11(9), 4235. https://doi.org/10.3390/app11094235