Monolithic 3D Inverter with Interface Charge: Parameter Extraction and Circuit Simulation

Abstract

We have simulated a monolithic three-dimensional inverter (M3DINV) structure by considering the interfacial trap charges generated thermally during the monolithic three-dimensional integration process. We extracted the SPICE model parameters from M3DINV structures with two types of inter-layer dielectric thickness T_ILD (=10,100 nm) using the extracted interface trap charge distribution of the previous study. Logic circuits, such as inverters (INVs), ring oscillators (ROs), a 2 to 1 multiplexer (MUX), and D flip-flop and 6-transistor static random-access memory (6T SRAM) containing M3DINVs, were simulated using the extracted model parameters, and simulation results both with and without interface trap charges were compared. The extracted model parameters reflected current reduction, threshold voltage increase, and subthreshold swing (SS) degradation due to the interface trap charge. HSPICE simulation results of the fanout-3 (FO3) ring oscillator considering the interface trap charges showed a 20% reduction in frequency and a 30% increase in propagation delay compared to those without the interface trap charges. The propagation delays of the 2 × 1 MUX and D flip-flop with the interface trap charges were approximately 78.2 and 39.6% greater, respectively, than those without the interface trap charges. The retention static noise margin (SNM) of the SRAM increased by 16 mV (6.4%) and the read static noise margin (SNM) of SRAM decreased by 43 mV (35.8%) owing to the interface trap charge. The circuit simulation results revealed that the propagation delay increases owing to the interface trap charges. Therefore, it is necessary to fully consider the propagation delay of the logic circuit due to the generated interface trap charges when designing monolithic 3D integrated circuits.

1. Introduction

Three-dimensional (3D) integration technology has been studied as a solution to the physical limitations of maintaining the road map predicted by Moore’s Law [1,2]. Compared to other 3D integration technologies, monolithic 3D integration (M3DI) enables very small inter-layer via to minimize the connection between the device and interconnection. Via in nm can significantly reduce the delay caused by interconnection [3]. M3DI is a 3D integration technology that sequentially fabricates two or more device layers instead of combining two processed substrates using through-silicon via (TSV). Due to sequential integration, low-temperature (<650 °C) processes must be applied to fabricate the upper layer device to ensure the quality of previous layers. Recently, LETI’s CoolCube^TM technology has succeeded in lowering the process temperature to below 650 °C [4,5]. However, even when a low-temperature process is applied, the silicon and oxide film interfaces of the previously fabricated layers are damaged by heat [6]. The generated interface trap charges make the threshold voltage and the current level of the device and the subthreshold swing (SS) worse. Subthreshold swing is amount of change in voltage according to current below the threshold voltage. When fabricating a circuit with M3DI, the effects of interface trap charges and electrical coupling due to inter-layer dielectric (ILD) distances should be considered. Previous studies investigated electrical coupling with the distance of the ILD when the interface trap charge was ignored [7,8,9,10,11] and extracted SPICE parameters of the monolithic 3D inverter (M3DINV) for the circuit design simulation [12]. However, for a realistic circuit design simulation, it is necessary to extract the SPICE model parameters considering the interface trap charge.

In this study, we introduced parameter extraction of SPICE model parameters of the top and bottom transistors in the M3DINV considering the interface trap charge distribution [13] extracted from the experimental data of the M3DINV [14] with inter-layer dielectric thickness (T_ILD) of 10 (coupling) and 100 nm (non-coupling). To verify the validity of the extracted SPICE model parameters of the M3DINV, technology computer-aided design (TCAD) and TCAD mixed-mode simulation were performed. The components of logic circuits, such as inverters, ring oscillators, 2 × 1 multiplexer (MUX), and D flip-flop and 6-transistor static random-access memory (6T SRAM), consisting of M3DINVs, were simulated using the extracted model parameters, and the simulation results, both with and without interface trap charges, were compared.

2. Interface Trap Charges in M3DINV

Figure 1 shows the M3DINV structure and the locations of the interface trap charges that can be generated during its fabrication. The M3DINV used in the simulation consists of N-type and P-type MOSFETs on the top and bottom layers, respectively [13,14]. Doping concentration of the MOSFET’s source/drain, lightly-doped doping (LDD), and the channel are 10²¹, 10¹⁸, and 10¹⁵ cm⁻³, respectively. The gate length and gate oxide thickness were simulated with a length of 30 nm and a thickness of 1 nm. SiO₂ was used for the gate oxide, ILD, and Box. The thicknesses of the ILD were 10 and 100 nm. In the TCAD simulation, the device simulator ATLAS [15] manufactured by Silvaco was used. The models used for device simulation were Lombardi CVT mobility, Shockley-Read-Hall Recombination, AUGER recombination, and Fermi-Dirac statistics. The extracted interface trap charge distribution was used for the simulation.

Figure 2 shows the interface trap charge distributions generated in the top and bottom gate-oxide and silicon interfaces extracted in a previous study [13] and the drain current-gate voltage (I_ds-V_gs) characteristics. The inset graph of Figure 2a shows the interface trap charge distribution generated at the ILD and silicon interface [13]. Figure 2b shows I_ds-V_gs characteristics obtained by fitting the interface trap charge extracted from the reference results [13]. The distribution is extracted by fitting the energy level and charge density parameter of the interface trap charge by using the TCAD simulation results with the same structure as the reference results. The I_ds-V_gs characteristics (lines) of the top and bottom transistors using the extracted interface trap charge were verified by matching the experimental data (symbols). Using the interface trap charge distribution extracted from the experimental data, the I_ds-V_gs characteristics according to various biases of this device were obtained by TCAD simulation. Based on the I_ds-V_gs characteristics of TCAD simulation, the SPICE model parameters of the bottom P-type and top N-type MOSFETs for circuit design are extracted as shown in

Table 1. Summary of extracted LETI-UTSOI model parameters for the bottom P-type MOSFET.

Parameter	Unit	Description	Value
DLQ	m	Effective channel length offset CV	4 × 10−8
VFBO	V	Geometry-independent flat-band voltage	0.3
CTO	-	Interface states factor	0.4
CICO	-	Geometry-independent part of substrate bias dependence factor of interface coupling	2.2
CFL	V−1	Length dependence of DIBL	1.3
UO	m2/V/s	Zero-field mobility	1.9 × 10−3
MUEO	m/V	Mobility reduction coefficient	4.3
THEMUO	-	Mobility reduction exponent	1
FETAO	-	Effective field parameter	3
PSCEL	-	Length dependence of short channel effect above threshold	0.15
THESATO	V−1	Geometry-independent velocity saturation parameter	3
AXO	-	Geometry-independent of linear/saturation transition factor	0
ALPL1	-	Length dependence of CLM pre-factor ALP	0.0005
VPO	V	CLM logarithm dependence factor	0.04
CGBOVL	F	Oxide capacitance for gate-substrate overlap	9 × 10−16
CFRW	F	Outer fringe capacitance	2.8 × 10−16

and

Table 2. Summary of extracted LETI-UTSOI model parameters for the top N-type MOSFET (coupling/non-coupling).

Parameter	Unit	Description	Value (TILD)
			10 nm	100 nm
DLQ	m	Effective channel length offset CV	4 × 10−8	4 × 10−8
VFBO	V	Geometry-independent flat-band voltage	−0.175	−0.26
CTO	-	Interface states factor	0.4	0.4
CICO	-	Geometry-independent part of substrate bias dependence factor of interface coupling	0.2	0.2
CFL	V−1	Length dependence of DIBL	0.4	1
UO	m2/V/s	Zero-field mobility	1.8 × 10−2	3.5 × 10−2
MUEO	m/V	Mobility reduction coefficient	1.5	7
THEMUO	-	Mobility reduction exponent	0.1	0.2
FETAO	-	Effective field parameter	1	0
PSCEL	-	Length dependence of short channel effect above threshold	0.14	0.06
THESATO	V−1	Geometry-independent velocity saturation parameter	7	1
AXO	-	Geometry-independent of linear/saturation transition factor	6	0.5
ALPL1	-	Length dependence of CLM pre-factor ALP	0.0002	0.002
VPO	V	CLM logarithm dependence factor	0.04	2
CGBOVL	F	Oxide capacitance for gate-substrate overlap	0	14 × 10−16
CFRW	F	Outer fringe capacitance	2.5 × 10−16	2.2 × 10−16
RSGO	-	Gate-bias dependence of RS	0.2	0.5

at T_ILD = 10 (and 100 nm), respectively. As the bottom layer P-type MOSFET is not affected by the thickness of the T_ILD, the extracted parameter is the same for T_ILD of 10 and 100 nm.

3. Parameter Extraction for Circuit Simulation

For circuit simulation, the LETI-UTSOI model (version 2.1) [16,17,18] in HSPICE [19] was used for the top and bottom MOSFETs [12].

Parameters of the LETI-UTSOI model were extracted by comparing them with the reference TCAD data. First, the threshold voltage (Vt) roll-off, subthreshold swing (SS) degradation, and interface state factor parameters were extracted. Next, the mobility and series resistance parameters, the velocity saturation parameters were extracted. For the short channel effect, the drain-induced barrier lowering (DIBL), and the channel length modulation (CLM) parameters were extracted. The process was repeated until the parameters were completely extracted. When the DC parameter extraction was complete, the output capacitance parameters were extracted. Finally, the back gate effect parameters were extracted.

To reflect the effect of interface trap charge, parameters such as interface state, threshold voltage, and mobility were used, as shown in Table 1 and Table 2. Figure 3a–c show the I_ds-V_gs characteristics of the bottom P-type MOSFET in M3DINV and the top N-type MOSFET at T_ILD = 10 and 100 nm, respectively. The symbols and lines denote the TCAD and HSPICE simulation results, respectively, using the extracted parameters both with and without interface trap charge distributions.

The drain voltages are 0.2, 0.6, and 1 V for N-type MOSFETs and −0.2, −0.6, and −1 V for P-type MOSFETs, respectively. In both top and bottom MOSFETs, the on-current levels are reduced, the threshold voltage is changed, and SS is reduced by the interface trap charge. The HSPICE circuit simulation results are in good agreement with the TCAD simulation results.

Figure 4 shows the total gate capacitance-gate voltage (C_g-V_gs) characteristics. Figure 4a–c shows the total gate capacitances of the bottom P-type MOSFET and top N-type MOSFETs at T_ILD = 10 and 100 nm, respectively. The solid and dashed lines show the total gate capacitances simulated with HSPICE without/with the interface trap charge, respectively, and the squares and circles show the total gate capacitances simulated with TCAD without/with the interface trap charge, respectively. In the bottom P-type MOSFET, the threshold voltage was shifted by approximately −0.176 V by the interface trap charge, and the maximum value of the gate capacitance was decreased by approximately 0.05 fF. In the top N-type MOSFETs at T_ILD = 10 and 100 nm, the threshold voltages are shifted approximately 0.13 and 0.083 V by the interface trap charge, respectively. However, changes in the minimum and the maximum values of the gate capacitance are hardly observed. The HSPICE simulation results also agree well with the total gate capacitance magnitude and trend within the error range.

Figure 5 shows the voltage transfer characteristics (VTC) of M3DINV both with and without the interface trap charge at T_ILD = 10 and 100 nm. The symbols and lines show the TCAD mixed-mode and HSPICE simulation results, respectively. The filled symbols (and solid lines) and empty symbols (and dashed lines) denote without and with the interface trap charge, respectively. The squares and triangles denote T_ILD of 10 and 100 nm, respectively. The HSPICE simulation results agree well with TCAD mixed-mode results. The switching threshold voltage V_m was shifted owing to the threshold voltage shift of the top/bottom MOSFETs by the interface trap charge. When the T_ILD is 10 and 100 nm, the V_m s shifts by 0.125 and 0.047 V, respectively.

Figure 6 shows the transient response characteristics of M3DINV at T_ILD = 10 and 100 nm. The load capacitance of M3DINV is C_L = 1 fF. The symbols and lines show the results of the TCAD mixed-mode and HSPICE circuit simulations, respectively. The black square (solid line), the red circle (red dotted line), and the green triangle (green dotted line) show the input and output voltages both with and without the interface trap charge, respectively. The HSPICE circuit simulation results match the TCAD mixed-mode results. The change in capacitance due to the interface trap charge at the interface is not large, but the on-current level is greatly reduced by the interface trap charge; thus, it can be confirmed that the propagation delays due to the reduced current increases.

Figure 7 shows the circuit diagram used for circuit simulation. Figure 7a–d are three stages fanout-3 ring oscillator [20], 2 × 1 MUX [21], D Flip-Flop [22], and 6T SRAM [23], respectively.

Table 3. FO-3 ring oscillator performance using extracted model parameters without interface trap charges (coupling/non-coupling).

Stages	Power [μW]		Frequency [GHz]		Delay per Stage [ps]
	10 nm	100 nm	10 nm	100 nm	10 nm	100 nm
3	281	274	18.7	22.1	9.04	7.59
19	279	272	2.88	3.37	9.16	7.81
101	281	276	0.52	0.62	9.28	7.93

and

Table 4. FO-3 ring oscillator performance using extracted model parameters with interface trap charges (coupling/non-coupling).

Stages	Power [μW]		Frequency [GHz]		Delay per Stage [ps]
	10 nm	100 nm	10 nm	100 nm	10 nm	100 nm
3	283	283	14.2	15.8	11.71	10.33
19	282	278	2.38	2.73	11.93	10.67
101	284	283	0.408	0.45	12.13	10.98

show the power consumption, frequency, and propagation delay of three types of fanout-3 ring oscillators (FO3-RO) consisting of M3DINVs both with and without interface trap charges, respectively. Table 3 and Table 4 show the simulation results of the HSPICE circuit of the FO3-RO both with and without interface trap charges at T_ILD = 10 and 100 nm, respectively. Comparing FO3-ROs both with and without interface trap charges, the power consumption of FO3-ROs with interface trap charges is almost same as that without them. However, the operating frequency of FO3-ROs with interface trap charges is reduced by approximately 20 and 25% at T_ILD = 10 and 100 nm, respectively and the propagation delay of FO3-ROs with interface trap charges is increased by approximately 30 and 36% at T_ILD = 10 and 100 nm, respectively.

Figure 8 shows the transient simulation result of the 2 × 1 MUX consisting of M3DINVs. The V_A, V_B, and V_SEL denote the input voltages, and V_OUTs denotes the output voltage of the 2 × 1 MUX at T_ILD = 10 and 100 nm. The solid and dashed lines of V_OUTs denote the circuit simulation results of the 2 × 1 MUX both with and without interface trap charges, respectively. Both the rising and falling propagation delay of the V_OUTs with interface trap charges are larger than those without the interface trap charges.

Table 5. Propagation delay and power consumption of the 2 × 1 MUX [21] and D FLIP-FLOP [22] consisting of M3DINVs both with and without interface trap charges (coupling/non-coupling).

	2 × 1 MUX				D Flip-Flop
	No-trap [10]		Trap		No-trap [10]		Trap
TILD [nm]	10	100	10	100	10	100	10	100
Propagation delay [ps]	2.3	1.95	4.1	3.75	10.2	8.35	16.2	13.7
Power Consumption [μW]	22.6	18.4	29.7	27.8	41.9	39.3	47.4	45.1

shows the propagation delay and power consumption of the 2 × 1 MUX and D flip-flop consisting of M3DINVs both with and without interface trap charges at T_ILD = 10 (and 100) nm. The propagation delays of the 2 × 1 MUX and D flip-flop with interface trap charges are approximately 78.2% (and 92.1%) and 39.6% (and 64.2%) greater than those without interface trap charges, respectively. The power consumptions of the 2 × 1 MUX and D flip-flop with interface trap charges are approximately 31.4% (and 51%) and 13.1% (and 14.7%) greater than those without interface trap charges, respectively.

Figure 9 shows the butterfly curve result of the 6T SRAM [23] consisting of M3DINVs. Figure 9a,b shows the retention and read static noise margins (SNMs) at T_ILD = 10 nm, respectively. Figure 9c,d shows the retention and read SNMs at T_ILD = 100 nm, respectively. The symbols and lines denote the SNMs of SRAM both with and without interface trap charges, respectively. The differences between T_ILD = 10 and 100 nm in the retention SNMs and the read SNMs of SRAM without interface trap charge are approximately 5 mV (1.8%) and 8 mV (7.14%), respectively. They reflect the trend in SNMs of planar 6T SRAM (neglecting any coupling between the P-type and N-type MOSFETs, almost equivalent with T_ILD = 100 nm) and 3D 6T SRAM (including coupling between the P-type and N-type MOSFETs, almost equivalent with T_ILD = 10 nm) [24]. The retention and read SNMs of the SRAM with T_ILD = 10 nm increased by 17 mV (6.4%) and decreased by 43 mV (35.8%) owing to the interface trap charges, respectively. The retention and read SNMs of SRAM with T_ILD = 100 nm increased by 10 mV (3.6%) and decreased by 40 mV (55%) due to the interface trap charges, respectively.

4. Conclusions

In this paper, we investigated the effect of interface trap charge distribution extracted from the experimental data of the M3DIC fabricated by LETI [14] in terms of electrical characteristics and extracted the distribution with TCAD at two types of T_ILD. To simulate the circuit considering the effect of the interface trap charge in M3DICs, SPICE model parameters of P-type MOSFET (bottom) and N-type MOSFET (Top) in M3DINV, including the interface trap charge distributions, were extracted by using TCAD simulation. To verify the validity of the extracted parameters in the SPICE M3DINV model, the HSPICE simulation results were compared with the TCAD mixed-mode simulation, and they agreed well with the TCAD mixed-mode results. When the interface trap charges were considered, the current level decreased, the threshold voltage shifted, the SS became worse, and the total gate capacitance changed slightly. It was observed that the propagation delays of M3DINV with the interface trap charges increased more than those without the interface trap charges owing to a reduced on-current level due to the interface trap charges. Using the extracted parameter model, the HSPICE simulation results of the FO3 ring oscillator considering the interface trap charges showed a 20% (and 25%) reduction in frequency and a 30% (and 36%) increase in propagation delay than those without the interface trap charges at T_ILD = 10 (and 100) nm. The propagation delays of the 2 × 1 MUX and D flip-flop with the interface trap charges were approximately 78.2% (and 92.1%) and 39.6% (and 64.2%) greater than those without the interface trap charges, respectively. The power consumption of the 2 × 1 MUX and D flip-flop with the interface trap charges was approximately 31.4% (and 51%) and 13.1% (and 14.7%) greater, respectively, than those without the interface trap charges. The retention SNM of the SRAM increased by 16 mV (6.4%) and the read SNM of SRAM decreased by 43 mV (35.8%) owing to the interface trap charge. The retention SNM of the SRAM increased 10 mV (3.6%) and the read SNM of SRAM decreased by 40 mV (55%) owing to the interface trap charge at T_ILD = 100 nm. For the coupling (T_ILD = 10 nm), the stage propagation delay and power consumption increased. The delays and power consumptions of M3D logics with T_ILD = 10 (coupling) and 100 nm (non-coupling) increased owing to the interface trap charges.

Therefore, it is necessary to fully analyze the electrical performance (such as the delay, power, the integration of logic circuits, and the stability of the SRAM considering electrical coupling [11,12] and interface trap charges) when designing M3DIC and M3D memories.