Monolithic 3D Inverter with Interface Charge: Parameter Extraction and Circuit Simulation
Round 1
Reviewer 1 Report
This paper extracts the SPICE model parameters of a monolithic 3D inverter with interface charge. Although it does not present a novel idea, the presented practice and its results are interesting and helpful.
The main part of the paper is section 2 and 3. The method and results are well understood, however, the exact method of parameter extraction including the formulation is not described in detail. Please strengthen your extractions by required formula and details.
Also, to add clarification to plots, I suggest to add grid lines to them. Some titles are italic and some are not. Please revise them.
Author Response
This paper extracts the SPICE model parameters of a monolithic 3D inverter with interface charge. Although it does not present a novel idea, the presented practice and its results are interesting and helpful.
The main part of the paper is section 2 and 3. The method and results are well understood, however, the exact method of parameter extraction including the formulation is not described in detail. Please strengthen your extractions by required formula and details.
--> Thanks for your comments. According to your suggestions we added the method of parameter extraction in L.92-99, P3. The formula for the LETI-UTSOI model is indicated as a reference [17-18].
Also, to add clarification to plots, I suggest to add grid lines to them. Some titles are italic and some are not. Please revise them.
--> Thanks for your comments. I would revise the manuscript according to your comments.
Author Response File: 
Author Response.pdf
Reviewer 2 Report
This work is an extension of previous work regarding simulations of a monolithic 3D inverter experimentally built by another group. In this work interface traps are added to the inverter model, and it is used as a building block for other devices such as ring oscillators, 2x1 multiplexers, and D flip-flops.
The work is interesting, and I have only a few comments:
-The abstract should be extended highlighting the results of this work. Also, the acronyms TILD and SS should be defined.
-The inset in Fig. 2 has low resolution making it difficult to read.
-A more in-depth description of the devices designed using the 3D inverter is mandatory. In particular, schematics of the ring oscillators, 2x1 multiplexers, and D flip-flops are needed. Do the simulations take into account the parasitic effects of metal connections? The oscillation frequency above 10 GHz could be heavily affected by metal parasitic components.
-Table 3 has data from three oscillators with different numbers of stages. Why is the power of the three oscillators the same?
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Author Response
This work is an extension of previous work regarding simulations of a monolithic 3D inverter experimentally built by another group. In this work interface traps are added to the inverter model, and it is used as a building block for other devices such as ring oscillators, 2x1 multiplexers, and D flip-flops.
The work is interesting, and I have only a few comments:
-The abstract should be extended highlighting the results of this work. Also, the acronyms TILD and SS should be defined.
--> Thanks for your comments. According to your suggestions we modified the abstract. We added also a full name of acronyms TILD and SS in L.45, P.1 and 54, P.2
-The inset in Fig. 2 has low resolution making it difficult to read.
--> Thanks for your comments. According to your suggestions we modified Figure 2 and the insert by increasing the resolution.
-A more in-depth description of the devices designed using the 3D inverter is mandatory. In particular, schematics of the ring oscillators, 2x1 multiplexers, and D flip-flops are needed.
--> Thanks for your comments. According to your suggestions we added schematics of logic circuit in Fig. 7.
Do the simulations take into account the parasitic effects of metal connections? The oscillation frequency above 10 GHz could be heavily affected by metal parasitic components.
--> Thanks for your comments. Parasitic effects of metal connections were not taken into account in this study. However, parasitic effects of metal connections were taken into account in the previous paper on parameter extraction of M3DI without interface trap charge. The parasitic effects of metal connections of M3DI without interface trap charge will be taken into account in further studies.
[Ahn, T.J.; Perumal, R.; Lim, S.K.; Yu, Y.S. Parameter Extraction and Power/Performance Analysis of Monolithic 3-D Inverter (M3INV). IEEE Trans. Electron Devices. 2019, 66, 1006–1011, doi: 10.1109/TED.2018.2885817.]
-Table 3 has data from three oscillators with different numbers of stages. Why is the power of the three oscillators the same?
--> Thanks for your comments. The power consumption in Table 3 represents the average power consumption per stage consumption.
Author Response File: Author Response.pdf
