A Study on Reducing Loss in PCB Motor Stator Using Multi-Via Structure

Abstract

This study proposes a multi-via structure as a loss-reduction design technique to mitigate current crowding in a slotless axial flux permanent magnet motor (AFPM) equipped with printed circuit board (PCB) stators. The PCB stator enables high current density operation through parallel copper-foil stacking and supports an ultra-compact structural configuration. However, current concentration in the via regions can increase copper loss and phase resistance. In this work, the via position and diameter were defined as design variables to perform a sensitivity analysis of current distribution and phase resistance variation. The effects of current density dispersion and the potential for copper loss reduction were evaluated using three-dimensional finite-element analysis (FEA). The results confirm that adopting a multi-via structure improves current path uniformity and reduces electrical losses, thereby enhancing overall efficiency. Furthermore, the analysis shows that excessive via enlargement or overuse does not necessarily yield optimal results and, in certain cases, may lead to localized current peaks. These findings demonstrate that the multi-via structure is an effective and appropriate design strategy for PCB stators and highlight the importance of optimized via placement tailored to each stator configuration.

1. Introduction

The global mobility market, including shared, electric, and autonomous services, is expected to grow at a compound annual rate exceeding 12% through 2030 [1]. An academic survey of shared-mobility business models likewise confirms that double-digit compound growth will persist into the mid-2020s [2]. This expansion sharply increases the demand for compact actuators that must be installed in large numbers inside vehicles [3].

An anti-lock braking system (ABS) requires one miniature hydraulic pump motor per wheel—four per vehicle—and must deliver counter-torque within a few milliseconds after slip is detected [4]. Experiments published in Actuators report torque-response times below 15 ms for electric actuators [5]. To meet such high-speed control requirements, axial flux permanent magnet (AFPM) machines have attracted considerable interest. By generating torque in the radial direction, AFPMs achieve both high torque density and a short axial length, enabling efficient operation in severely space-constrained environments [6,7]. Laminated core AFPMs, however, suffer from intricate coil insertion, localized heat concentration, and tight manufacturing tolerances [8].

Printed circuit board (PCB) coreless AFPMs have emerged to overcome these limitations. Removing the magnetic core eliminates iron loss, while multilayer parallel copper traces provide a high conductor fill factor. Since the experimental demonstration of an ultra-thin AFPM employing dual-stator PCB windings [9], electromagnetic and thermal performance have been continuously improved through composite coil architectures [10] and refined PCB winding designs [11]. A slotless PCB-wound electric/hydraulic brake (EHB) motor has further shown that a flat form factor and rapid dynamic response can be achieved simultaneously [12]. A comparative optimization study on brake-by-wire (BBW) actuators has reinforced the suitability of PCB-AFPMs for high-response braking systems [13].

The parallel layer structure of PCB stators accommodates high current while distributing it laterally, thereby reducing copper loss. When driven by GaN-FET power electronics, PCB windings have achieved substantial gains in power density [14]; eddy current and circulating current losses associated with variations in the number of winding layers have also been quantified [15]. Optimizing thermal-via placement alone has been reported to lower the winding temperature of a PCB-AFPM by more than 15 °C [12].

Nonetheless, the vias that interconnect the layers of a multilayer PCB winding concentrate current locally, increasing the current density within the via and raising phase resistance [16]. Multiphysics analysis shows that, under pulsed excitation, temperature rise at the winding–via junction of a PCB-wound AFPM is pronounced, making thermal management essential [17]. A comparative study of PCB winding patterns in high-speed coreless AFPMs further reports that via layout markedly affects circulating and eddy current losses, which in turn play a decisive role in overall efficiency [18]. Although electric machines generally incur multiple loss components, including iron, mechanical, and stray losses, their contribution is negligible in the structure considered. The rotor, composed of solid S45C carbon steel, rotates synchronously with the stator field, thereby preventing relative flux variation and suppressing eddy current formation. The stator, built from laminated non-oriented electrical steel (35PN230), limits circulating currents through its lamination layers, which minimizes eddy current losses and leaves hysteresis loss as the dominant core component [19]. Consequently, copper loss emerges as the principal loss mechanism in coreless PCB stators under high current density, and this study therefore focuses on copper loss minimization through multi-via optimization. The quantitative relationships between via geometry (diameter, number, and placement) and phase resistance or peak current density remain insufficiently characterized [20]. A systematic review of 38 papers published between 2019 and 2024 highlights the absence of predictive via-loss models as a major research gap [21].

Previous studies have mainly focused on qualitative comparisons of PCB winding structures in terms of thermal and loss characteristics, while systematic investigations into the quantitative relationship between via diameter, number, layout, and the resulting phase resistance and current density remain limited. Therefore, the originality of this study lies in conducting a comparative FEM analysis of single-via, inline multi-via, and grid multi-via structures under identical conditions, clarifying the trade-off between phase resistance, current density, and copper loss, and proposing an optimized via layout design strategy tailored for actuator-oriented PCB AFPM. Using a three-phase, two-turn PCB stator rated at 114.67 W for an ABS actuator as a case study, the effects of via diameter, number, and placement on phase resistance and peak current density are systematically compared. The results show that simply enlarging or increasing the number of vias does not guarantee optimal performance; in certain cases, local current spikes cause a non-linear rise in phase resistance. The proposed grid multi-via layout reduces phase resistance and peak current density by 20.76% and 20.72%, respectively, relative to the single-via baseline, lowering copper loss by 10.4% while remaining compatible with standard PCB fabrication.

The remainder of this paper is organized as follows. Section 2 introduces the basic design of the PCB distributed-winding motor for actuators. Section 3 presents the multi-via design of the PCB stator. Section 4 describes the FEM methodology and performance evaluation. Finally, Section 5 concludes the paper.

2. Basic Design of PCB Distributed Winding Motor for Actuators

2.1. Distributed Winding PCB Axial Flux Permanent Magnet Motor

Figure 1 shows an axial flux permanent magnet motor (AFPM) equipped with a PCB stator. Replacing the conventional laminated iron core with a slotless PCB stator greatly simplifies the design and markedly shortens the axial length [10,11]. In a traditional AFPM, windings must be wrapped around stator teeth, complicating manufacturing and increasing stack height [6]. In contrast, printing conductors directly onto the PCB substrate eliminates tooth geometry and enables a much thinner profile [12]. Formed from ultra-thin copper foil and supported by a parallel layer architecture, the PCB windings can withstand high current densities—indeed, PCB stators have been reported to operate at current densities three to four times higher than those of conventional wound machines without thermal issues [15]. Once the circuit pattern is finalized, automated printing accelerates production and lowers cost; in addition, the PCB fabrication process offers high repeatability and minimal quality variation, providing clear advantages for high-volume applications such as compact precision actuators [20].

Table 1. Design parameters of the PCB AFPM motor model.

Parameter	Unit	Value
Magnet	-	N45UH
Rotor	-	S45C
Stator	-	35PN230
Number of phases	-	3
Magnet thickness	mm	2.7
Rotor backyoke thickness	mm	2.7
Stator backyoke thickness	mm	2
Outer diameter	mm	65.4
Inner diameter	mm	20.6
Axial length	mm	10.1

summarizes the key design parameters of the proposed PCB AFPM motor model, including the material specifications of the magnet, rotor, and stator, as well as the principal geometric dimensions (outer diameter, inner diameter, axial length, and back-yoke thickness). This information defines the baseline configuration used in the FEM simulations and clarifies the structural constraints of the analyzed model.

Table 2. 3D Finite element analysis (3D FEA) data.

Parameter	Unit	Conventional Model
Back EMF	Vrms	3.23
Rated Speed	Rpm	3650
Load Torque	Nm	0.3
Current	Arms	12.37
Current density	A/mm2	29.46
Copper Loss	W	48.52
AC Loss	W	5.2
Output Power	W	114.67
Efficiency	%	68.10

summarizes the key performance metrics of the proposed motor, obtained through three-dimensional finite-element analysis (3D FEA) under rated operating conditions. At a rated speed of 3650 rpm, the motor delivers an output power of 114.67 W with a corresponding shaft torque of 0.3 Nm. The phase current is set to 12.37 Arms, resulting in a peak current density of 29.46 A/mm² in the conductor region. Copper and ac losses are estimated at 48.52 W and 5.2 W, respectively, leading to a total input power of approximately 168.4 W. Under these conditions, the overall efficiency is calculated to be 68.10%. The back-EMF at rated speed under no-load conditions is 3.23 Vrms.

2.2. Trace Configuration of the Distributed Winding PCB Motor

Figure 2a shows the single-phase PCB substrate, whereas Figure 2b shows the three-phase PCB substrate. The stator integrates all three phases on a single board, adopting a distributed winding layout with a pole-to-slot ratio of 1:3 [11]. Six copper layers are stacked to obtain two turns per slot for each phase, and the upper and lower layers are electrically linked through vias, guaranteeing uninterrupted current flow in the multilayer PCB [11]. As illustrated in Figure 2a, each phase appears to split into two separate conductor shapes, but these traces are connected through end-turns to form one continuous current path; the two shapes are, therefore, segments of the same phase rather than independent phases. Figure 2b consequently represents a complete three-phase, two-turn (3Φ 2T) winding configuration. Compared with conventional winding techniques, this PCB stator greatly simplifies manufacturing and is well suited to scalable mass production [12,20]. The design is especially advantageous for ultra-compact precision-actuator applications, where severe space constraints demand a thin, low-profile structure that still meets strict packaging requirements [3].

Figure 3 presents a cross-sectional view of the effective copper traces interconnected by via holes. The effective copper trace serves as the primary current-carrying path that directly contributes to torque generation. The effective traces for each phase are distributed across different PCB layers and electrically connected through vias to form a closed-loop circuit. These traces function as active conductors that interact magnetically with the rotor to deliver driving force.

Figure 4 shows the cross-section of the PCB winding layers. The end-turn traces provide return paths between effective copper traces within the same phase, and, positioned along the inner and outer boundaries of the PCB stator, the current begins at the inner end-turns (Layers 3 and 6), passes sequentially through each layer via the vias, and exits through the outer end-turns [11]. Although the end-turn traces themselves do not directly contribute to torque generation, they are essential for maintaining current continuity and circuit completeness [11]. Consequently, the structure consists of six parallel effective copper traces and two parallel end-turns on the inner and outer sides, establishing a stable two-turn current loop per phase. This parallel conductor arrangement lowers both resistance and copper loss, thereby enhancing overall efficiency [12].

The conductor resistance R is defined by Equation (1):

$$R=\rho {\displaystyle \frac{L}{A}}$$

(1)

where $\rho$ is the electrical resistivity, L is the current-path length, and $A$ is the conductor cross-sectional area.

$$A_{Total}=N·A$$

(2)

When the number of parallel conductors is N, the total effective cross-sectional area increases as shown in (2), which directly leads to a reduction in the overall conductor resistance.

Figure 5 presents a three-dimensional exploded view of the plated via structure in the multilayer PCB stator. The inner wall of each drilled via is coated with a 25 µm copper layer, forming a cylindrical conductor [11]. Via pads on every layer act as bonding sites for the plating, providing dependable electrical connections to the upper- and lower-layer copper traces, while multiple FR-4 prepreg layers insulate adjacent copper sheets and preserve mechanical rigidity [11]. These vias link the upper and lower conductor traces, completing the current path across the six-layer PCB stack.

Effective conductor traces constitute the primary copper paths that carry current and generate torque; traces distributed across different layers are electrically interconnected through the vias to produce a single closed circuit with two turns per phase [11]. End-turn traces offer return paths within each phase, running between the inner (Layers 3 and 6) and outer end-turns and positioned along the stator boundary to maintain continuity of the inter-layer conductor network [11]. Fabricated with the standard 25 µm plating thickness, the vias align precisely with the pads of both effective and end-turn traces, thereby reducing electrical resistance and mitigating current crowding in the multilayer structure [16,17]; this ensures stable, well-distributed current paths even under high current density conditions [17].

The integrated architecture enables straightforward manufacturing while preserving an ultra-thin, lightweight form factor [12], delivering high electromagnetic performance and electrical reliability for space-constrained applications such as compact precision actuators [3].

2.3. Distributed Winding End-Turn Structure of the PCB Stator

Figure 6 shows a three-dimensional enlarged view of the plated via network in the three-phase, two-turn PCB stator. Black arrows mark the current direction along each layer’s effective trace, and yellow columns depict inter-layer current flow through the vias. The stator integrates three phases with two dedicated end-turn layers per phase; this separation minimizes inter-phase interference and physically isolates each phase’s current path [11]. The total number of end-turn layers is determined by the turns per slot and the number of parallel PCB layers, which together close the current loop [11]. The parallel layer arrangement was tuned within the feasible design range to optimize end-turn placement, yielding a stable current distribution across all traces. As Figure 6 illustrates, the stator employs a distributed winding strategy that exploits the end-turn regions, providing magnetic force balancing and current distribution benefits comparable to those of conventional slotted distributed windings—even in a slotless structure [6]. End-turns interconnect the effective traces of each phase through vias, so current flows in a distributed manner across the parallel conductors, lowering current density and conductor resistance and thereby reducing copper loss [15]. Finally, the via-based inter-layer connections keep current path lengths among the effective traces precisely aligned, contributing to balanced torque generation across all three phases [11].

3. Multi-Via Design of the PCB Stator

3.1. Limitations of Conventional Single-Via Structures

Figure 7 shows the current density distribution concentrated inside the via of the conventional single-via model. The simulation results indicate peak current densities exceeding 5 × 10⁵ A mm⁻² along the via wall (red region), whereas the surrounding copper traces exhibit much lower values (cyan–green regions). Although a single via links the inter-layer current paths in a multilayer PCB, the actuator-grade AFPM PCB stator investigated here must carry 12.37 A to deliver its rated output of 114.67 W; consequently, a single-via configuration cannot distribute the current effectively. Under the limited copper plating thickness of 25 µm, local heating and thermal saturation risks increase, the effective cross-sectional area for current flow is restricted, phase resistance rises, and both power loss and efficiency degradation occur [17]. Over prolonged operation, such thermal and electrical concentration can weaken via reliability and elevate the likelihood of failure [17].

Figure 8 illustrates the cross-sectional layout of the via hole, plated copper barrel, and surrounding pad area. A PCB via is a cylindrical conductor formed by plating the inner wall of a drilled hole; its conductive cross-section is determined by the plating thickness and the drill diameter. The effective current-carrying area of the via is represented by an annular cross-section, as expressed in Equation (3).

$$A_{Via}=\pi \left(r^2-{\left(r-t\right)}^2\right)=\pi (2rt-t^2)$$

(3)

where $r$ is the radius of the drilled hole, and $t$ is the plating thickness of the via wall.

$$t \ll r$$

(4)

In most cases, as shown in Equation (4), the expression can be approximated and simplified as in Equation (5).

$$A_{Via}\approx 2\pi rt$$

(5)

Accordingly, the electrical resistance of the via is given by the general conductor-resistance formula, as shown in Equation (6).

$$R_{Via}=\rho ·{\displaystyle \frac{l}{A_{Via}}}\approx \rho ·{\displaystyle \frac{l}{2\pi rt}}$$

(6)

where $\rho$ is the electrical resistivity of copper, and $l$ is the PCB thickness (i.e., the via length). Equation (6) shows that the via resistance $R_{Via}$ decreases as the via radius $r$ increases. Nevertheless, from a practical design standpoint, arbitrarily enlarging the via radius is undesirable for three reasons. First, because the conductive copper is only a thin plated layer of thickness t, increasing the drill radius reduces the proportion of conductive plating in the via’s cross-sectional area [17]. Second, an excessively large via diameter restricts routing space on the PCB and undermines the mechanical and thermal robustness of the current path [16]. Third, since the plating thickness t is fixed by process constraints, increasing the radius alone does not meaningfully improve current-carrying capacity [17].

$$\pi (2rt-t^2)$$

(7)

The effective cross-sectional area of a via is given by Equation (7) when the plating thickness $t$ is much smaller than the radius $r$, the area can be approximated as $2\pi rt$. Accordingly, the via resistance is defined by Equation (8) and, in theory, decreases as the via radius increases.

$$R=\rho l/\left(2\pi rt\right)$$

(8)

However, as the drill diameter grows, the proportion of the actual copper conductive layer within the cross-section diminishes, indicating that enlarging a single via’s diameter is not an effective way to reduce resistance.

3.2. Multi-Via Structure

Figure 9 compares the single-via and multi-via configurations in the inner and outer end-turn regions. The single-via configuration (left) employs one plated through hole for each layer-to-layer connection, whereas the multi-via configuration (right) incorporates multiple parallel vias to reduce local current crowding and lower effective resistance. The top images show enlarged views of the inner end-turn region, while the bottom images illustrate the outer end-turn region. All conductor layers are implemented on a multilayer PCB with 2 oz copper plating. In the single-via structure, each effective conductor layer is interconnected by only one via, producing several disadvantages. First, the current is forced through a narrow path, resulting in a high current density within the via [17]. Second, the limited cross-sectional area raises electrical resistance and, consequently, copper loss [17]. Third, the associated thermal concentration can degrade long-term reliability [16]. Because the via lies directly on the main current path, its resistance adds to the total equivalent resistance, and the elevated local current density concentrates heat in the via, accelerating aging and reducing durability [16,17].

Therefore, a multi-via design must do more than simply increase the via count; the vias must be placed strategically along the current path to minimize loss and provide an optimized, reliable layout [16]. To systematically evaluate and optimize the multi-via design, this study employed a step-by-step procedure. First, a two-turn PCB stator consisting of two 6-layer boards was chosen as the baseline configuration, considering the trade-off between back-EMF requirements and AC loss. This selection reflects a limitation inherent to the chosen motor topology, which may restrict the direct applicability of the results to other winding patterns. Step 1: The single-via structure was analyzed by gradually varying the via diameter to establish reference trends in phase resistance and current density. Step 2: Inline multi-via structures were introduced, and the effects of sequential via placement at the inner and outer end-turns were examined. Step 3: Grid multi-via structures were applied, distributing multiple smaller vias across the conductor segment to improve current sharing and reduce resistance. Step 4: Finally, the inline and grid configurations were quantitatively compared, and the optimal layout was identified by balancing current distribution effectiveness with conductor area utilization.

3.3. Inline-Type and Grid-Multi-Via Structures

The top row shows the inline configuration, while the bottom row presents the grid configuration. (a) and (b) display the inner and outer end-turns of the inline design, where vias are sequentially inserted from the conductor tip. (c) and (d) illustrate the grid design, in which multiple parallel vias are distributed throughout the conductor segment to equalize current density. Compared with the inline configuration, the grid structure more effectively mitigates current crowding, reduces resistance, and enhances thermal dissipation, while maintaining full compatibility with standard PCB fabrication processes.

Figure 10a shows the inline multi-via structure at the inner end-turn. Vias are arranged in a single row and inserted in the sequence 1 → 2 → 3, starting from the terminal end of the conductor. This layout directs incoming current from the inner side through the conductor tip first, mitigating localized current concentration and reducing heat generation.

Figure 10b presents the inline multi-via structure at the outer end-turn. Although the physical order is 3 → 2 → 1, the insertion sequence remains 1 → 2 → 3. This arrangement distributes current entering from the outer side toward the conductor tip first, optimizing the current path and enhancing both electrical and thermal performance.

Figure 10c illustrates the grid multi-via structure at the inner end-turn. Each row consists of a pair of vertical vias, added sequentially in the order 3 → 2 → 1. Consequently, two, four, and six vias are distributed across the conductor segment, effectively reducing current density and electrical resistance.

Figure 10d shows the grid multi-via structure at the outer end-turn. While the physical arrangement is 3 → 2 → 1, the insertion sequence again follows 1 → 2 → 3. Because current enters from the outer side, prioritizing via connections near the conductor tip minimizes thermal loss and electrical resistance.

In the two-turn conductor pattern used in this study, the grid multi-via approach offers superior electrical performance compared with the inline configuration. In inline designs, if space is insufficient for multiple vias at the same location, enlarging the via diameter can lower internal current density; however, the resulting larger plated area occupies more of the effective conductor, reducing copper cross-section and increasing phase resistance. When adequate spacing between conductors is available—as in the present two-turn layout, the grid method, which distributes multiple small vias, more effectively mitigates current density and lowers resistance. Considering factors such as number of turns, conductor width, via arrangement, parallel current paths, and manufacturability, the grid multi-via configuration is optimal for a two-turn PCB stator. This design provides superior resistance reduction and thermal dissipation performance while remaining compatible with standard PCB fabrication processes.

3.4. Simulation Conditions

In this study, the rotor and stator structures were kept identical; only the via configuration was varied to compare and analyze electrical characteristics such as phase resistance and current density. The analysis conditions were as follows. First, for the single-via structure, the via diameter was gradually increased, and the resulting changes in phase resistance and current density distribution were evaluated. This analysis considered both the reduction in current density due to the enlarged via diameter and the opposing effect of decreased effective conductor area—caused by the enlarged plated via region within the same conductor width—on resistance behavior. Second, for the multi-via structures, two configurations were investigated: inline multi-via and grid multi-via. For both configurations, the via diameter was incrementally increased within the same effective conductor width. The current distribution effect and conductor loss characteristics of each structure were then compared. Through this evaluation, an electrical performance optimization strategy was established by balancing the benefit of an increased plated via area against the reduction in effective conductor cross-section.

In addition, the finite-element simulations were performed using ANSYS Maxwell 3D, Release 2025 R2 with the Eddy Current Solver for resistance and current density evaluation. Adaptive meshing with a minimum element size of 200 μm was applied to ensure accuracy, and representative mesh distributions are shown in Figure 11. Specifically, the mesh applied to the PCB stator and via regions for eddy current analysis is presented in Figure 11a, while Figure 11b,c illustrates the mesh discretization of the multilayer PCB circuit and the refined airgap/airband region used in transient electromagnetic simulations for torque and dynamic field evaluation. No special boundary conditions were applied beyond the default solver settings.

4. FEM Methodology and Performance Evaluation

4.1. Analysis Items

The stator employs a parallel layer configuration with two vias—inner and outer—allocated to each slot. These vias electrically connect the upper and lower effective conductors, enabling current distribution across layers. In this study, the diameters of the inner and outer vias were varied independently to evaluate their effects on phase resistance and current density, with the aim of identifying the optimal combination of via diameter and placement. The analysis began with the single-via structure, uniformly increasing both inner and outer via diameters in successive FEM simulations. Building on these results, inline multi-via (IM-via) and grid multi-via (GM-via) configurations were then applied to the inner and outer regions. After determining the inner via condition that minimized phase resistance, the same procedure was applied to the outer via to obtain the overall optimal layout. This step-by-step approach allowed separate sensitivity studies of phase resistance and current density with respect to via diameter and layout, enabling a quantitative optimization that balances current distribution effectiveness against conductor area utilization.

4.2. FEM-Based Performance Analysis

Figure 12 shows that, in the single-via configuration, a via diameter of 0.60 mm produces the lowest values—0.1008 Ω in phase resistance and 425 A/mm² in peak current density—corresponding to reductions of approximately 4.63% and 22.73%, respectively, relative to the 0.30 mm baseline. These improvements stem from the enlarged effective current path and enhanced current spreading that accompany an increase in via diameter, which mitigate loss and local heating caused by current crowding. Once the via diameter surpasses this optimal value, however, both phase resistance and peak current density rise again because the larger via removes copper from the effective conductor, narrowing the remaining conductive path. Simply enlarging a single via, therefore, does not always reduce resistance; beyond a certain point, it can have the opposite effect. Optimal via design must balance current spreading effectiveness against retention of a sufficient copper cross-section.

Based on the preceding single-via analysis, Figure 13 evaluates phase resistance and current density characteristics by incrementally applying the IM-via structure to the inner via while keeping the outer via fixed at the baseline diameter of 0.30 mm. For each via position (1st, 2nd, and 3rd), the diameter was varied from 0.30 mm to 0.70 mm, and the resulting phase resistance values were quantitatively compared. The lowest phase resistance occurs with a 0.50 mm diameter for the 1st via and 0.30 mm for the 2nd via, identifying this pair as the optimal IM-via configuration. Adding a 3rd via provides only marginal resistance reduction, and in some cases even increases resistance, because additional vias reduce the effective conductor area and distort the current path, leading to local crowding and extra loss. The graph in Figure 13 plots the minimum phase resistance value obtained for every via-diameter combination (0.30–0.70 mm) at the 1st, 2nd, and 3rd positions, making the optimal design point easy to identify. In summary, for the IM-via structure, the 1st-via 0.50 mm and 2nd-via 0.30 mm combination is optimal. These results confirm that precise coordination of via position and diameter, rather than simply increasing the via count, is essential for improving electrical performance.

Figure 13, under the same conditions as the IM-via analysis in Figure 12, evaluates phase resistance and current density characteristics by fixing the outer via at the baseline diameter of 0.30 mm and applying a GM-via configuration to the inner via. In the GM-via scheme, two vias are placed in parallel across the conductor width at each position. Considering space constraints and conductor interference, the via diameter was varied from 0.30 mm to 0.40 mm. The analysis proceeded in three stages: two vias at the 1st position, four vias at the 1st + 2nd positions, and six vias at the 1st + 2nd + 3rd positions. Phase resistance and current density performance were compared for every combination.

The best result was obtained with two 0.30 mm diameter vias at the 1st position, yielding a minimum phase resistance of 0.0878 Ω. Relative to the baseline model (inner and outer vias both 0.30 mm, phase resistance 0.1057 Ω), this represents a 16.96% reduction. The peak current density at the inner via also decreased from 410 A/mm² to 212 A/mm², a 48.29% reduction. Adding vias at the 2nd and 3rd positions, thereby increasing the via count, often raised phase resistance. Excessive vias reduce the effective conductor area and distribute current inefficiently, which degrades electrical performance. In the GM-via layout, horizontally paired vias further increase copper area loss and conductor interference as diameter grows, raising resistance.

Figure 14 shows the lowest phase resistance value for each combination obtained from FEM simulations over the 0.30–0.40 mm diameter range at the 1st, 2nd, and 3rd stages. Overall, the GM-via scheme achieves lower resistance than the IM-via approach, and the simplest configuration (two 0.30 mm vias at the 1st position) proves most effective. This option is also the easiest to manufacture and confirms that adding more vias does not necessarily improve performance.

Figure 15 builds on Figure 14, in which the inner via uses the GM-via scheme, and the configuration with two 0.30 mm vias at the 1st position proves optimal. With that condition fixed, the present stage applies the IM-via structure to the outer via to evaluate additional phase resistance and current density characteristics. The arrangement is the same as before, except that the outer vias are stacked inward from the stator edge in the order 1st → 2nd → 3rd. For each position, the via diameter is varied stepwise from 0.30 mm to 0.70 mm, and the resulting performance differences attributable to current spreading are quantified.

The lowest phase resistance is obtained with a 0.70 mm via at the 1st position and a 0.30 mm via at the 2nd position, indicating that a large-diameter via at the outermost location secures the main current path, while smaller vias in subsequent positions provide auxiliary current dispersion. Adding a 3rd via yields no significant additional reduction, offering limited benefit compared with the added design complexity.

Figure 15 plots the minimum phase resistance value for every position–diameter combination obtained from the FEM simulations, confirming that strategic selection of via positions and diameters, rather than merely increasing the via count, is decisive for improving electrical performance.

Figure 16 summarizes the FEM results for all GM-via combinations at the 1st, 2nd, and 3rd positions, graphing the lowest phase resistance value obtained in each set. For the inner via, the GM-via arrangement identified in Figure 14—two 0.30 mm vias at the 1st position—gives the best electrical performance, yielding a phase resistance of 0.0878 Ω and a peak current density of 212 A/mm². With this inner via condition fixed, the same GM-via scheme is applied to the outer via, and the resulting phase resistance and current-density characteristics are evaluated.

For the outer GM-via, two side-by-side vias are placed at each position (1st, 2nd, and 3rd) with diameters swept from 0.30 mm to 0.40 mm, resulting in two, four, and six total vias for the 1st, 1st + 2nd, and 1st + 2nd + 3rd stages, respectively. FEM analysis shows that a 0.40 mm via at the 1st position combined with a 0.30 mm via at the 2nd position (1st 0.4, 2nd 0.3) provides the best performance, with a phase resistance of 0.0837 Ω and a peak current density of 290 A/mm². Relative to the optimal inner GM-via case with a single 0.30 mm outer via (phase resistance 0.0878 Ω), this configuration lowers phase resistance by 4.67%. Compared with the baseline single-via design (inner and outer vias both 0.30 mm, peak outer via current density 422 A/mm²), the peak current density decreases by 31.28%. Even against the optimal IM-via outer arrangement (1st 0.7 mm, 2nd 0.3 mm; phase resistance 0.0843 Ω, current density 310 A/mm²), the GM-via layout achieves lower phase resistance and current density. Overall, it reduces phase resistance by 20.76% relative to the single-via baseline.

These results confirm that the GM-via approach provides a more efficient current-distribution path for outer via design. Applying GM vias strategically to both inner and outer locations yields the greatest performance improvement over the single-via and IM-via schemes, demonstrating that precise selection of via position and diameter, rather than simply increasing via count or size, is essential for optimal PCB stator design.

According to the three-dimensional finite-element results in

Table 3. Comparison of 3D finite-element analysis (FEA) results between the conventional and improvement through FEM approach model.

Parameter	Unit	Conventional Model	Improvement Through FEM Approach Model	Change
Back EMF	Vrms	3.2	3.23	-
Load Torque	Nm	0.3	0.3	-
Current	Arms	12.57	12.57	-
Current density	A/mm2	42.19	33.45	20.7%
Phase Resistance	Ohm	0.106	0.083	21.7%
Copper Loss	W	50.08	39.70	20.7%
AC Loss	W	7.11	7.11	-
Output Power	W	114.67	114.67	-
Efficiency	%	66.72	71.01	6.4%

, the grid multi-via (GM-via) design evaluated under the same operating conditions as the baseline single-via model (identical back-EMF, rated speed of 3650 rpm, load torque of 0.3 Nm, line current of 12.57 A rms, and output power of 114.67 W) reduces the peak current density from 42.19 A·mm⁻² to 33.45 A·mm⁻² (≈20.7%) and lowers the phase resistance from 0.106 Ω to 0.083 Ω (≈21.7%). This resistance reduction directly decreases I²R losses, with copper loss falling from 50.08 W to 39.70 W (≈20.7%), which in turn raises overall efficiency from 66.72% to 71.01%, that is, +4.29 percentage points (≈6.4%). These results confirm that the GM-via layout equalizes current paths, mitigates localized current crowding, and effectively increases the usable conductor cross-section under identical mechanical specifications.

In Figure 17, (a) Copper loss, increasing approximately with the square of load current (torque), is ≈20% lower in the GM-via design at rated operation, consistent with the resistance reduction. (b) AC loss, dominated by speed (frequency-dependent effects), shows minor sensitivity to torque and peaks near the highest rpm. (c) Output power, following $P_{out}$-Tω reaches 114.67 W at the rated point, indicating that loss reduction does not compromise deliverable power. (d) Efficiency, reflecting the combined influence of losses and output, exceeds 70% near the rated region, with a maximum of 71.01% compared to 66.72% for the single-via baseline.

5. Conclusions

This study presents an optimal design for a compact axial flux permanent magnet motor (AFPM) that employs an ultra-thin, high-density PCB stator. A multi-via configuration was introduced to reduce phase resistance and peak current density, thereby improving overall electrical performance. Step-by-step FEM analyses were carried out for both inline and grid multi-via schemes to determine the optimal via arrangement. Using the grid multi-via structure, phase resistance decreased from 0.106 Ω to 0.084 Ω (≈20.8%), and peak current density fell from 42.19 A/mm² to 33.45 A/mm² (≈20.7%) relative to the single-via baseline. Copper loss was reduced from 50.08 W to 39.7 W, while overall efficiency increased from 66.72% to 71.01%, with output power and other operating conditions held constant. These results demonstrate that carefully selecting via position and diameter, rather than simply increasing the via count, provides the best balance between design complexity and electrical performance. Unlike earlier PCB-stator motor studies, which lacked systematic optimization of via structures, this work offers a practical design methodology that simultaneously accounts for via diameter, placement, and the number of parallel layers. Real manufacturing constraints, such as minimum drill diameter and copper clearance limits, are also included, ensuring both practicality and reproducibility.