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Review

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

Department of Materials Science and Engineering, University of Seoul, 163 Seoulsiripdae-ro, Dongdaemun-gu, Seoul 02504, Korea
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Author to whom correspondence should be addressed.
Academic Editor: Bálint Medgyes
Metals 2021, 11(10), 1664; https://doi.org/10.3390/met11101664
Received: 31 August 2021 / Revised: 12 October 2021 / Accepted: 13 October 2021 / Published: 19 October 2021
(This article belongs to the Special Issue Reliability Aspects of Lead-Free Solder Alloys Used in Electronics)
With the continuous miniaturization of electronic devices and the upcoming new technologies such as Artificial Intelligence (AI), Internet of Things (IoT), fifth-generation cellular networks (5G), etc., the electronics industry is achieving high-speed, high-performance, and high-density electronic packaging. Three-dimensional (3D) Si-chip stacking using through-Si-via (TSV) and solder bumping processes are the key interconnection technologies that satisfy the former requirements and receive the most attention from the electronic industries. This review mainly includes two directions to get a precise understanding, such as the TSV filling and solder bumping, and explores their reliability aspects. TSV filling addresses the DRIE (deep reactive ion etching) process, including the coating of functional layers on the TSV wall such as an insulating layer, adhesion layer, and seed layer, and TSV filling with molten solder. Solder bumping processes such as electroplating, solder ball bumping, paste printing, and solder injection on a Cu pillar are discussed. In the reliability part for TSV and solder bumping, the fabrication defects, internal stresses, intermetallic compounds, and shear strength are reviewed. These studies aimed to achieve a robust 3D integration technology effectively for future high-density electronics packaging. View Full-Text
Keywords: through-Si-via (TSV); solder bump; 3-dimensional integration; reliability through-Si-via (TSV); solder bump; 3-dimensional integration; reliability
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MDPI and ACS Style

Cho, D.H.; Seo, S.M.; Kim, J.B.; Rajendran, S.H.; Jung, J.P. A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process. Metals 2021, 11, 1664. https://doi.org/10.3390/met11101664

AMA Style

Cho DH, Seo SM, Kim JB, Rajendran SH, Jung JP. A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process. Metals. 2021; 11(10):1664. https://doi.org/10.3390/met11101664

Chicago/Turabian Style

Cho, Do Hoon, Seong Min Seo, Jang Baeg Kim, Sri Harini Rajendran, and Jae Pil Jung. 2021. "A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process" Metals 11, no. 10: 1664. https://doi.org/10.3390/met11101664

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