#### 2.1. Operating Principle

In general, the SC DC–DC converter consists of capacitors and switches, which are driven by two non-overlapping clock signals. The clock signals are set as close as 50% duty cycle with a minimal dead-time (n-channel metal-oxide semiconductor (NMOS) and p-channel metal-oxide semiconductor (PMOS) switches are never closed at the same time to prevent the shoot-through current loss) for the maximum efficiency and the maximum charge transfer to the load.

Figure 1a, b shows the conventional 2-to-1 topology and its low-swing gate-driving signals, respectively. The signals are generated from the level-shifters followed by the non-overlapping clock generators, which will be shown later in Figure 5 in

Section 3 to minimize the switching loss. To present the loss due to bottom-plate parasitic capacitors, a bottom-plate parasitic capacitor is modeled as α

C_{fly}, where

C_{fly} is the actual capacitance of a flying capacitor and is the process and layout-dependent parameter. For convenience,

Figure 1a can be symbolized as the one shown in

Figure 1c, which has two input terminals and one output terminal. Assuming that (1) all MOS switches have the same on-resistance of

R_{on}; (2) the time durations of phase1 and phase2 are the same with the minimal dead time; and (3) the time constant (

R_{L} + 2

R_{on})

C_{fly} is much larger than

1/(2

f_{sw}), the average load voltage (

V_{L}) in

Figure 1a,c, is defined as the average voltage between two input voltages (=(

V_{IN} + 0 V)/2 =

V_{IN}/2) minus Δ

V_{L}, since the average voltage across the flying capacitor (

C_{fly}) is constant at

V_{IN}/2 in steady-state. Δ

V_{L} results from the conduction loss and can be given by:

As shown in Equation (1), if the MOS switches have zero on-resistance, ΔV_{L} becomes zero; therefore, no conduction loss exists, and the average load voltage (V_{L}) will be the same as the no-load voltage (V_{NL} = V_{IN}/2).

In a similar way, the proposed 4-to-3 topology is created in a combination of two 2-to-1 topologies as shown in

Figure 1d; one input terminal of the

2-to-1_up block is fed directly from the input voltage source (

V_{IN}), and the other input terminal is fed out of the output (

V_{L_dw}) of the

2-to-1_dw block. Therefore, the generated load voltage

V_{L_up} (=(

V_{IN} + V_{L_dw})/2 − Δ

V_{L_up}) is the average value of

V_{IN} and

V_{L_dw} (=

1/2

V_{IN} − Δ

V_{L_dw}) minus Δ

V_{L_up}. Δ

V_{L_up} and Δ

V_{L_dw} represent the voltage difference between the delivered load voltages when there is load and there is no load. Again, Δ

V_{L_up} and Δ

V_{L_dw} arise from the conduction loss, and they limit the maximum attainable efficiency to η

_{lin} = V_{L_dw}/(1/2

V_{IN}) for

2-to-1_dw and η

_{lin} = V_{L_up}/{(

V_{IN} + V_{L_dw})/2} for

2-to-1_up.

Figure 2a shows the transistor level implementations of the

2-to-1_dw(

up) blocks, and

Figure 2a shows the gate-driving signals. Since the gate-oxide breakdown voltage of 5 V CMOS transistors in 0.35 μm BCDMOS technology is 5.5 V, all switches can withstand any voltage levels between ground (0 V) and input (5 V). All the gate driving signals in

Figure 2b are generated from the level shifters and the non-overlapping clock generators to minimize the switching loss and shoot-through current loss, which will be shown in Figure 5 in

Section 3. The NMOS transistors (Mn1, Mn3, and Mn4) in

Figure 2a are implemented by means of a triple-well device to isolate the body voltage from the substrate (or bulk).

#### 2.2. Charge Transfer and Loss Mechanisms

The 2-way interleaved structure of the proposed SC DC–DC converter shown in

Figure 3a is used for simplicity of the analysis. For the gate driving signals, ϕ1

a (ϕ1

b) and ϕ2

a (ϕ2

b) are 180° out of phase signals, while ϕ1

a (ϕ2

b) and ϕ1

b (ϕ2

b) represent non-overlapping clock signals, which are shown in

Figure 2b.

Figure 3b represents the equivalent circuit during every half period (phase1 and phase2) of the switching frequency. Assuming that the SC DC–DC converter delivers charge to the loads at average voltages of

V_{L_up} (or

V_{L}) and

V_{L_dw}, the charge extracted from the input voltage source (

Q_{EXT}_{(VIN)}) during every half period of the switching frequency (when the MOS transistors which have the gate-driving signals of ϕ1

a (ϕ1

b) and ϕ2

b (ϕ2

a) are on) can be derived as:

Since the total charge delivered to the load (

V_{L_up}) is the sum of the charge transferred from both top flying capacitors (

C_{up}/2) as shown in

Figure 3b, the total charge transferred to the load is given by:

Considering only the charge transfer, the efficiency can be defined as the ratio of the total charge delivered to the load shown in Equation (3) to the charge extracted from the input voltage source shown in Equation (2). The relationship between ΔV_{L_up} and ΔV_{L_dw} is determined by the ratio between C_{up} and C_{dw}, which will be derived in Equation (6). By solving Equations (2) and (6) together, the efficiency of the proposed 4-to-3 step-down SC DC–DC converter is given by V_{L_up}/(3/4V_{IN} (=V_{NL})). It shows the upper limit of the efficiency of any kind of SC DC–DC converters; in other words, the maximum attainable efficiency decreases as the voltage drop between the no-load voltage (V_{NL}) and the average load voltage (V_{L_up}) increases.

In order to determine the minimum required capacitances for each flying capacitor that satisfy the design requirements (

I_{L}_{(MAX)} = 10 mA and

V_{L_up} = 3.2 V @

ƒ_{sw}_{(MAX)} = 13 MHz), the load current driving capability of the proposed SC DC–DC converter has to be derived in terms of

C_{fly}, Δ

V_{L}, and

ƒ_{sw}_{(MAX)}. From Equations (2) and (3), and

Figure 3b, the load current driving capability at a fixed switching frequency (

ƒ_{sw}) and Δ

V_{L} (=Δ

V_{L_up} + 1/2Δ

V_{L_dw} since Δ

V_{L} =

V_{NL} −

V_{L_up}, where

V_{NL} = 3/4

V_{IN} and

V_{L_up} = (

V_{IN} +

V_{L_dw})/2 − Δ

V_{L_up}) is given by:

From Equations (4) and (5), the relationship between Δ

V_{L_up} and Δ

V_{L_dw} is determined by the ratio between

C_{up} and

C_{dw}, which is given by:

There is an optimal ratio between

C_{up} and

C_{dw}, which yields the maximum load current (

I_{L}) at a constant Δ

V_{L_dw},

ƒ_{sw}, and

C_{fly}. Since

V_{L_up} is the summation of Δ

V_{L_up} and 1/2Δ

V_{L_dw}, Δ

V_{L_up} can be express in terms of Δ

V_{L_dw},

C_{up} (=

C_{fly} −

C_{dw}), and

C_{dw} using Equation (6) as:

From Equations (4) and (7), the load current (

I_{L}) is given by:

By taking the partial derivative of Equation (8) with respect to

C_{dw} and putting it to zero, the maximum load current (

I_{L}_{(MAX)}) is obtained when

C_{fly} is three times that of

C_{dw}. Therefore, the optimal ratio between

C_{up} and

C_{dw}, which yields the maximum load current (

I_{L}) at a constant Δ

V_{L},

ƒ_{sw}, and

C_{fly} (=

C_{up} +

C_{dw}), is given by

C_{up} = 2

C_{dw}. Therefore, Equation (8) can be rewritten as:

where

${C}_{fly}={C}_{up}+{C}_{dw}$,

${C}_{up}=2{C}_{dw}$.

From Equation (6), if C_{up} is twice the value of C_{dw}, ΔV_{L_up} is equal to ΔV_{L_dw}. Since our target load voltage is 3.2 V, ΔV_{L} is determined to be 0.55 V (ΔV_{L} = ΔV_{NL} − V_{L_up}). Therefore, both ΔV_{L_up} and ΔV_{L_dw} are determined to be about 0.367 V, since ΔV_{L} is equal to the summation of ΔV_{L_up} and 1/2 ΔV_{L_dw}. For the given specifications, (1) ΔV_{L_up} (=ΔV_{L_dw}) is 0.367 V; (2) the maximum load current (I_{L}_{(MAX)}) is 10 mA; and (3) the maximum switching frequency (ƒ_{sw}) of the voltage controlled oscillator (VCO) is about 13 MHz, and the minimum required C_{up} can be estimated as about 455 pF. Considering process–voltage–temperature (PVT) variations, the C_{up} of 600 pF and C_{dw} of 300 pF are chosen. The MOS switches are sized with small margins to guarantee that the converter is able to deliver a 10 mA load current to the 3.2 V load.

As can be observed from Equation (9), with the fixed values of ΔV_{L} and C_{up} (C_{dw}), the load current (I_{L}) can be controlled by changing switching frequency (ƒ_{sw}). Therefore, with a change in load current, the output load voltage can be regulated by means of pulse frequency modulation (PFM). In this design, the PFM control scheme is used with the compensated two-stage operational transconductance amplifier (OTA) and the current-starved voltage controlled oscillator (VCO) as shown in Figure 5, which are designed to be operating in the range of 0.44 MHz to 15 MHz. Therefore, switching and bottom-plate capacitance loss are the maximum at the heaviest load condition (I_{L} = 10 mA at V_{L_up} = 3.2 V) and scale down linearly with the decreasing load by means of PFM technique.

Besides the conduction loss, the loss due to the bottom-plate parasitic capacitors is significant, especially when on-chip capacitors are used as flying capacitors. Since MOS capacitors (2.7 fF/μm

^{2}) have higher capacitance density than MIM capacitors (1 fF/μm

^{2}) in BCDMOS 0.35 μm technology, only MOS capacitors are used as the flying and load capacitors. In this case, the bottom-plate capacitance ratio (α) is assumed to be 6.5% of an actual capacitance. As shown in

Figure 3b, during every half period of the switching frequency, each top bottom-plate capacitor α

C_{up}/2 (α

C_{dw}/2) in

2-to-1_up(

dw) is charged to

V_{L_up} (

V_{L_dw}), while each bottom bottom-plate capacitor α

C_{up}/2 (α

C_{dw}/2) is discharged to

V_{L_dw} (0 V). While the charged electrons in the bottom-plate capacitors of the

2-to-1_dw block are discharged to ground, the charged electrons in the bottom-plate capacitors of

2-to-1_up block are discharged to the load

V_{L_dw}. As a result, the energy lost per cycle due to those bottom-plate capacitors can be given by:

Assuming the bottom-plate capacitance ratio (α) is 0%, Equation (9) can be used to verify the previous analysis.To determine the optimum ratio between

C_{up} and

C_{dw} with non-zero,

C_{up} is swept from 450 pF to 700 pF at a different bottom-plate capacitance ratio (α).

C_{up} is altered from 0% to 10% while the total flying capacitance

C_{fly} is maintained at 900 pF. As shown in

Figure 4a, the maximum efficiency of 78.5% is obtained when

C_{up} is 550 pF and α is 0%. According to Equation (9), the maximum load is supposed to be obtained when

C_{up} is twice the value of

C_{dw}; that is,

C_{up} = 600 pF. The discrepancy can be explained from the neglected control current (

I_{ctrl}) in Equation (5). However, as α increases from 0% to 10%, the maximum efficiency points in

Figure 4a moves to the right hand side of the x-axis while the overall efficiency decreases linearly, which can be explained with Equation (10). However, as shown in

Figure 3b, since the voltage swing (

V_{L_up} −

V_{L_dw}) at the top bottom-plate capacitors (

C_{up}/2) is always smaller than the voltage swing (

V_{L_dw}) at the bottom bottom-plate capacitors (

C_{dw}/2) for the range of

C_{up} between 450 pF and 700 pF, the energy loss due to the bottom-plate capacitor is reduced as

C_{up} increases. As the maximum efficiency of 73.5% is obtained when

C_{up} is 600 pF and is 6.5% from

Figure 4a,

C_{u}_{p} and

C_{dw} are selected to be 600 pF and 300 pF, respectively, for the implementation.

Figure 4b shows the efficiency drop of the proposed 4-to-3 topology and the conventional 3-to-2 topology [

1] with respect to increasing α. In both cases, load voltages are regulated at ~85% of the no-load voltages (3.75 V for 4-to-3 topology and 3.33 V for 3-to-2 topology), while delivering a 10 mA load current using the same amount of flying and load capacitors, the same control scheme, and the same bias circuits for the implementation of both SC DC–DC converters. As shown in

Figure 4b, with an increasing bottom-plate capacitance ratio (α) from 0% to 10% of the flying capacitors, the efficiency drop of the proposed 4-to-3 topology is less than 8%, which is 2.25 times less than that of the conventional 3-to-2 topology.