# Fully Integrated on-Chip Switched DC–DC Converter for Battery-Powered Mixed-Signal SoCs

^{1}

^{2}

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## Abstract

**:**

_{L_dw}) from the 2-to-1_dw, and low swing level-shifted gate-driving signals are generated using the internal load voltage (V

_{L_dw}). Therefore, the proposed implementation reduces control circuit and switching power consumptions. The programmable power supply voltage is regulated by means of a pulse frequency modulation (PFM) technique with the compensated two-stage operational transconductance amplifier (OTA) and the current-starved voltage controlled oscillator (VCO) to maintain high efficiency over a wide range of load currents. The proposed on-chip SC DC–DC converter is designed and simulated using high-voltage 0.35 μm bipolar, complementary metal-oxide-semiconductor (CMOS) and DMOS (BCDMOS) technology. It achieves a peak efficiency of 74% when delivering an 8 mA load current at a 3.2 V supply voltage level, and it provides a maximum output power of 48 mW (I

_{L}= 15 mA at V

_{L_up}= 3.2 V) at 70.5% efficiency. The proposed on-chip SC voltage regulator shows better efficiency than the ideal linear regulator over a wide range of output power, from 2.6 mW to 48 mW. The 18-phase interleaving technique enables the worst-case output voltage ripple to be less than 5.77% of the load voltage.

## 1. Introduction

_{ox}) of MOS capacitors has been increasing with continuous technology scaling. For example, the C

_{ox}for 1 μm technology (t

_{ox}= 20 nm) is 1.75 fF/μm

^{2}, while the C

_{ox}for 50 nm technology (t

_{ox}= 1.4 nm) is 25 fF/μm

^{2}[6].

## 2. Core Design

#### 2.1. Operating Principle

_{fly}, where C

_{fly}is the actual capacitance of a flying capacitor and is the process and layout-dependent parameter. For convenience, Figure 1a can be symbolized as the one shown in Figure 1c, which has two input terminals and one output terminal. Assuming that (1) all MOS switches have the same on-resistance of R

_{on}; (2) the time durations of phase1 and phase2 are the same with the minimal dead time; and (3) the time constant (R

_{L}+ 2R

_{on})C

_{fly}is much larger than 1/(2f

_{sw}), the average load voltage (V

_{L}) in Figure 1a,c, is defined as the average voltage between two input voltages (=(V

_{IN}+ 0 V)/2 = V

_{IN}/2) minus ΔV

_{L}, since the average voltage across the flying capacitor (C

_{fly}) is constant at V

_{IN}/2 in steady-state. ΔV

_{L}results from the conduction loss and can be given by:

_{L}becomes zero; therefore, no conduction loss exists, and the average load voltage (V

_{L}) will be the same as the no-load voltage (V

_{NL}= V

_{IN}/2).

_{IN}), and the other input terminal is fed out of the output (V

_{L_dw}) of the 2-to-1_dw block. Therefore, the generated load voltage V

_{L_up}(=(V

_{IN}+ V

_{L_dw})/2 − ΔV

_{L_up}) is the average value of V

_{IN}and V

_{L_dw}(=1/2V

_{IN}− ΔV

_{L_dw}) minus ΔV

_{L_up}. ΔV

_{L_up}and ΔV

_{L_dw}represent the voltage difference between the delivered load voltages when there is load and there is no load. Again, ΔV

_{L_up}and ΔV

_{L_dw}arise from the conduction loss, and they limit the maximum attainable efficiency to η

_{lin}= V

_{L_dw}/(1/2V

_{IN}) for 2-to-1_dw and η

_{lin}= V

_{L_up}/{(V

_{IN}+ V

_{L_dw})/2} for 2-to-1_up.

#### 2.2. Charge Transfer and Loss Mechanisms

_{L_up}(or V

_{L}) and V

_{L_dw}, the charge extracted from the input voltage source (Q

_{EXT}

_{(VIN)}) during every half period of the switching frequency (when the MOS transistors which have the gate-driving signals of ϕ1a (ϕ1b) and ϕ2b (ϕ2a) are on) can be derived as:

_{L_up}) is the sum of the charge transferred from both top flying capacitors (C

_{up}/2) as shown in Figure 3b, the total charge transferred to the load is given by:

_{L_up}and ΔV

_{L_dw}is determined by the ratio between C

_{up}and C

_{dw}, which will be derived in Equation (6). By solving Equations (2) and (6) together, the efficiency of the proposed 4-to-3 step-down SC DC–DC converter is given by V

_{L_up}/(3/4V

_{IN}(=V

_{NL})). It shows the upper limit of the efficiency of any kind of SC DC–DC converters; in other words, the maximum attainable efficiency decreases as the voltage drop between the no-load voltage (V

_{NL}) and the average load voltage (V

_{L_up}) increases.

_{L}

_{(MAX)}= 10 mA and V

_{L_up}= 3.2 V @ƒ

_{sw}

_{(MAX)}= 13 MHz), the load current driving capability of the proposed SC DC–DC converter has to be derived in terms of C

_{fly}, ΔV

_{L}, and ƒ

_{sw}

_{(MAX)}. From Equations (2) and (3), and Figure 3b, the load current driving capability at a fixed switching frequency (ƒ

_{sw}) and ΔV

_{L}(=ΔV

_{L_up}+ 1/2ΔV

_{L_dw}since ΔV

_{L}= V

_{NL}− V

_{L_up}, where V

_{NL}= 3/4V

_{IN}and V

_{L_up}= (V

_{IN}+ V

_{L_dw})/2 − ΔV

_{L_up}) is given by:

_{L_up}and ΔV

_{L_dw}is determined by the ratio between C

_{up}and C

_{dw}, which is given by:

_{up}and C

_{dw}, which yields the maximum load current (I

_{L}) at a constant ΔV

_{L_dw}, ƒ

_{sw}, and C

_{fly}. Since V

_{L_up}is the summation of ΔV

_{L_up}and 1/2ΔV

_{L_dw}, ΔV

_{L_up}can be express in terms of ΔV

_{L_dw}, C

_{up}(=C

_{fly}− C

_{dw}), and C

_{dw}using Equation (6) as:

_{L}) is given by:

_{dw}and putting it to zero, the maximum load current (I

_{L}

_{(MAX)}) is obtained when C

_{fly}is three times that of C

_{dw}. Therefore, the optimal ratio between C

_{up}and C

_{dw}, which yields the maximum load current (I

_{L}) at a constant ΔV

_{L}, ƒ

_{sw}, and C

_{fly}(=C

_{up}+ C

_{dw}), is given by C

_{up}= 2C

_{dw}. Therefore, Equation (8) can be rewritten as:

_{up}is twice the value of C

_{dw}, ΔV

_{L_up}is equal to ΔV

_{L_dw}. Since our target load voltage is 3.2 V, ΔV

_{L}is determined to be 0.55 V (ΔV

_{L}= ΔV

_{NL}− V

_{L_up}). Therefore, both ΔV

_{L_up}and ΔV

_{L_dw}are determined to be about 0.367 V, since ΔV

_{L}is equal to the summation of ΔV

_{L_up}and 1/2 ΔV

_{L_dw}. For the given specifications, (1) ΔV

_{L_up}(=ΔV

_{L_dw}) is 0.367 V; (2) the maximum load current (I

_{L}

_{(MAX)}) is 10 mA; and (3) the maximum switching frequency (ƒ

_{sw}) of the voltage controlled oscillator (VCO) is about 13 MHz, and the minimum required C

_{up}can be estimated as about 455 pF. Considering process–voltage–temperature (PVT) variations, the C

_{up}of 600 pF and C

_{dw}of 300 pF are chosen. The MOS switches are sized with small margins to guarantee that the converter is able to deliver a 10 mA load current to the 3.2 V load.

_{L}and C

_{up}(C

_{dw}), the load current (I

_{L}) can be controlled by changing switching frequency (ƒ

_{sw}). Therefore, with a change in load current, the output load voltage can be regulated by means of pulse frequency modulation (PFM). In this design, the PFM control scheme is used with the compensated two-stage operational transconductance amplifier (OTA) and the current-starved voltage controlled oscillator (VCO) as shown in Figure 5, which are designed to be operating in the range of 0.44 MHz to 15 MHz. Therefore, switching and bottom-plate capacitance loss are the maximum at the heaviest load condition (I

_{L}= 10 mA at V

_{L_up}= 3.2 V) and scale down linearly with the decreasing load by means of PFM technique.

^{2}) have higher capacitance density than MIM capacitors (1 fF/μm

^{2}) in BCDMOS 0.35 μm technology, only MOS capacitors are used as the flying and load capacitors. In this case, the bottom-plate capacitance ratio (α) is assumed to be 6.5% of an actual capacitance. As shown in Figure 3b, during every half period of the switching frequency, each top bottom-plate capacitor αC

_{up}/2 (αC

_{dw}/2) in 2-to-1_up(dw) is charged to V

_{L_up}(V

_{L_dw}), while each bottom bottom-plate capacitor αC

_{up}/2 (αC

_{dw}/2) is discharged to V

_{L_dw}(0 V). While the charged electrons in the bottom-plate capacitors of the 2-to-1_dw block are discharged to ground, the charged electrons in the bottom-plate capacitors of 2-to-1_up block are discharged to the load V

_{L_dw}. As a result, the energy lost per cycle due to those bottom-plate capacitors can be given by:

_{up}and C

_{dw}with non-zero, C

_{up}is swept from 450 pF to 700 pF at a different bottom-plate capacitance ratio (α). C

_{up}is altered from 0% to 10% while the total flying capacitance C

_{fly}is maintained at 900 pF. As shown in Figure 4a, the maximum efficiency of 78.5% is obtained when C

_{up}is 550 pF and α is 0%. According to Equation (9), the maximum load is supposed to be obtained when C

_{up}is twice the value of C

_{dw}; that is, C

_{up}= 600 pF. The discrepancy can be explained from the neglected control current (I

_{ctrl}) in Equation (5). However, as α increases from 0% to 10%, the maximum efficiency points in Figure 4a moves to the right hand side of the x-axis while the overall efficiency decreases linearly, which can be explained with Equation (10). However, as shown in Figure 3b, since the voltage swing (V

_{L_up}− V

_{L_dw}) at the top bottom-plate capacitors (C

_{up}/2) is always smaller than the voltage swing (V

_{L_dw}) at the bottom bottom-plate capacitors (C

_{dw}/2) for the range of C

_{up}between 450 pF and 700 pF, the energy loss due to the bottom-plate capacitor is reduced as C

_{up}increases. As the maximum efficiency of 73.5% is obtained when C

_{up}is 600 pF and is 6.5% from Figure 4a, C

_{u}

_{p}and C

_{dw}are selected to be 600 pF and 300 pF, respectively, for the implementation.

## 3. Architecture

_{REF1}and V

_{REF2}) from a modified single bandgap voltage reference, which is based on Reference [7]. Once the internal load voltage (V

_{L_dw}) is charged up to about 1.8 V by start-up circuit, the power supply voltage of the control circuits (V

_{CTRL}) is regulated at 1.6 V by NMOS pass transistor-based low-drop out (LDO) voltage regulator connected to the internal load voltage (V

_{L_dw}), which is the output voltage of the 2-to-1_dw. Therefore, the reduction of control loss is achieved by decreasing the dynamic power consumption in the current-starved VCO and 18 non-overlapping clock generators. In addition, the internal load voltage (V

_{L_dw}) is used to generate low swing level-shifted gate-driving signals to reduce switching loss.

_{x}(t)), which is set by a 3-bit resistor divider network, becomes less than V

_{REF1}, the output voltage (V

_{VCO}(t)) of the error-amplifier increases, and vice versa; thus, the oscillation frequency of the current-starved ring oscillator increases or decreases until V

_{x}(t) is equal to V

_{REF1}. The 18-phase interleaved structure is used to reduce the output ripple voltage. The equally phase-shifted 18-phase interleaved signals are generated from the current-starved ring oscillator and inverters, and they become the low swing gate-driving signals using the non-overlapping clock generators and the level shifters to reduce the gate-drive switching loss.

## 4. Simulation Results

_{L}) between 1 mA and 15 mA at four different output load voltage levels (V

_{L}or V

_{L_up}, henceforth referred to as V

_{L}). The efficiency is also shown for a different bottom-plate capacitance ratio (α) between 0% and 10%. In order to effectively visualize the degrees of the efficiency drop, which increase when the proposed converter is set to support one of four different output load voltage levels (3.2 V, 3 V, 2.8 V, and 2.6 V), the scale of the y-axis is adjusted to show the maximum efficiency change of 20%.

_{sw}) scales with the load power. As the load power decreases, the losses due to the switching loss and the bottom-plate capacitance decrease as well. Therefore, the proposed converter provides higher efficiency over a wide output power range between 2.6 mW and 48 mW than the ideal linear regulator. However, since the static control power does not scale with the switching frequency, the portion of the control power loss becomes dominant as the load power decreases, causing the overall efficiency to decrease. As the regulated load voltage is set to 2.8 V from 3.2 V, the efficiency drop becomes less sensitive to the increase since the voltage swings at the bottom-plate capacitors decrease, as presented in Equation (10), and the conduction loss becomes more dominant than the bottom-plate capacitance loss.

_{L}) changes from 1 mA to 10 mA, and vice versa. The worst-case transient response occurs with the load current transition from 10 mA to 1 mA when the load voltage is regulated at 3.2 V; the recovery time is about 2 μs, while the average response time of the load current variation between 10 mA (1 mA) and 1 mA (10 mA) is less than 1.5 μs. The worst-case peak-to-peak output ripple voltage occurs when the proposed SC DC–DC converter delivers a 1 mA load current to a 2.6 V load voltage as shown in Figure 7d; it is about 150 mV and 5.77% of the load voltage (V

_{L}= 2.6 V) when the output buffer capacitor of 400 pF is added to the load.

_{L}) and the efficiency variations with process–voltage–temperature (PVT) variations when the proposed SC DC–DC converter delivers a 10 mA load current at four different output load voltage levels. For the process variation, device mismatches such as threshold voltage (V

_{to}), current factor (β = μ

_{o}C

_{ox}), and base-to-emitter voltage (V

_{be}

_{(eb)}) variations are considered. In addition to the components’ statistical variation provided by the fabrication vendor, an intentional 20% capacitance variation (at 3-sigma) in flying capacitors are considered. A 3% supply voltage variation at 3-σ at different temperatures is considered as well. In order to extract the average and 1-sigma variations of the output load voltage and the efficiency, 100 transient Monte Carlo (MC) simulations are performed at different temperatures.

_{L}) until the down-scaled load voltage (V

_{X}(t)) in Figure 5 in Section 3 is equal to the reference voltage (V

_{REF1}) from the bandgap voltage reference, V

_{L}can be regarded as the up-scaled reference voltage. Therefore, each average load voltage (V

_{L}) in Figure 8 has a parabolic shape with respect to temperature since the reference voltage from bandgap voltage reference has a parabolic shape with respect to temperature as well. The degree of load voltage and efficiency variations increases rapidly when the proposed converter supplies a 3.2 V load voltage and a 10 mA load current. As the load voltage level (V

_{L}) increases, ΔV

_{L}decreases requiring a higher switching frequency (ƒ

_{sw}) to deliver the same load current (I

_{L}= 10 mA), as explained in Equation (9). In addition, since the maximum frequency generated from the VCO decreases with increasing temperature, when the same voltage of V

_{VCO}(t) is applied to the input of the VCO as shown in Figure 5 in Section 3, the shape of the average load voltage (@V

_{L}= 3.2 V) in Figure 8a shows a slightly different parabolic shape. That is, the peak load voltage occurs at a temperature of 25 °C and the average load voltage decreases faster from that point than the other load voltages in Figure 8b,c. This means that the switching frequency (f

_{sw}) generated from the VCO is reached at its maximum value (f

_{sw}

_{(MAX)}) when the temperature is around 25 °C; therefore, the load voltage drops faster than the other load voltages. The average efficiency drops faster with increasing temperature due to increased conduction loss. The worst-case percent variations occur when the converter delivers a 2.6 V load voltage at 100 °C temperature; the percent variation of the average load voltage is about 0.68%, while the percent variation of the average efficiency is about 2.47% at 1-σ The simulation results confirm that the load regulation and the efficiency of the proposed SC DC–DC converter is robust with PVT variations.

_{L}= 2.6 V) when the proposed SC DC–DC converter delivers a 1 mA load current. A 5.77% worst-case ripple voltage is obtained with the smallest on-chip load capacitor (400 pF) compared to other SC DC–DC converter designs, and it can be further reduced by employing a larger load capacitor at an increasing cost/area. The switching frequency (f

_{sw}) range is from 0.44 to 15 MHz, and the average load voltage range is from 2.6 to 3.2 V.

## 5. Conclusions

_{sw}) range is from 0.44 to 15 MHz, and the average load voltage range is from 2.6 to 3.2 V. The proposed converter achieves a peak efficiency of 74% when it delivers an 8 mA load current at a 3.2 V load voltage. The proposed converter shows better efficiency than the ideal linear regulator over a wide range of output power, from 2.6 to 48 mW. The 18-phase interleaving technique enables the worst-case output voltage ripple to be less than 5.77% of the load voltage.

## Author Contributions

## Conflicts of Interest

## References

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**Figure 1.**(

**a**) Conventional 2-to-1 step-down topology. (

**b**) Level-shifted non-overlapping gate-driving signals for conventional 2-to-1 topology. (

**c**) Simplified block diagram of 2-to-1 topology. (

**d**) Proposed 4-to-3 step-down topology.

**Figure 2.**Transistor level implementation of one-phase of 4-to-3 converter core. (

**a**) 2-to-1_dw (left down) and 2-to-1_up (left up). (

**b**) One of 18 phases of level shifted non-overlapping gate-driving signals.

**Figure 3.**(

**a**) The 2-way interleaved structure for the proposed 4-to-3 step-down topology. (

**b**) Equivalent circuit for Figure 3a.

**Figure 4.**(

**a**) Efficiency variation of the proposed switched-capacitor (SC) DC–DC converter with varying C

_{up}while C

_{fly}=(C

_{up}+ C

_{dw}) is kept constant at 900 pF (where V

_{L_up}= 3.2 V, I

_{L}= 10 mA, and temperature = 25°). (

**b**) Efficiency drop with respect to increasing bottom-plate capacitance ratio (α) (where V

_{L_up}= 3.2 V, I

_{L}= 10 mA, C

_{up}= 600 pF, C

_{dw}= 300 pF, V

_{L_up}= 0.85 × V

_{NL}, and temperature = 25°).

**Figure 5.**Architecture of proposed 18-phase interleaved 4-to-3 step-down switched capacitor DC–DC converter. (

**a**) Start-up circuit. (

**b**) Error-Amp. & VCO. (

**c**) Bandgap reference. (

**d**) Level shifter. (

**e**) Non-overlapping CLK generator.

**Figure 6.**Efficiency comparison between the proposed SC DC–DC converter and the ideal linear regulator with a different load current (I

_{L}) while α is swept from 0% to 10% (temperature = 25°). (

**a**) V

_{L}= 3.2 V. (

**b**) V

_{L}= 3 V. (

**c**) V

_{L}= 2.8 V. (

**d**) V

_{L}= 2.6 V.

**Figure 7.**Transient response of the load voltage (V

_{L}) [V] with varying load current (I

_{L}) (1 to 10 mA and vice versa) (temperature = 25°). (

**a**) V

_{L}= 3.2 V. (

**b**) V

_{L}= 3 V. (

**c**) V

_{L}= 2.8 V. (

**d**) V

_{L}= 2.6 V.

**Figure 8.**Average and 1-sigma variation of the load voltage (V

_{L}) [V] and the efficiency [%] with process–voltage–temperature (PVT) variations. (

**a**) V

_{L}= 3.2 V, I

_{L}= 10 mA. (

**b**) V

_{L}= 3 V, I

_{L}= 10 mA. (

**c**) V

_{L}= 2.8 V, I

_{L}= 10 mA. (

**d**) V

_{L}= 2.6 V, I

_{L}= 10 mA.

Reference | Technology | V_{IN} | V_{L} | C_{fly} | C_{L} | f_{sw} | % Ripple | η_{MAX} | P_{MAX} | I_{L(MAX)} |
---|---|---|---|---|---|---|---|---|---|---|

This Work | 0.35 μm BCDMOS | 5 V | 2.6~3.2 V | 900 pF (on-chip) MOS-cap | 400 pF (on-chip) MOS-cap | 0.44~15 MHz | <5.77% @V _{L} = 2.6 VI _{L} = 1 mA | 74% @V _{L} = 3.2 VI _{L} = 8 mA | 48 mW | 15 mA @V _{L} = 3.2 V |

[1] | 45 nm | 1.8 V | 0.8~1 V | 534 pF (on-chip) MOS-cap | 700 pF (on-chip) MOS-cap | 30 MHz | <6.25% | 69% | 7.2 mW | 8 mA @V _{L} = 0.9V |

[5] | 0.35 µm | 2.5 V | 0.9~1.5 V | 6.72 nF (on-chip) PIP-cap + 3-D cap | 470 nF (off-chip) | 0.2~1 MHz | 1.33% @I _{L} = 5 mA | 66.7% | 7.5 mW | 5 mA @V _{L} = 1.5 V |

[8] | 0.35 µm | 5 V | 0.885 V | 1.2 nF (on-chip) | 10 nF (off-chip) | 15 MHz | 3.96% @I _{L} = 8.85 mA | 62% | 7.83 mW | 8.85 mA |

[9] | 0.35 µm | 3.4~5 V | 3.3 V | 1 µF (off-chip) | 1 µF (off-chip) | 100 kHz | 1.21% @I _{L} = 7.5 mA | 65% | 40.59 mW | 12.3 mA |

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## Share and Cite

**MDPI and ACS Style**

Jeon, H.; Kim, K.K.; Kim, Y.-B.
Fully Integrated on-Chip Switched DC–DC Converter for Battery-Powered Mixed-Signal SoCs. *Symmetry* **2017**, *9*, 18.
https://doi.org/10.3390/sym9010018

**AMA Style**

Jeon H, Kim KK, Kim Y-B.
Fully Integrated on-Chip Switched DC–DC Converter for Battery-Powered Mixed-Signal SoCs. *Symmetry*. 2017; 9(1):18.
https://doi.org/10.3390/sym9010018

**Chicago/Turabian Style**

Jeon, Heungjun, Kyung Ki Kim, and Yong-Bin Kim.
2017. "Fully Integrated on-Chip Switched DC–DC Converter for Battery-Powered Mixed-Signal SoCs" *Symmetry* 9, no. 1: 18.
https://doi.org/10.3390/sym9010018