Design and Analysis of Hardware Acceleration for Semi-Physical Simulation of Ground-Based Drag-Free Control

Abstract

To meet the in-orbit performance verification requirements of a drag-free control system for gravitational wave detection satellites, this study develops a ground simulation platform using the H-infinity ($H_{\infty }$) control method in Simulink. The FPGA implementation accelerates the core algorithm of drag-free control. A frequency-domain linear robust control design is employed, with a frequency pre-warped bilinear transformation method used to discretize the multi-degree-of-freedom controller. The established control system model includes 18 degrees of freedom, with 12 from the dual test masses (TM) and 6 from the satellite body. The two test masses are spatially arranged in a symmetric configuration, and their control structure also exhibits symmetry. A rapid reconfigurable hardware architecture is utilized, and the Vitis Model Composer tool is employed to efficiently translate the Simulink algorithm model into hardware description language, reducing the processing delay of the core control algorithm to the nanosecond level. Through a 15-channel gradient test comparison, the FPGA platform maintains numerical equivalence with the Simulink platform (maximum error of ${10}^{-13}$). Experimental results show that the hardware acceleration improves dynamic response speed by an order of magnitude, achieving position control accuracy of ±5 μm and attitude accuracy of ±10 μrad, with overall processing latency at the microsecond level. This method provides a reliable engineering validation approach for ultra-precision control systems in gravitational wave detection.

1. Introduction

Gravity is a fundamental force of interaction between matter, and the detection of gravitational waves overcomes the limitations of electromagnetic wave observations, enabling the exploration of large-scale cosmic phenomena and extreme astrophysical events. Space-based gravitational wave detection works by capturing the distance changes induced by gravitational waves and then inversely calculating the related information about the waves [1,2,3,4]. However, gravitational waves are extremely weak, resulting in minuscule changes in distance. For example, the distance variation they induce is less than the diameter of an atom over a length of millions of kilometers.

In 1959, American physicist George Pugh first proposed the drag-free control system [5]. The core idea of drag-free control is for the satellite to actively track the test mass suspended inside, using microthrusters to counteract external disturbances, thereby achieving an “ultra-quiet and ultra-stable” state [6,7,8,9,10]. In 1972, the United States launched the first drag-free control technology verification satellite, TRIAD I, which demonstrated the feasibility of drag-free control satellites [11]. As shown in Figure 1, the diagram illustrates the drag-free control mode. A drag-free control platform typically consists of a satellite body and multiple test masses, which are symmetrically distributed in space. This symmetrical configuration helps balance the system’s mass distribution and inertial properties, thereby simplifying controller design, reducing coupling effects, and enhancing both system stability and the uniformity of response.

Based on the aforementioned research background and in light of the challenges posed by the insufficient in-orbit performance of drag-free control systems in future gravitational wave detection satellite missions, ground simulation testing for verifying the performance of the drag-free control system becomes particularly important. Currently, ground-based simulation platforms include Sun Yat-sen University’s system, which uses the Stewart platform for kinematic and dynamic modeling and the design and construction of a drag-free ground simulation experimental setup. The system has successfully implemented drag-free control with two degrees of freedom. Experimental results show that, except at the inherent frequency point of the suspension system, the controller achieves a precision of less than 8 µm in the X-axis translation direction and less than 0.2 mrad in the Y-axis rotation direction [12]. The European Space Agency (ESA) and the Japan Aerospace Exploration Agency (JAXA) used a high-precision accelerometer (ISA) for the BepiColombo mission, employing a constrained multi-segment orbit determination method to complete the drag-free control ground simulation system for Mercury satellite simulation. Through numerical simulations, they identified a calibration method for the ISA data, effectively compensating for accelerometer errors and ensuring data reliability in the scientific target frequency band (1.2 × ${10}^{-4}$ Hz), achieving simulation accuracy at the nanometer level [13]. In the LISA gravitational wave detection program jointly developed by NASA and the European Space Agency, a constrained decoupled $H_{\infty }$ control architecture was employed to construct a linearized state-space model with 20 degrees of freedom. High-fidelity verification was conducted using a Simscape model, achieving ground-based simulation validation at the sub-nanometer level [14].

However, the aboveground-based simulations are affected by ground vibrations and residual forces from air damping (ranging from ${10}^{-5}$∼${10}^{-6}$ N). Moreover, most air-floating platforms support only three to six degrees of freedom, making it difficult to replicate the complex multi-body coupled dynamics of space environments. To address the above issues, this study proposes a drag-free control hardware–software platform based on the Simulink simulation environment and the $H_{\infty }$ control method. The platform is capable of implementing drag-free control across 18 degrees of freedom, including 6 degrees of freedom for the satellite and 12 for the two test masses. The two test masses are symmetrically arranged with respect to the centers of their respective electrode housings. Their masses are closely matched, with a mismatch controlled within 5∼10%, and their deviations from the ideal positions are in the order of hundreds of micrometers. This symmetric configuration satisfies the system’s symmetry requirements, enabling algorithmic simplification and facilitating the implementation of coupled control. The platform achieves a position control accuracy of ±5 μm and an attitude accuracy of ±10 μrad. To ensure real-time performance, the drag-free control algorithm is deployed on an FPGA for testing, enabling parallel simulation of drag-free control with eighteen or more degrees of freedom. This implementation overcomes key limitations of software-based systems, such as poor parallelism and inadequate timing precision, reducing the overall processing latency to the microsecond level and significantly enhancing the system’s real-time capability.

2. Model Building

With its exceptional ability to achieve ultra-low disturbances, drag-free control technology has advanced rapidly in both theoretical and engineering domains. The Gravity Probe B (GP-B) satellite employed the LQR method to design its test mass suspension control system, with a classical PID controller serving as a backup [15]. LQR assumes a fully known system model; however, drag-free control systems are affected by sensor noise, the nonlinear characteristics of micro-thrusters, and uncertain external disturbances such as solar radiation pressure and gravity gradients. Consequently, LQR exhibits insufficient robustness against these perturbations. The European Space Agency designed the disturbance reduction system (DRS) of the LISA Pathfinder satellite based on the principles of PID control [16]. This approach requires separate tuning of the PID control parameters for 15 control loops, as well as high-order attenuation filters, and it is challenging to effectively utilize frequency-domain information. The Science and Technology on Space Intelligent Control Laboratory proposed an adaptive drag-free control law design based on setpoint identification using adaptive control. By introducing multiple thresholds within a constrained interval, the observed outputs are transformed into setpoint information corresponding to different thresholds, and an identification algorithm for unknown parameters is constructed based on these thresholds and weighted optimization techniques [17]. It allows for an online estimation of system parameters or disturbances, enabling the control of unknown systems. However, for drag-free control systems, high-precision position control requires sub-nanometer residual accelerations. If the parameter convergence is slow, errors may occur during the initial stage or under abrupt disturbances, resulting in suboptimal transient responses.

Given that the closed-loop control metrics of drag-free satellites are defined in the frequency domain, designing controllers in the frequency domain allows for global optimization of performance metrics, thereby efficiently achieving the control accuracy required for mission objectives. Leveraging its central role in robust control, $H_{\infty }$ control theory provides strong robustness and disturbance rejection by minimizing the $H_{\infty }$ norm of the system. The key advantage of this approach is its frequency-domain design framework, which offers explicit physical interpretation and is especially suited to meeting the high-precision control demands of drag-free satellites [18,19,20]. Accordingly, this study presents a Simulink-based implementation of a drag-free control algorithm grounded in $H_{\infty }$ robust control theory, with hardware acceleration achieved via FPGA.

The semi-physical simulation system for drag-free control consists of a high-precision sensing module, a filtering module, a core control algorithm module, and a command execution module. The high-precision sensing module monitors the relative position between the test mass and the spacecraft in real time. This task is primarily handled by the gravitational reference sensor (GRS), which acquires both the position and attitude of the test mass. The collected data are transmitted to the Kalman filtering module, which includes both prediction and update submodules. Based on the system dynamics model, the prediction module estimates the state at the next time step, while the update module balances the weights of prediction and observation to minimize estimation error. The filtered results are then passed to the core drag-free control algorithm module, where control commands are generated and sent to the next stage, as illustrated in Figure 2. This study focuses on the implementation of the drag-free control core algorithm on the Simulink platform and its acceleration using FPGA-based hardware.

The core drag-free control algorithm is designed using a frequency-domain linear robust control approach, with theoretical analysis and implementation based on the $H_{\infty }$ control method. This method synthesizes the magnitude frequency characteristics of the closed-loop sensitivity function S, the complementary sensitivity function T, and the product of the controller transfer function and sensitivity function KS, thereby deriving a controller transfer function K that meets the required performance specifications [21,22].

2.1. $H_{\infty }$ Control Method

The design of the $H_{\infty }$ control method primarily addresses the tracking control problem of linear systems, as illustrated in Figure 3. In this framework, $\mu$ represents the control input, y is the measured output, $\omega$ is the disturbance input, and z is the controlled output. The transfer function matrix from the inputs $\mu$ and $\omega$ to the outputs z and y, denoted as G(s), is referred to as the augmented plant. It includes both the actual plant and additional weighting functions introduced to represent design specifications. K(s) denotes the controller [23,24].

Let the state-space realization of the transfer function matrix G(s) be given by

$$\begin{array}{cc}\hfill \dot{x}\left(t\right)& =Ax\left(t\right)+B_{1}w\left(t\right)+B_{2}u\left(t\right)\hfill \\ \hfill z\left(t\right)& =C_{1}x\left(t\right)+D_{11}w\left(t\right)+D_{12}u\left(t\right)\hfill \\ \hfill y\left(t\right)& =C_{2}x\left(t\right)+D_{21}w\left(t\right)+D_{22}u\left(t\right)\hfill \end{array}$$

(1)

In Equation (1), x is an n-dimensional state vector, $\omega$ is an r-dimensional disturbance vector, u is a p-dimensional control input vector, z is an m-dimensional controlled output vector, and y is a q-dimensional measured output vector. The above equation can therefore be rewritten in matrix form as

$$\begin{array}{c}\hfill G\left(s\right)=\left[\begin{array}{cc}{G}_{11}\left(s\right)\hfill & G_{12}\left(s\right)\hfill \\ G_{21}\left(s\right)\hfill & G_{22}\left(s\right)\hfill \end{array}\right]=\left[\begin{array}{ccc}A& B_1& B_2\\ C_1& D_{11}& D_{12}\\ C_2& D_{21}& D_{22}\end{array}\right]\end{array}$$

(2)

The closed-loop transfer function from $\omega$ to z is given by

$$\begin{array}{c}\hfill T_{zv}\left(s\right)=LFT[G\left(s\right),K\left(s\right)]=G_{11}+G_{12}K{\left(I-G_{22}K\right)}^{-1}{G}_{21}\end{array}$$

(3)

The theoretical core of this method lies in establishing constraints on three categories of transfer functions. The magnitude frequency characteristics of the sensitivity function S are constrained to ensure the system’s disturbance rejection capability; the complementary sensitivity function T is constrained to guarantee robust stability; and the magnitude frequency characteristics of the transfer function K(s) are constrained to limit the dynamic behavior of the actuators [25,26].

At the engineering implementation level, weighting functions are introduced to shape the magnitude frequency characteristics of the aforementioned transfer functions, forming a mixed sensitivity optimization problem. The optimal controller parameters are then obtained by solving the standard $H_{\infty }$ control problem.

2.2. Drag-Free Control Model

When implementing the $H_{\infty }$ control method using hardware circuits, the inherent digital nature of such systems necessitates the discretization of the continuous-time controller to enable realization within a digital control framework. The basic idea is to first design an analog controller in the continuous-time domain that meets the required control performance and then convert it into a digital controller through an appropriate approximation method [27,28]. This approach generally requires a sufficiently small sampling period; the smaller the sampling period, the closer the discrete system approximates the behavior of the original continuous system.

In the drag-free control algorithm module, the controllers for TM1 along the x-axis (TM1_−x) and TM2 along the x-axis (TM2_−x) are discretized using the frequency prewarped bilinear transformation method, while the controller for TM1 along the z-axis (TM1_−z) is implemented using the standard bilinear transformation method. After discretization, the transfer functions of the respective controllers are given as follows:

TM1_−x, TM2_−x:

$$\begin{array}{c}\hfill K_1={\displaystyle \frac{1044.3(s_1+5.352)(s_1+0.0007154)(s_1+0.0005659)(s_1^2+1.231s_1+0.8327)}{(s_1+22.42)(s_1+0.0004875)(s_1^2+0.001628s_1+6.942\times {10}^{-7})(s_1^2+3.432s_1+137)}}\end{array}$$

(4)

The transfer function of controller K₁ is defined as the ratio of the Laplace transform of the output signal to that of the input signal for TM1 and TM2 along the x-axis.

TM1_−z:

$$\begin{array}{c}\hfill K_2={\displaystyle \frac{391.4(s_2+6.687)(s_2+0.9014)(s_2+0.3303)(s_2+0.0007143)(s_2+0.0005667)}{(s_2+13.19)(s_2+0.0004877)(s_2^2+0.001628s+6.942\times {10}^{-7})(s_2^2+3.432s_2+137)}}\end{array}$$

(5)

The transfer function of controller K₂ is defined as the ratio of the Laplace transform of the output signal to that of the input signal for TM1 along the z-axis.

The attitude control loop algorithm module is discretized using the bilinear transformation method, which effectively preserves the system’s stability and dynamic characteristics. Under zero-delay conditions, the transfer function models of the controller system are derived theoretically.

In the discretization design of the electrostatic suspension control loop, symmetry coupling is applied with reference to Equations (4) and (5) under the no-delay condition. The controllers for TM1 along the y-axis (TM1_−y) and TM2 along the y-axis (TM2_−y) are discretized using the frequency prewarped bilinear transformation method, while the controller for TM2 along the z-axis (TM2_−z) adopts the standard bilinear transformation method. The controllers for all remaining degrees of freedom are discretized using the frequency prewarped bilinear transformation approach. This method enables the discretization of the $H_{\infty }$ control method to accommodate digital control systems.

3. Simulation Design and Implementation

The core objective of $H_{\infty }$ control is to minimize the impact of external disturbances on the system while ensuring overall stability [25,26,27]. In this study, the $H_{\infty }$ control method is implemented on both the Simulink simulation platform and an FPGA-based hardware platform. An ideal simulation environment is constructed to provide high-precision modeling, while hardware acceleration is employed to enhance the algorithm’s real-time processing capabilities. The drag-free control simulation system is realized in Simulink, enabling a fully integrated workflow, rapid algorithm iteration, and seamless hardware deployment. With built-in modules and automatic code generation tools, the closed loop from theoretical design to engineering validation is efficiently achieved. Furthermore, the high computational capability of the FPGA enables oversampling of the input signals, thereby enhancing the control accuracy of the drag-free control algorithm.

The rapid reconfigurable hardware implementation of the control algorithm model via the MATLAB (R2019b)/Simulink platform addresses the long development cycles and high complexity commonly associated with traditional FPGA development, which stem from hardware parallelism, resource constraints, and low-level logic design. The FPGA-based semi-physical simulation platform for drag-free control overcomes the limitations of conventional controllers in timing precision and multi-channel parallel processing. As a result, a high-precision ground-based semi-physical simulation platform has been successfully established to support ultra-sensitive weak-force measurement.

3.1. Based on Simulink

3.1.1. Simulation Design Based on Simulink

Based on the $H_{\infty }$ control method, a “strong-following” motion of the spacecraft simulation platform with respect to the test mass is realized under free-fall mode, while a “weak-following” mechanism of the test mass relative to the platform is established under active vibration isolation mode. Based on this mechanism, a drag-free control system simulation model is constructed using the Simulink platform.

The simulation platform comprises a total of 18 degrees of freedom. These include the sensitive axis directions of the dual-test mass system and the direction perpendicular to the optical axis plane of one test mass, where displacement-based drag-free control is applied. The remaining nine degrees of freedom are controlled via electrostatic suspension to achieve coordinated motion between the test masses and the electrode cage. Additionally, six degrees of freedom correspond to the satellite’s motion; among these, the three translational motions of the satellite are outcomes of the drag-free control and are not actively controlled within the closed-loop system and thus are neglected. The core drag-free control module based on Simulink is illustrated in Figure 4.

• The core drag-free control module also includes the following inputs: SCB_EattME, representing the satellite attitude error angles, and SCB_QtmME, representing the filtered 12-degree-of-freedom state variables of the two test masses.
• The outputs of the core drag-free control module include Cont_SC, which provides the drag-free control forces for the three degrees of freedom of the two test masses, as well as the satellite’s attitude pointing (three degrees of freedom) relative to a reference frame, and Cont_TM, which represents the electrostatic control forces for the remaining nine degrees of freedom of the test masses.
• Core control functions of the drag-free control module:

  -

  Inputs:

  SC_STATE: The physical input variable for a single degree of freedom of the satellite at time step n.

  x_n: The state vector corresponding to the state-space representation at time step n (initialized to zero).

  A, B, C, D: The discrete-time state-space coefficient matrices derived from the transfer function for the corresponding degree of freedom.

  -

  Basic Control Function:

  Computes the control force along the corresponding rotational axis by processing the single-degree-of-freedom state input of the satellite at time step n.

  -

  Outputs:

  y_n: The control force in the direction of the corresponding degree of freedom at time step n.

  x_n: The updated state vector in the state-space model at time step n, which serves as the input state for calculations at time step n + 1.

  -

  Detailed Algorithm:

  The current input estimation error is denoted as un. Compute the output control force as

  $$\begin{array}{c}\hfill y_n=Cxn+Dun\end{array}$$

  (6)

  -

  State Update:

  $$\begin{array}{c}\hfill x_n=A{x}_n+Bun\end{array}$$

  (7)

  This function is implemented in the Simulink model using the Discrete State-Space block. The Discrete State-Space block represents a system described by the following equations:

  $$\begin{array}{c}\hfill y\left(n\right)=Cx\left(n\right)+Du\left(n\right)\end{array}$$

  (8)

  $$\begin{array}{c}\hfill x(n+1)=Ax\left(n\right)+Bu\left(n\right)\end{array}$$

  (9)

  where u denotes the input, x the state vector, and y the output.

3.1.2. Modeling and Implementation Based on Simulink

To simplify the control of the entire loop, it is essential to analyze its driving factors. Each controller is designed to meet the closed-loop performance requirements within the scientific measurement bandwidth while also ensuring sufficient gain and phase margins across appropriate variations in the transfer function, including gain and stiffness.

The following presents a decomposition of the complete force and torque system acting on the satellite and the two test masses:

• Inputs acting on the spacecraft: FEEP thrust noise, solar radiation pressure and associated torque noise, and the reaction forces and torques induced by the test masses (resulting from electrostatic suspension actuation).
• Inputs acting on the test masses: electrostatic suspension control forces and torques, noise introduced by the electrostatic suspension actuation, and forces and torques resulting from the coupling between the spacecraft and the test masses, such as those induced by stiffness.

The following provides an analysis of the control loops acting on the spacecraft and the two test masses:

• The primary functions driving the spacecraft attitude control loop include shielding the test masses from external disturbances, reducing spacecraft attitude jitter by suppressing noise, managing control loop time delays, and accommodating variations in transfer function gain and phase margins.
• The primary objectives of the suspension control loop are stabilizing the non-drag-free coordinates of the test masses, which exhibit inherent negative stiffness, reducing test mass jitter caused by noise suppression, managing control loop time delays, and maintaining gain and phase margins in the presence of variations in transfer function gain and pole locations.

The control model of the entire system loop is shown in Figure 5.

Taking the satellite roll angle control algorithm within the satellite attitude error as an example, the drag-free control process is designed using the Discrete State-Space block. The core of this approach is to convert the satellite roll angle error into an output force along the roll axis. The inputs include SCB_EattME(0), which is the satellite roll angle error, $\phi$ x_n, which is the corresponding state variable in the roll angle control state-space representation (initialized to zero), and KSC.ztxA, KSC.ztxB, KSC.ztxC, and KSC.ztxD, which are the discrete state-space coefficient matrices derived from the roll axis control transfer function. By applying the basic control function Control_SC, the outputs obtained are Cont_ATT(0), which is the satellite roll axis output force, and $\phi$ x_n, which is the updated state variable in the state-space representation. The drag-free control processes for the other degrees of freedom are similar to the satellite roll angle control algorithm.

The drag-free control model was constructed in MATLAB/Simulink. Based on the noise characteristics described in reference [26], the model simulates the required noise signals through numerical simulation, including actuator noise, dynamic noise, and sensor noise, which serve as inputs for the system simulation. Figure 6 illustrates the simulated input noise signals.

Since the satellite’s three translational motions are outcomes of the drag-free control and are not actively controlled within the closed-loop system, they are omitted from the control loop. As a result, 15 simulated noise signals are generated, as shown in Figure 7a, to drive the remaining 15 degrees of freedom in the control simulation platform. The resulting drag-free control outputs are shown in Figure 7b.

Since all performance requirements are specified in terms of spectral density, the simulation results demonstrate that the designed controller effectively achieves drag-free control along the designated axis. The resulting noise spectral density remains below the relative jitter requirement, with position control accuracy reaching ±5 μm and attitude control accuracy reaching ±10 μrad.

3.2. Based on FPGA

The Zynq UltraScale+ MPSoC EG series, developed by Xilinx, is a high-performance heterogeneous multiprocessor system-on-a-chip (MPSoC) that integrates ARM multi-core processors, a field-programmable gate array (FPGA), and dedicated hardware acceleration units. It offers significant advantages in parallel processing, memory architecture, and computational performance. In this study, the Xilinx XCZU19EG-2FFVC1760I chip is employed to implement FPGA-based multi-channel drag-free control, data processing, command distribution, external communication, and the control and management of various memory devices.

Using an FPGA as the hardware platform for the core drag-free control algorithm can significantly enhance computational efficiency. Its integrated configurable logic blocks (CLBs) and look-up tables (LUTs) support hardware-level multi-instruction stream parallel processing, efficiently handling operations that involve large-scale multiply-accumulate tasks, such as fast Fourier transforms and digital filtering, thereby substantially improving computation speed and dynamic response. In terms of system stability, the FPGA logic architecture is built on deterministic timing circuits and does not rely on operating system task scheduling, making task execution time and response latency highly predictable. Additionally, its real-time status monitoring capability ensures reliable and consistent performance during long-term operation. Furthermore, FPGA allows for a flexible configuration of logic structures, data paths, and interface protocols, enabling the expansion of processing capacity through additional functional modules or deeper pipelines. Multiple control modules and communication interfaces can also be integrated within a single chip, demonstrating strong potential for system scalability.

3.2.1. Rapid Reconfigurable Technology

The Vitis Model Composer, a model-based design tool, is employed to implement rapid reconfigurable technology. Its core feature lies in the automatic generation of hardware implementation code from algorithmic models, enabling seamless integration from system simulation to hardware deployment, as illustrated in Figure 8. This tool operates within the MathWorks MATLAB and Simulink environments, supporting rapid design and automatic generation of hardware description language (HDL) code. With the deployment of this tool, control algorithm models developed in MATLAB/Simulink can be imported to the FPGA platform for hardware-level verification and design, thereby enabling both data computation and system control.

The use of rapid reconfigurable technology to generate HDL code is primarily intended for early-stage rapid verification, resource utilization assessment, and preliminary execution time testing. This approach can significantly shorten the conversion cycle from Simulink models to FPGA implementation, thereby improving development efficiency. The automatically generated HDL code is largely implemented using combinational logic, which facilitates subsequent synthesis and optimization. Compared with sequential logic, combinational logic consumes more resources but achieves higher computational speed, effectively trading additional resources for faster execution. The automatically generated HDL code also demonstrates good adaptability in cross-clock-domain designs, reducing the complexity and effort of manual intervention. As a result, it not only meets current design requirements but also offers strong maintainability and scalability. For the final deployment version, manual optimization should be applied on top of the automatically generated code to further enhance system performance and resource utilization, balancing resource consumption and execution time to satisfy stricter requirements for real-time operation and power efficiency.

When implementing rapid reconfigurable technology based on Simulink algorithms, it is essential to address the timing model of the system clock to eliminate interference across clock domains. A globally synchronized reset signal architecture must be configured. In this study, a high-level triggered asynchronous reset scheme is adopted. The drag-free control core algorithm is implemented using the Xilinx XCZU19EG-2FFVC1760I chip. During the configuration process, careful attention must be paid to parameter settings, interface specifications, and other key configuration parameters. Finally, the makehdl command is used to generate RTL-level Verilog code.

3.2.2. Design Base on FPGA

Using the rapid reconfigurable design capabilities of Vitis Model Composer, the drag-free control core algorithm is translated from a high-level software description to HDL. The algorithm is then synthesized on the Vivado (2019.1) platform, resulting in the hardware circuit diagram of the drag-free control core, as shown in Figure 9.

• The inputs to the drag-free core control module include EAttm_0-2, representing the satellite attitude angle errors, and Qtm_0-11, representing the filtered 12-degree-of-freedom state variables of the two test masses.
• The outputs of the drag-free core control module include Cont_Att_0-2, representing the satellite attitude control forces, Cont_DF_0-2, the drag-free control forces, and Cont_SU_0-8, the electrostatic control forces corresponding to the remaining nine degrees of freedom of the test masses.
• The core control function module of the drag-free control system includes a subsystem composed of three components, namely u_ATTControlZ (attitude control), u_DFControlZ (drag-free degree-of-freedom control), and u_SUSControlZ (electrostatic suspension). These modules collectively enable the implementation of the drag-free control core algorithm in a hardware environment.

The resource utilization of the synthesized core algorithm is summarized in

Table 1. Resource utilization.

Resource	Estimation	Available	Utilization%
LUT	330,359	522,720	63.2%
FF	209,088	1,045,440	20%
DSP	984	1968	50%

.

This design implements the drag-free control algorithm on the Xilinx XCZU19EG-2FFVC1760I chip. As shown in Table 1. The resource utilization is as follows: approximately 63.2% of LUTs and 20% of flip-flops (FFs) are occupied, demonstrating a reasonable hardware mapping efficiency. The core algorithm involves extensive matrix multiplications and filtering operations, with DSP block utilization around 50%, fully leveraging the FPGA hardware multiply-accumulate acceleration capabilities. The usage of internal block RAM is minimal, primarily for storing state variables and parameters, which has not been analyzed in detail. The relatively high utilization of LUTs directly reflects that the HDL code generated using rapid reconfigurable technology is primarily composed of combinational logic. This implementation approach leverages resource and power costs to achieve higher computational speed, aligning with the trade resources for performance strategy adopted in the earlier design phase.

As shown in

Table 2. On-chip power consumption.

Types	Targets				Overall
Dynamic	Signals	Logic	DSP	I/O
	2.02 W	1.96 W	0.21 W	0.70 W	4.89 W
	39.73%	38.53%	4.11%	13.70%	95.89%
Static	-				0.21 W
	-				4.11%

. According to power estimates obtained using the Vivado power analysis tool, the total on-chip power consumption is approximately 5.1 W. Dynamic power dominates at about 4.89 W, accounting for 95.89% of the total. Static power is approximately 0.21 W, accounting for 4.11% of the total. Overall, although the total power consumption is relatively moderate, this outcome is consistent with the trading resources for performance strategy adopted during the early design stage. Therefore, the proposed approach offers valuable reference potential for scenarios with stringent performance requirements.

Regarding timing, a comprehensive analysis of the maximum delay path based on Vivado timing reports shows a timing requirement of 20.429 ns. Additionally, the clock setup slack and hold slack are 14.143 ns and 0.054 ns, respectively, with a pulse width slack of 0.750 ns. Test results show that the timing jitter variance is less than 10⁻¹² s², and the maximum delay deviation is less than 5% of the clock period. The timing analysis indicates that the core algorithm predominantly relies on combinational logic, and the strategy of trading resource usage for speed has significantly enhanced the execution speed of the drag-free control core algorithm.

3.2.3. Modeling and Implementation Based on FPGA

In MATLAB/Simulink, the To Workspace Block is used to export the simulated noise signals generated by the Simulink model to the MATLAB workspace, where they are saved as programmable variables—such as SCB_ActuN, SCB_DynaN, and SCB_SensN, as shown in Figure 6. Since floating-point signal processing is relatively slow on FPGA hardware, the exported simulated noise signals are quantized and converted into a 16-bit fixed-point format suitable for FPGA computation. On the Vivado platform, these fixed-point signals are then used as inputs to the drag-free control core algorithm, implemented via rapid reconfigurable techniques, to evaluate the performance of the algorithm on the FPGA platform. The overall process is illustrated in Figure 10.

A file-based data exchange method was used in the Vivado test bench, where the $readmemh system task was invoked to load simulated noise signals as excitation inputs to the drag-free control core algorithm for simulation testing. The overall timing simulation results of the drag-free control algorithm are shown in Figure 11.

4. Discussion

By analyzing the data processing capability and control accuracy of the drag-free control simulation implemented concurrently on Simulink and FPGA platforms, the performance of the FPGA-based drag-free control hardware-in-the-loop simulation can be evaluated. Under identical input noise signal conditions, this evaluation is performed by comparing the control outputs of the drag-free control algorithm module with the numerical simulation results obtained from the Simulink platform.

4.1. Parallel Data Processing

To evaluate the differences in parallel computing performance between the Simulink and FPGA-based drag-free control hardware-in-the-loop simulation systems, a gradient testing method was employed. By progressively reconstructing the task topology, the control algorithm loop was expanded from a single channel to a 15-channel parallel architecture. The experiment recorded the system’s single-cycle computation latency at each level through a real-time monitoring module, establishing a quantitative model relating the parallel architecture to real-time performance metrics.

As shown in Figure 12, the runtime of the Simulink-based drag-free control core algorithm increases with the number of input noise channels, with computation times on the millisecond scale. The algorithm’s average execution time is 0.1416 s, and the timing stability is characterized by a variance of 2.0689 × 10⁻⁴ s² and a standard deviation of 0.0144 s. These quantitative results reveal the timing fluctuation characteristics of the algorithm operating in a non-real-time system environment. In contrast, the FPGA-based drag-free control core algorithm maintains stable runtime as the number of input noise channels increases, with computation times on the nanosecond scale. This demonstrates that the use of FPGA can effectively enhance the real-time computational capability of the drag-free control core algorithm.

4.2. Accuracy Comparison Analysis

Using the MATLAB platform, the output results from the Simulink and FPGA platforms were compared under identical input noise conditions. The actual drag-free control results were captured using an integrated logic analyzer (ILA). In the Vivado test bench file, the $fwrite function was used to store the simulation output as hexadecimal data in a binary file. On the MATLAB platform, the fopen function was used to read the binary file, extract the raw byte data, decode it into numerical values, and reconstruct the time axis for comparison with the Simulink output.

A comparative analysis was conducted on the output results of the drag-free control hardware-in-the-loop simulation systems implemented on FPGA and Simulink platforms under identical input conditions. As shown in Figure 13, steady-state output data were collected after 200, 5000, 10,000, and 20,000 drag-free control cycles. The experimental results clearly demonstrate that the red circles representing the Simulink-based outputs and the blue asterisks representing the FPGA-based outputs exhibit a high degree of overlap. This indicates strong consistency in the error convergence characteristics between the two implementation approaches.

To thoroughly evaluate the consistency between the two matrix outputs produced by different implementations of the drag-free control algorithm, a comprehensive difference analysis was conducted, as illustrated in Figure 14. Panel (a) displays the element-wise signed difference curve, which reveals both the direction and trend of fluctuations between corresponding elements in the two matrices. This provides insight into whether deviations tend to be positive or negative over the data set. Panel (b) presents the absolute difference values, offering a clear and intuitive representation of the magnitude of numerical discrepancies without regard to their sign, thereby emphasizing the size of deviations. Panel (c) shows the histogram distribution of the difference values, demonstrating that the majority of deviations are tightly clustered around zero, which strongly indicates a high degree of overall agreement between the two outputs. Lastly, panel (d) depicts the cumulative distribution function (CDF) of the differences, quantitatively illustrating the statistical concentration and stability of these deviations across all matrix elements. Collectively, these analyses confirm that the numerical differences between the software- and hardware-based implementations remain within an acceptable tolerance, thereby validating the accuracy and reliability of the FPGA realization of the drag-free control algorithm.

5. Conclusions

By formulating the system’s dynamic equations based on symmetry, the control strategy achieves consistency across multiple degrees of freedom, thereby enabling coordinated multi-axis control. Moreover, symmetry helps ensure an even distribution of control and compensation forces, effectively reducing control errors and structural vibrations. Furthermore, comparative analysis with the Simulink simulation platform demonstrates that the FPGA architecture, optimized using hardware description language, exhibits excellent consistency in control accuracy, further validating the effectiveness of the system design. Compared with conventional implementations, this approach significantly enhances the dynamic response speed and timing precision of the drag-free control semi-physical simulation system while maintaining control accuracy. Overall, the hardware-based implementation shows substantial advantages over traditional simulation platforms, clearly demonstrating its value for engineering applications. With the continuous development of drag-free control system actuators, such as micro-thrusters, the latency requirements for the core drag-free control algorithm are expected to increase. In this study, a ground-based hardware-in-the-loop drag-free control system is established, providing a valuable technical reference for the future application of this algorithm in actual satellites. In addition, FPGAs offer excellent scalability, providing a practical solution for future control tasks with higher degrees of freedom and a greater number of test masses.