Research on ADPLL for High-Precision Phase Measurement

Comments 1: The authors should write the reason for preferring an ADPLL architecture in terms of noise immunity and implementation scalability.

Response 1: We sincerely thank the reviewer for this excellent and insightful comment. We fully agree that providing a clear rationale for our choice of the ADPLL architecture would strengthen the manuscript. As suggested, we have added the following content to the third paragraph of the introduction of revised manuscript:

“As a digital circuit, ADPLL is less susceptible to power supply noise, substrate noise, and parasitic effects, which typically affect the performance of analogue PLLs. Additionally, the digital architecture offers high scalability on FPGA. This architecture meets the multi-channel, high-speed, and high-precision requirements of the PMS for space-based GW detection. “

Comments 2: Include a comparative analysis table to compare your results with similar published articles.

Response 2: We thank the reviewer for this constructive comment regarding the scope of our work. But it is hard to compare our results with similar published articles. Existing studies primarily focus on the impact of analog front-end circuits on PMS performance. Even after pilot tone calibration, the precision in those works remains at the  level due to residual analogue noise sources. In contrast, our study emphasizes the ADPLL algorithm itself and does not include an analog front-end. Therefore, the two approaches are not directly comparable.

Our results show that the noise of ADPLL can be significantly lower than the  level, being primarily limited by quantization noise. Although a few studies have reported similar digital signal measurement results, they often lack detailed loop parameter configurations, making meaningful comparisons difficult.

Comments 3: As the ADPLL-based phase measurement has been studied extensively, the authors should clarify its unique contributions. This could be in terms of architecture innovation, algorithmic improvement.

Response 3: We thank the reviewer for raising this point. While the field is relatively mature, designing an ADPLL that meets specific bandwidth and precision requirements remains challenging. Our key contributions are:

1) A systematic workflow for designing loop parameters to ensure sufficient phase margin and stable operation, starting from bandwidth requirements.

2) A comprehensive noise model that identifies three previously overlooked noise sources: PA readout noise, PIR readout noise, and phase noise due to amplitude quantization. These noise components cannot be suppressed by the loop and ultimately dominate the measurement performance.

3) Full disclosure of loop parameters and performance results, enhancing reproducibility and enabling meaningful comparisons in future studies.

Comments 4: Include the numerical findings in the conclusion section.

Response 4: We thank the reviewer for this constructive suggestion. We agree that incorporating the key numerical results will make the conclusion more impactful and concrete. We have now revised the conclusion s to include the primary numerical findings of our work.

Comments 5: Justify, on what basis you have selected the values of the loop parameters (as mentioned in table 1).

Response 5: We sincerely thank the reviewer for raising this critical point. The 80 MHz sampling frequency is employed to ensure non-aliasing sampling of heterodyne signals up to 25 MHz in space-based GW detection missions. To simplify the generation of digital heterodyne signals, we set the normalized gain to 1. Figure 5 indicates the optimal bandwidths of the PMS for the LISA and Taiji missions are 200 kHz and 250 kHz, respectively. Hence, we set the target bandwidth to 200 kHz. As noted in Section 3, the damping factor is typically preset to a value greater than 1 to compensate for significant phase lag introduced by the LPF and delay term. This ensures the actual loop has a sufficient phase margin. So, we set the preset damping factor to 2. Then the proportional gain and integral gain can be calculated via Equation (11). We have added a justification in the first paragraph of Section 5 of the revised manuscript:

‘’To ensure the actual loop has sufficient phase margin, the damping factor was set to 2. The proportional and integral gains were then calculated using Equation (11).’’

Comments 6: There are few errors like "Figure 5 illustrates the presents the calculated ......". Proofread the manuscript and correct such errors.

Response 6: We thank the reviewer for highlighting this error. The manuscript has been carefully proofread, and such grammatical inaccuracies have been corrected.

Comments 7: Write proper reason for nature of variation shown in different figures (fig. 5, fig. 6).

Response 7: We sincerely thank the reviewer for this insightful comment. The reasons for the nature of the variations are as follows:

For Figure 5:

• Trend: The variance of additive-noise-induced phase noise increases as the PLL bandwidth increases, whereas the variance of input-phase-noise-induced phase noise increases as the bandwidth decreases. Therefore, a PLL has an optimum bandwidth that minimizes the total phase noise variance from both input and additive noise.
• Reason: This behavior is a direct consequence of the PLL's differing responses to additive and input phase noise. For additive noise, the PLL exhibits a low-pass response, as detailed in Equation (20). For input phase noise, the PLL exhibits a high-pass response, as detailed in Equation (14).

As suggested, we have added the following content to the fourth paragraph of the subsection 4.1.2 of revised manuscript:

‘’As anticipated by Equations (20) and (14), the variance of additive-noise-induced phase noise increases as the PLL bandwidth increases (red line), whereas the variance of input-phase-noise-induced phase noise decreases as the bandwidth increases (green line). For comparative analysis, the phase error variance caused by shot noise is also calculated and presented for two additional received optical power levels: 1.2 nW (blue line) and 78 nW (gray line).’’

For Figure 6:

Figure 6 presents the frequency response of the measured closed-loop transfer function and open-loop transfer function in the form of a Bode plot. Bandwidth is defined as the frequency range where the closed-loop transfer function magnitude remains within -3 dB of its DC value. Phase margin numerically is equal to the difference between the phase at the unity gain angular frequency of the open-loop transfer function and - . Therefore, we can obtain the bandwidth and phase margin of the loop from Figure 6. The peak at 14 MHz in the Bode plot is caused by the second harmonic.

As suggested, we have added the following content to the first paragraph of the Section 5 of revised manuscript:

‘’By injecting broadband white noise perturbations into the error signal, the frequency response of both the system and the open-loop transfer functions for this loop were estimated. The results are presented in the Bode plot in Figure 6. The peak at 14 MHz in the Bode plot is caused by the second harmonic. The results indicate a loop bandwidth of approximately 180 kHz and a phase margin of approximately 60°.’’

We believe that these additions significantly improve the discussion and provide a solid physical interpretation of the results. Thank you again for this valuable suggestion.

1. Summary

2. Point-by-point response to Comments and Suggestions for Authors

Comments 1: The manuscript requires careful proofreading to improve the clarity and professionalism of the English writing. Several instances of awkward phrasing and errors were noted. For example: "illustrates the presents" → should be "presents" or "illustrates".

Response 1: We agree with the reviewer and thank you for highlighting this issue. The manuscript has been carefully proofread and all instances of unclear or unprofessional phrasing have been revised to improve readability and academic tone.

Comments 2: The experimental section lacks detailed description of key hardware platforms.

Response 2: We thank the reviewer for this feedback. All experiments in this study were implemented on a Terasic TR-530 development board equipped with a Stratix IV GX EP4SGX530C2 FPGA. Since the Terasic TR-530 development board lacks a built-in UART interface, an external USB-to-TTL module was used to facilitate data transmission between the FPGA and the computer. In practice, the results of digital measurements do not depend on their hardware implementation platform. As suggested, we have added the following content to the second paragraph of the Section 5 of the revised manuscript:

“All experiments in this study were implemented on a Terasic TR-530 development board equipped with a Stratix IV GX EP4SGX530C2 FPGA. Since the Terasic TR-530 development board lacks a built-in UART interface, an external USB-to-TTL module was used to facilitate data transmission between the FPGA and the computer.”

Comments 3: The references are outdated, failing to cite the latest research from the past 3-5 years, which does not demonstrate the work's positioning within the current state-of-the-art.

Response 3: We thank the reviewer for this critical suggestion. We have thoroughly updated the reference list to include several recent publications from the past five years. These additions help better situate our work within the current state-of-the-art and acknowledge relevant contemporary advances in the field.

Comments 4: Neither simulations nor experiments include control groups or benchmarking against existing algorithms, lacking comparative data to prove the superiority of the proposed method.

Response 4: We appreciate the reviewer’s comment. We apologize for any lack of clarity in our original manuscript. We would like to clarify that the ADPLL is currently the only solution used for phase measurement in intersatellite interferometry, and thus there are no alternative algorithms for direct comparison.

This work does not propose a new ADPLL algorithm, but rather establishes a scientific foundation for designing ADPLLs that meet specific phase measurement requirements. Our research has identified the determining factors for ADPLL performance. The simulations or experiments conducted in this paper have thoroughly validated the correctness of the proposed loop parameter design workflow and noise model.

Comments 5: The quality of Figure 8 must be significantly improved. The low resolution makes it difficult to evaluate the data presented. Please replace it with a high-resolution, clear version.

Response 5: We thank the reviewer for pointing this out. We sincerely apologize for the low resolution of the original figure, which was due to an error during the export process. Figure 8 has been replaced with a high-resolution version that clearly displays all data. The updated figure has been placed in Section 5 of the revised manuscript.

Response to Reviewer 3 Comments

1. Summary

We sincerely thank you for handling our manuscript and for the constructive comments. We appreciate the time and effort dedicated to reviewing our work, as the feedback has been invaluable in improving the quality and clarity of our manuscript.

We have carefully considered all the comments and have made revisions to the manuscript accordingly. Our point-by-point responses to your comments are detailed below. All changes in the manuscript have been highlighted in yellow for your convenience.

We hope that our revisions and responses have adequately addressed all the concerns raised and that the manuscript is now suitable for publication.

2. Point-by-point response to Comments and Suggestions for Authors

Comments 1: After the Digital measurements chapter, a comparison table could be included and figure 8 should be moved in this chapter.

Response 1: We sincerely appreciate the time and effort you have dedicated to reviewing our manuscript. Your comments have been invaluable in improving our work.

We have carefully considered your suggestion and have relocated Figure 8 to Section 5 as recommended. Regarding the addition of a comparison table, we agree that effective data presentation is crucial. After thorough consideration, we believe that Figure 8 in its revised form already provides a clear and comprehensive visual summary of the experimental results. We are concerned that adding a table might create redundancy without substantially enhancing the presented information.

Response to Reviewer 4 Comments

1. Summary

We sincerely thank you for handling our manuscript and for the constructive comments provided by the reviewers. We appreciate the time and effort dedicated to reviewing our work, as the feedback has been invaluable in improving the quality and clarity of our manuscript.

We have carefully considered all the comments and have made revisions to the manuscript accordingly. Our point-by-point responses to the reviewers' comments are detailed below. All changes in the manuscript have been highlighted in yellow for your convenience.

We hope that our revisions and responses have adequately addressed all the concerns raised and that the manuscript is now suitable for publication.

2. Point-by-point response to Comments and Suggestions for Authors

Comments 1: The introduction could benefit from a brief mention of the role of symmetry in phase-

locked loop design or noise modeling to better align with the scope of the journal.

Response 1: We thank the reviewer for this excellent suggestion. We agree that highlighting the role of symmetry will better align our manuscript with the journal's scope. As suggested, we have added the following content to the last paragraph of the Section 1 of revised manuscript:

“A symmetrical balance is inherent in the loop filter design, trading off tracking agility (wide bandwidth) against noise suppression (narrow bandwidth). As detailed in Section 4, identifying this optimum is essential for achieving a high-fidelity PMS.”

Comments 2: The derivation from the first to the second line of Equation (2) is not fully explained.

Please clarify the simplification step or cite a reference.

Response 2: We thank the reviewer for this insightful comment. The simplification from the first to the second line of Equation (2) involves combining the transfer functions of the constituent blocks (phase detector, loop filter, and NCO) in the z-domain, as is standard for linear ADPLL models. To provide a more complete derivation, we have added a citation to the canonical work by Gerberding et al. [1], which details this process in Section 2.2. This reference has been added to the revised manuscript following Equation (2).

[1] Gerberding, O.; Sheard, B.; Bykov, I.; Kullmann, J.; Delgado, J.J.E.; Danzmann, K.; Heinzel, G. Phasemeter Core for Intersat-ellite Laser Heterodyne Interferometry: Modelling, Simulations and Experiments. Class. Quantum Grav. 2013, 30, 235029, doi:10.1088/0264-9381/30/23/235029.

Comments 3: The captions for Figures 3 and 4 should explicitly state that the values are simulation-

based and under nominal conditions (fs = 80 MHz, D= 3, A= 0.8).

Response 3: We thank the reviewer for this precise feedback. We have updated the captions for both Figure 3 and Figure 4 to explicitly state that the results are derived from simulations under the nominal conditions of fs = 80 MHz, D= 3, A= 0.8.

Comments 4: Although overall clear, there are a few instances where grammar or phrasing could be

improved for fluency (e.g., “allows enables” on page 11, line 336). A careful proofreading pass is recommended.

Response 4: We thank the reviewer for their thorough review and for identifying these linguistic issues. We have carefully proofread the entire manuscript to improve grammar, phrasing, and overall fluency. The specific instance of "allows enables" on page 11, line 350 has been corrected to "allows". We believe these edits have significantly enhanced the clarity and readability of the manuscript.

Comments 5: The notation for truncation noise (e.g., , ) is introduced without a full definition.

A brief explanatory phrase would improve readability.

Response 5: We thank the reviewer for this thoughtful comment and for highlighting the need for clarity in our notation. We apologize for any confusion caused. Upon revisiting the text, we realize that our naming convention may have been misleading.

The variables  and  themselves do not denote truncated noise, but rather represent the intermediate signals in the loop. In the article, only variables with a tilde (˜) on top represent a type of noise. In fact, the original text has already provided a detailed introduction to truncated noise and given its definition at the beginning of Section 4.2.

Comments 6: The conclusion could be strengthened by briefly summarizing the key findings and

their implications for future missions like LISA, Taiji, and TianQin.

Response 6: We thank the reviewer for this excellent suggestion. We agree that explicitly stating the implications of our work will significantly strengthen its impact. We have revised the Conclusion section to summary the key findings and discuss their relevance to future space-borne gravitational wave detection missions.

Comments 7: Some references are incomplete (e.g., Refs. 15, 26). If possible, add links/websites

to access these references. Please ensure that all references are formatted consistently

and completely.

Response 7: We thank the reviewer for this critical feedback. All references have been reviewed and formatted consistently according to journal guidelines. The publication year for Reference 15 has been updated. Unfortunately, we were unable to obtain DOIs or URLs for References 15 and 26 despite extensive searches, but all available bibliographic details have been provided to ensure completeness.

1. Summary

2. Point-by-point response to Comments and Suggestions for Authors

Comments 1: The Bode plot in Figure 6 shows a noticeable peak at approximately 14 MHz, which the authors attribute to the "second harmonic." However, the manuscript does not elaborate on the origin of this harmonic. A brief explanation of the possible sources of this harmonic component can be provided

Response 1: We are grateful to the reviewer for this valuable suggestion. The issue you raise is indeed significant, and we concur that the origin of the harmonic peak at 14 MHz in Figure 6 warrants explanation. This second harmonic is in fact the sum-frequency component following the phase detector output. Only by neglecting this sum-frequency component can the error signal be linearized, thereby yielding the linear model of the PLL. The entire process is detailed in the second paragraph of Section 2 of the original paper. However, in the actual loop, this summing term cannot be entirely eliminated by a low-pass filter. Given that the frequency of digital input signal used in this paper is 7 MHz, the frequency of summing term or second harmonic is 14 MHz. This ultimately results in the peak at 14 MHz in the Bode plot of Figure 6. This further corroborates the authenticity of our simulation results. To better explain this issue, we have incorporated the following content on page 12, line 396 of the revised manuscript:

‘’The peak at 14 MHz in the Bode plot is caused by the sum-frequency component in the phase detector output which is neglected in Equation (1).’’