Polytopic Robust Stability for a Dual-Capacitor Boost Converter in Symmetric and Non-Symmetric Configurations

Abstract

The step-up power electronic converter, which is easily implemented with two symmetric parallel-boost stages, has recently been proposed in the literature, showing considerable voltage gains with no excessive duty cycle, thus minimizing heat and other adverse effects. Its other advantages are floating-output voltage and increased power density because of the diminution of the capacitors’ voltage rating. In this paper, the Lyapunov-based robust stability of a converter operating in both closed- and open-loop is proved, showing its versatility even during the variation of parameters, which nullifies the symmetry of the converter. Simulation and experimental data allow the corroboration of the analysis.

1. Introduction

In the transition from traditional power systems to smart grids, symmetry is a term connected with power system modeling and analysis. Modern electronics widely use electronic converters, allowing impedance coupling in electric source and load connections. Frequently, symmetry in the electronic design enhances singular characteristics for the benefit of an improved operation. For instance, voltage step-up or boost converters are commonly used in the generation of green energy from various homogeneous power harvesting sources to match the voltage levels of loads such as batteries, supercapacitors, grids, and smart grids, among many others [1]. Increasing the power-per-size relationship (power density) and lowering the building cost are also relevant characteristics of these step-up converters. State-of-the-art symmetric circuit configurations (topologies) provide these characteristics, as well as bi-directionality and high voltage gain [2,3,4].

Still, there is a need to enhance the power density of electronic converters and, for instance, increase the voltage gain of boost-type converters, which is a trade-off between size and voltage amplification. A classic boost converter with a single capacitor gains up to five times the input voltage with moderate efficiency. Still, the output capacitor must be at least of such an output voltage rating [5] and, hence, of a relatively big size, and other series or cascaded configurations have this drawback. On the other hand, gains that are more significant than five can be obtained with different topologies at the cost of an increased component number, including those with magnetic coupling [6,7,8].

The topology studied in this paper and shown in Figure 1 effectively reduces the volume and cost of having a (big) single-output capacitor (see, for example, [9,10,11]); this is achieved by lowering the voltage rating because of a symmetric connection of two capacitors. Although other double-series unidirectional capacitor topologies were presented in [12], the configuration used in this paper requires only two switches, can be expanded for bidirectional usage (adding two more switches), and provides significant voltage gain from moderate duty cycles, thus reducing conduction losses. Related topologies and their characteristics were also presented in a review [13] and in the literary works of [14,15,16,17]; however, none of the above include the dynamic analysis of the topology used in this paper, and, nowadays, knowing power converters’ properties—such as their controllability and stability in closed- and open-loop conditions—is indispensable.

To the author’s knowledge, the presented topology is novel and has not been studied for its dynamic and control behavior. Hence, the contributions of this paper to the state of the art are the following:

• A novel symmetric dual-capacitor boost converter topology.
• The (polytopic) model of the topology in which dynamic and linear parameters are varied, in addition to numerical and experimental validations.
• An asymptotic stability analysis against bounded parameter uncertainty in both closed and open loops, including asymmetric and symmetric stances.
• Numerical and experimental corroboration of stability and performance using a PI control scheme.

2. Preliminaries

From the topology shown in Figure 1, equal PWM pulses in both $S_1,S_2$ switches allow the energy charge in both inductors $L_1,L_2$ and the discharge in both $C_1,C_2$ capacitors, respectively, whose voltages $v_1$ and $v_2$ increase, which also augments the output voltage $v_o$ in the load R by:

$$\begin{array}{c}\hfill v_0=E+v_1+v_2\end{array}$$

(1)

If the duty cycle d of the PWM remains zero, the output voltage will be $v_0=E$, as in a regular one-stage boost converter. Duty-cycle values near unity are avoided because of the high switch conduction losses, which induce overheating and possible device damage. Note that the voltage rating of $C_1,C_2$ is less than that of a regular single-capacitor boost converter (in a boost converter, the voltage of the output capacitor must be at least $v_o$), and that serialized stages allow more considerable voltage gains.

A standard average technique in a CCM (see [5], for instance) allows one to obtain the expressions that model the converter:

$$\begin{array}{c}\hfill L_1\frac{d_{i_1}}{dt}=dE-(1-d)v_1\end{array}$$

(2)

$$\begin{array}{c}\hfill L_2\frac{d_{i_2}}{dt}=dE-(1-d)v_2\end{array}$$

(3)

$$\begin{array}{c}\hfill C_1\frac{d_{v_1}}{dt}=(1-d)i_1-\frac{E+v_1+v_2}{R}\end{array}$$

(4)

$$\begin{array}{c}\hfill C_2\frac{d_{v_2}}{dt}=(1-d)i_2-\frac{E+v_1+v_2}{R}\end{array}$$

(5)

In addition, a simple analysis for smart ripple consideration allows one to obtain the ideal output voltage gain:

$$\begin{array}{c}\hfill v_o=E\frac{1+D}{1-D}\end{array}$$

(6)

In Figure 2 is shown a simple validation of the above model in which $d=0.67$ is used to obtain $v_o\approx 100$ V. The adequate values for obtaining a CCM with a 100 W load are calculated (

Table 1. Parameters for the converter.

Parameter	Value	Units
$C_1,C_2$	10	$\mathsf{\mu }$F
E	20	V
$L_1,L_2$	250	$\mathsf{\mu }$F
PWM frequency	50	kHz
R	100	$\mathsf{\Omega }$

). A 3% error in the steady state and a maximum of 9% error in the transient stage due to some non-ideal characteristics were included in the simulation software as the forward diode voltage and diode resistance of the switches. Nonetheless, the above model is qualitatively accurate and tractable for control purposes.

3. Results

The state-space representation of (5) can be written as:

$$\begin{array}{c}\hfill \dot{y}=Ay+B\end{array}$$

(7)

where

$$\begin{array}{ccc}\hfill y=\left[\begin{array}{c}{i}_1\\ i_2\\ v_1\\ v_2\end{array}\right],& A=\left[\begin{array}{cccc}0& 0& -\frac{1-d}{L_1}& 0\\ 0& 0& 0& -\frac{1-d}{L_2}\\ \frac{1-d}{C_1}& 0& -\frac{1}{R{C}_1}& -\frac{1}{R{C}_1}\\ 0& \frac{1-d}{C_2}& -\frac{1}{R{C}_2}& -\frac{1}{R{C}_2}\end{array}\right],& B=\left[\begin{array}{c}\frac{dE}{L_1}\\ \frac{dE}{L_2}\\ -\frac{E}{R{C}_1}\\ -\frac{E}{R{C}_2}\end{array}\right],\hfill \end{array}$$

(8)

and the time dependence of A (recall that $d:\mathbb{R}\to \mathbb{R}$) and the states is omitted for readability. Since A is invertible, the variable change $x=y-A^{-1}B$ allows for the shifting of the operating point to the origin; hence:

$$\begin{array}{c}\hfill \dot{x}=Ax.\end{array}$$

(9)

An LPV representation of the above model is:

$$\begin{array}{c}\hfill \dot{x}=Ax=\sum _{i=1}^n{A}_i{\theta }_{i}x\end{array}$$

(10)

where ${\theta }_i$ are numbers such that ${\sum }_{i=1}^n{\theta }_i=1$, $0\le {\theta }_i\le 1$$\forall i$ (simplex), and $n=2^6=64$; that is, the matrix A is represented as a polytopic sum of the vertexes multiplied by the corresponding variation ${\theta }_i$. Recall that the vertexes are built with the combinations of the maximum and minimum values of each nonzero entry of A, since one considers that all of the converter parameters are time-varying within bounded values; for instance, one knows that $\underline{L_1}\le L_1\left(t\right)\le \overline{L_1}$ and $\underline{d}=0\le d\left(t\right)\le \overline{d}$; hence, the first row of the third column of $A_1$ has the lowest possible value $\frac{1-\overline{d}}{\overline{L_1}}=\underline{a_{1,3}}$. Repeating that for the rest of entries results in:

$$\begin{array}{c}\hfill A_1=\left[\begin{array}{cccc}0& 0& -\underline{a_{1,3}}& 0\\ 0& 0& 0& -\underline{a_{2,4}}\\ \underline{a_{3,1}}& 0& -\underline{a_{3,3}}& -\underline{a_{3,4}}\\ 0& \underline{a_{4,2}}& -\underline{a_{4,3}}& -\underline{a_{4,4}}\end{array}\right]\end{array}$$

(11)

which represents the first vertex of the polytopic representation. For the second vertex, the first row of the third column of $A_1$ is the greatest possible value $\frac{1-\underline{d}}{\underline{L_1}}=\overline{a_{1,3}}$, while the rest of the entries remain with their minimum values (underlined). For the third vertex, the second row of the fourth column of $A_1$ is built by finding the minimum ($\underline{a_{2,4}}$) and maximum ($\overline{a_{2,4}}$) values of the entry, and the rest of the entries remain in their minimal values. Once vertexes with a single maximum entry are found (eight), those with combinations of two or more overlined entries are found to obtain the 64 vertexes. That is, the rest of the vertexes are built with a binary combination of the minimum and maximum entries of A:

$$\begin{array}{cc}\hfill A_2=\left[\begin{array}{cccc}0& 0& -\overline{a_{1,3}}& 0\\ 0& 0& 0& -\underline{a_{2,4}}\\ \underline{a_{3,1}}& 0& -\underline{a_{3,3}}& -\underline{a_{3,4}}\\ 0& \underline{a_{4,2}}& -\underline{a_{4,3}}& -\underline{a_{4,4}}\end{array}\right],& A_3=\left[\begin{array}{cccc}0& 0& -\underline{a_{1,3}}& 0\\ 0& 0& 0& -\overline{a_{2,4}}\\ \underline{a_{3,1}}& 0& -\underline{a_{3,3}}& -\underline{a_{3,4}}\\ 0& \underline{a_{4,2}}& -\underline{a_{4,3}}& -\underline{a_{4,4}}\end{array}\right],\dots ,\end{array}$$

(12)

$$\begin{array}{cc}\hfill A_{63}=\left[\begin{array}{cccc}0& 0& -\overline{a_{1,3}}& 0\\ 0& 0& 0& -\overline{a_{2,4}}\\ \overline{a_{3,1}}& 0& -\overline{a_{3,3}}& -\overline{a_{3,4}}\\ 0& \overline{a_{4,2}}& -\overline{a_{4,3}}& -\underline{a_{4,4}}\end{array}\right],& A_{64}=\left[\begin{array}{cccc}0& 0& -\overline{a_{1,3}}& 0\\ 0& 0& 0& -\overline{a_{2,4}}\\ \overline{a_{3,1}}& 0& -\overline{a_{3,3}}& -\overline{a_{3,4}}\\ 0& \overline{a_{4,2}}& -\overline{a_{4,3}}& -\overline{a_{4,4}}\end{array}\right],\end{array}$$

(13)

where all $a_{·,·}>0$. The vertexes are constant in the above polytopic representation, and the ${\theta }_i$ values represent the variations in the parameter. The advantage of such a representation is that the robust control theory demonstrates global asymptotic stability if all of the vertexes are individually Lyapunov-stable using a common Lyapunov function.

Theorem 1.

The polytopic system (10) is globally asymptotically stable.

Proof. 

Consider the common Lyapunov candidate function

$$\begin{array}{c}\hfill V=\frac{1}{2}\left({\eta }_1{i}_1^2+{\eta }_2{i}_2^2+{\eta }_3{v}_1^2+{\eta }_4{v}_1^2\right),\end{array}$$

(14)

where all values of eta are positive constants; hence, $V\left(0\right)=0$ and is positive for any other argument values. The time derivative along the system trajectories for some vertex of (10) is:

$$\begin{array}{ccc}\hfill \dot{V}& =& ({\eta }_3{a}_{3,1}-{\eta }_1{a}_{1,3})i_1{v}_1+({\eta }_4{a}_{4,2}-{\eta }_2{a}_{2,4})i_2{v}_2-({\eta }_3{a}_{3,4}+{\eta }_4{a}_{4,3})v_1{v}_2\hfill \\ & & -{\eta }_3{a}_{3,3}{v}_1^2-{\eta }_4{a}_{4,4}{v}_2^2\hfill \end{array}$$

(15)

Since all state variables are positive (the configuration of diodes only allows positive values), the only conditions for negativeness of $\dot{V}$ are:

$$\begin{array}{c}\hfill \frac{{\eta }_3}{{\eta }_1}<\frac{a_{1,3}}{a_{3,1}},\end{array}$$

(16)

$$\begin{array}{c}\hfill \frac{{\eta }_4}{{\eta }_2}<\frac{a_{2,4}}{a_{4,2}}.\end{array}$$

(17)

As all parameters are considered to be time-varying but bounded within known positive limits, one can always find constants ${\gamma }_1$ and ${\gamma }_2$ such that $\dot{V}<0$. By the theory of robust control [18], all of the conditions for global stability are met. □

4. Numerical Simulation

Consider the nominal parameters of Table 1, a classic PI voltage controller set to a 100 V reference with variation ranges of $\underline{L_1}=200$ $\mathsf{\mu }$H, $\overline{L_1}=300$ $\mathsf{\mu }$H, $\underline{C_1}=100$ $\mathsf{\mu }$F, and $\overline{C_1}=200$ $\mathsf{\mu }$F, and similar bounds for $L_2$ and $C_2$. Figure 3 shows the behavior of the output voltage for representative parameter variations; the different combinations of other parameters do not affect the dynamics considerably with respect to the nominal values and are not shown in such a plot. However, the most important characteristic is the asymptotic stability in the closed loop.

5. Experimental Results

A converter prototype was built to corroborate the analytic and numerical results (Figure 4). The first test was performed with an abrupt load change from 100 to 50 $\mathsf{\Omega }$ with a 600 W programmable DC electronic load (Model 8510 from BK PRECISION). This is shown at $t=0.13$ s of Figure 5. The experimental data were captured with a four-channel oscilloscope and plotted in Matlab; hence, the time shown is used only for reference.

The second test consisted of the modification of the values $L_2=200$ $\mathsf{\mu }$H and $C_2=5$ $\mathsf{\mu }$F with the expectation of preserving the stability for a reference change from 20 to 100 V. Figure 6 shows the output voltage behavior; it can be easily noted that the stability was preserved even for such parametric changes. Figure 7 shows that these parametric changes only affected the ripple in a capacitor, but the dynamic behavior remained acceptable.

6. Conclusions

This paper reports a study of robust stability against parametrically bounded and arbitrary variations for a double-capacitor boost converter. This topology showed excellent stability properties, and the tuning of a simple controller was easy to perform without a destabilization risk. Additionally, the significant voltage gain, high power density, high efficiency (about 95% for the proposed parameters), and the non-pulsating voltage between the input and output made the converter versatile. An analysis of parasitic components in electronic devices for high-resilience systems will be performed in future work. In addition, cascaded configurations and the dynamic behavior with a constant power load must be further analyzed.