A New Bridgeless High Step-up Voltage Gain PFC Converter with Reduced Conduction Losses and Low Voltage Stress

Bridgeless power factor correction (PFC) converters have a reduced number of semiconductors in the current flowing path, contributing to low conduction losses. In this paper, a new bridgeless high step-up voltage gain PFC converter is proposed, analyzed and validated for high voltage applications. Compared to its conventional counterpart, the input rectifier bridge in the proposed bridgeless PFC converter is completely eliminated. As a result, its conduction losses are reduced. Also, the current flowing through the power switches in the proposed bridgeless PFC converter is only half of the current flowing through the rectifier diodes in its conventional counterpart, therefore, the conduction losses can be further improved. Moreover, in the proposed bridgeless PFC converter, not only the voltage stress of power switches is lower than the output voltage, but the voltage stress of the output diodes is lower than the conventional counterpart. In addition, this proposed bridgeless PFC converter features a simple circuit structure and high PFC performance. Finally, the proposed bridgeless PFC converter is analyzed and designed in the discontinuous conduction mode (DCM). The simulation results are presented to verify the effectiveness of the proposed bridgeless PFC converter.


Introduction
In the past decades, AC-DC converters have been widely used in numerous power electronic equipment supplied by the power grid in order to obtain the DC voltage. For the passive AC-DC rectifier, the input current harmonics are large, which is very harmful for the power grid and other power electronic equipment. In order to alleviate the input current harmonics and satisfy the rigorous input current harmonic standards, for instance, the IEC 61000-3-2 criterion, the active power factor correction (PFC) converter has become a popular and effective method to shape the input current waveform and achieve the near unity power factor (PF) in the power supplies. For single-phase power supplies, the boost topology is the most popular option as the PFC pre-regulator, by reason of its simple circuit structure and high PFC performance [1][2][3]. Unfortunately, the boost topology cannot achieve a very high voltage gain in practical applications, because the extremely high duty cycle is unpractical. Therefore, in some high voltage applications, for example, X-ray medical/industry equipment, HVDC system insulator testing, electrostatic precipitators and high voltage battery charger, the boost PFC converter is a poor candidate, especially for the universal line [4,5].

Operation Principle
This proposed bridgeless high step-up voltage gain PFC converter uses two bidirectional switches in series with two same level inductors. Each bidirectional switch is constructed by two antiseries power switches. It should be noted that the two power switches in one bidirectional switch have the common source terminal, which can simplify the drive circuit. Simultaneously, an output bridge including D1, D2, D3 and D4 which are fast-recovery diodes is used to obtain a high DC output voltage in the proposed bridgeless PFC converter, while only D5 is the fast-recovery diode in its conventional counterpart. The proposed bridgeless PFC converter is designed to operate in DCM. Thereby, it has three operation modes during one switching period. The detailed operation modes of one switching period in the positive line cycle are presented in Figure 3. Since the proposed bridgeless PFC converter is symmetrical, the operation modes in negative line cycle are similar to the modes in positive line cycle. Its key time-domain waveforms are exhibited in Figure 4.
Mode I shown in Figure 3a：when the power switches S1 and S3 are turned on, the input sinusoidal source vin charges the two inductors L1 and L2, simultaneously, through the power switches S2 and S4. The output bulk capacitor maintains the output voltage vo. In each branch of the proposed bridgeless PFC converter, only two semiconductors consisting by two power switches are active, while three semiconductors are active in one branch of the conventional counterpart. In this mode, the inductor currents satisfy: Mode II shown in Figure 3b: when all the power switches are turned off, the input source and the two inductors releases energies to the load. Only two output fast-recovery diodes conduct in this mode, while three semiconductors including two slow-recovery diodes and one fast-recovery diode conduct in the corresponding conventional counterpart. In this mode, the inductor currents satisfy:

Operation Principle
This proposed bridgeless high step-up voltage gain PFC converter uses two bidirectional switches in series with two same level inductors. Each bidirectional switch is constructed by two antiseries power switches. It should be noted that the two power switches in one bidirectional switch have the common source terminal, which can simplify the drive circuit. Simultaneously, an output bridge including D1, D2, D3 and D4 which are fast-recovery diodes is used to obtain a high DC output voltage in the proposed bridgeless PFC converter, while only D5 is the fast-recovery diode in its conventional counterpart. The proposed bridgeless PFC converter is designed to operate in DCM. Thereby, it has three operation modes during one switching period. The detailed operation modes of one switching period in the positive line cycle are presented in Figure 3. Since the proposed bridgeless PFC converter is symmetrical, the operation modes in negative line cycle are similar to the modes in positive line cycle. Its key time-domain waveforms are exhibited in Figure 4.
Mode I shown in Figure 3a：when the power switches S1 and S3 are turned on, the input sinusoidal source vin charges the two inductors L1 and L2, simultaneously, through the power switches S2 and S4. The output bulk capacitor maintains the output voltage vo. In each branch of the proposed bridgeless PFC converter, only two semiconductors consisting by two power switches are active, while three semiconductors are active in one branch of the conventional counterpart. In this mode, the inductor currents satisfy: Mode II shown in Figure 3b: when all the power switches are turned off, the input source and the two inductors releases energies to the load. Only two output fast-recovery diodes conduct in this mode, while three semiconductors including two slow-recovery diodes and one fast-recovery diode conduct in the corresponding conventional counterpart. In this mode, the inductor currents satisfy:

Operation Principle
This proposed bridgeless high step-up voltage gain PFC converter uses two bidirectional switches in series with two same level inductors. Each bidirectional switch is constructed by two anti-series power switches. It should be noted that the two power switches in one bidirectional switch have the common source terminal, which can simplify the drive circuit. Simultaneously, an output bridge including D 1 , D 2 , D 3 and D 4 which are fast-recovery diodes is used to obtain a high DC output voltage in the proposed bridgeless PFC converter, while only D 5 is the fast-recovery diode in its conventional counterpart. The proposed bridgeless PFC converter is designed to operate in DCM. Thereby, it has three operation modes during one switching period. The detailed operation modes of one switching period in the positive line cycle are presented in Figure 3. Since the proposed bridgeless PFC converter is symmetrical, the operation modes in negative line cycle are similar to the modes in positive line cycle. Its key time-domain waveforms are exhibited in Figure 4.
Mode I shown in Figure 3a: when the power switches S 1 and S 3 are turned on, the input sinusoidal source v in charges the two inductors L 1 and L 2 , simultaneously, through the power switches S 2 and S 4 . The output bulk capacitor maintains the output voltage v o . In each branch of the proposed bridgeless PFC converter, only two semiconductors consisting by two power switches are active, while three semiconductors are active in one branch of the conventional counterpart. In this mode, the inductor currents satisfy: Mode II shown in Figure 3b: when all the power switches are turned off, the input source and the two inductors releases energies to the load. Only two output fast-recovery diodes conduct in this mode, while three semiconductors including two slow-recovery diodes and one fast-recovery diode conduct in the corresponding conventional counterpart. In this mode, the inductor currents satisfy: Mode III shown in Figure 3c: all the semiconductors are in the off state. The inductor currents are zero. The output bulk capacitor C maintains the output voltage. Figure 4 presents the key waveforms of duty cycle D, inductor current i L1 , i L2 , input current i in , and the voltage v S1 , v S3 , v D1 , v D4 across the semiconductors in the positive line cycle. From this figure, the inductor current i L1 , i L2 are equal to each other. When the power switches are turned on, the inductor current are half of the input current i in . When the power switches are turned off, the inductor current are same with the input current. The maximum voltage across the power switches and the output diodes are (v in + v o )/2 in the positive line cycle. It should be noted that the duty cycle D equals to (t 2 − t 1 )/T S , where T S is the switching period.
Energies 2018, 11, 2640 4 of 14 Mode III shown in Figure 3c: all the semiconductors are in the off state. The inductor currents are zero. The output bulk capacitor C maintains the output voltage.

Theoretical Analysis
The detailed theoretical analysis and designed consideration in DCM are presented in this subsection. First of all, some ideal assumptions are provided to simplify the analysis. Notably, the theoretical analysis is made in one positive line cycle. These assumptions are shown as follows: • The switching frequency fs is much higher than the line frequency. Thus, the input voltage is constant during one switching period.

•
The capacitance of the bulk capacitor is large enough. Thereby, the output voltage is ideal constant.

•
All the components are ideal without losses.

•
The input voltage is ideally sinusoidal.

The Voltage Conversion Ratio M
Appling the voltage-second balance principle to the inductor L1, the voltage conversion ratio M is derived as follows: where vm is the amplitude of the sinusoidal input voltage vin, θ is the angle of the input voltage vin, and Dx is equal to (t3 − t2)/TS. Based on (3), the relationship between the duty cycle D and Dx can be expressed as: In addition, the peak inductor current iL1-peak in one switching period is:

Theoretical Analysis
The detailed theoretical analysis and designed consideration in DCM are presented in this subsection. First of all, some ideal assumptions are provided to simplify the analysis. Notably, the theoretical analysis is made in one positive line cycle. These assumptions are shown as follows: • The switching frequency f s is much higher than the line frequency. Thus, the input voltage is constant during one switching period.

•
The capacitance of the bulk capacitor is large enough. Thereby, the output voltage is ideal constant. • All the components are ideal without losses.

•
The input voltage is ideally sinusoidal.

The Voltage Conversion Ratio M
Appling the voltage-second balance principle to the inductor L 1 , the voltage conversion ratio M is derived as follows: where v m is the amplitude of the sinusoidal input voltage v in , θ is the angle of the input voltage v in , and D x is equal to (t 3 − t 2 )/T S . Based on (3), the relationship between the duty cycle D and D x can be expressed as: In addition, the peak inductor current i L1-peak in one switching period is: Due to the power balance between input power and output power, we can get: Substituting (4) and (5) into (6), the relationship of the voltage conversion ratio M and duty cycle D is derived as follows: where the dimensionless conduction parameter K is: and the parameter β is The relationship of the voltage conversion ratio M and duty cycle D is presented in Figure 5. From this figure, one can see that the voltage conversion ratio M increases with the lower parameter K. Compared to the conventional boost PFC converter, the voltage conversion ratio M of the proposed bridgeless PFC converter is much higher. Therefore, the proposed bridgeless PFC converter is more suitable for the high voltage applications.
Energies 2018, 11, 2640 6 of 14 Due to the power balance between input power and output power, we can get: Substituting (4) and (5) into (6), the relationship of the voltage conversion ratio M and duty cycle D is derived as follows: where the dimensionless conduction parameter K is: and the parameter β is The relationship of the voltage conversion ratio M and duty cycle D is presented in Figure 5. From this figure, one can see that the voltage conversion ratio M increases with the lower parameter K. Compared to the conventional boost PFC converter, the voltage conversion ratio M of the proposed bridgeless PFC converter is much higher. Therefore, the proposed bridgeless PFC converter is more suitable for the high voltage applications.

The Operation Conditon for DCM
In order to operate in DCM, the operation condition must satisfy as follows: Substituting (3) and (7) into (10), the operation condition for DCM is derived as:

The Operation Conditon for DCM
In order to operate in DCM, the operation condition must satisfy as follows: Substituting (3) and (7) into (10), the operation condition for DCM is derived as: The proposed bridgeless PFC converter is designed to operate in DCM totally. Therefore, the inductor currents should be discontinuous at the peak point in the line cycle. Thus, the simplified operation condition for DCM is: Figure 6 draws the operation boundary between the DCM and the continuous conduction mode (CCM). From this figure, the operation boundary is higher at the low voltage conversion ratio. However, for the universal line, the voltage conversion ratio is different under different input voltage. Hence, the key parameter K must be designed at the lowest input voltage. The proposed bridgeless PFC converter is designed to operate in DCM totally. Therefore, the inductor currents should be discontinuous at the peak point in the line cycle. Thus, the simplified operation condition for DCM is: Figure 6 draws the operation boundary between the DCM and the continuous conduction mode (CCM). From this figure, the operation boundary is higher at the low voltage conversion ratio. However, for the universal line, the voltage conversion ratio is different under different input voltage. Hence, the key parameter K must be designed at the lowest input voltage.

The Voltage Stress and Current Stress
The voltage stress of semiconductors in the proposed bridgeless PFC converter and in its conventional bridge counterpart are shown in Table 1. From this table, the voltage stress of power switch in the proposed bridgeless PFC converter is same with its conventional bridge converter, and it is lower than the output voltage. The voltage stress of fast-recovery diode in the proposed bridgeless PFC converter is lower than that in the conventional bridge converter. Therefore, the lower rated diode can be used in the proposed bridgeless PFC converter. It is beneficial to improve cost and losses. In addition, no slow-recovery diode is used in the proposed bridgeless PFC converter, while four slow-recovery diodes as the input bridge are used in its conventional bridge counterpart, and their voltage stress is vm. The root-mean-square (RMS) current iS1-rms of power switch in one switching period is shown as follows: The averaged current iD1-avg of output diode in one switching period is derived as follows:

The Voltage Stress and Current Stress
The voltage stress of semiconductors in the proposed bridgeless PFC converter and in its conventional bridge counterpart are shown in Table 1. From this table, the voltage stress of power switch in the proposed bridgeless PFC converter is same with its conventional bridge converter, and it is lower than the output voltage. The voltage stress of fast-recovery diode in the proposed bridgeless PFC converter is lower than that in the conventional bridge converter. Therefore, the lower rated diode can be used in the proposed bridgeless PFC converter. It is beneficial to improve cost and losses. In addition, no slow-recovery diode is used in the proposed bridgeless PFC converter, while four slow-recovery diodes as the input bridge are used in its conventional bridge counterpart, and their voltage stress is v m .

Proposed Bridgeless PFC Converter Conventional Bridge PFC Converter
Power switch The root-mean-square (RMS) current i S1-rms of power switch in one switching period is shown as follows: The averaged current i D1-avg of output diode in one switching period is derived as follows:

The Conduction Losses
In this subsection, the conduction losses of semiconductors are calculated. The detail derivations in one positive line cycle are exhibited as follows: where R on is the conduction resistance of the power switch and V F is the forward voltage of diodes. Under the operation condition v in = 220 V rms /50 Hz, v o = 800 V, f s = 30 kHz and P o = 500 W, the conduction losses of semiconductors are calculated. It should be noted that the parameters R on and V F are chosen from the datasheet of the selected components. The conduction losses of semiconductors of the proposed bridgeless PFC converter and its conventional counterpart are presented in Figure 7. From this figure, it can be found that the total conduction losses of semiconductors in the proposed bridgeless PFC converter is much lower than its conventional bridge counterpart. The conduction losses of power switches in the proposed bridgeless PFC converter are higher, while it has no conduction losses of input rectifier diodes.

The Conduction Losses
In this subsection, the conduction losses of semiconductors are calculated. The detail derivations in one positive line cycle are exhibited as follows: where Ron is the conduction resistance of the power switch and VF is the forward voltage of diodes.
Under the operation condition vin = 220 Vrms/50 Hz, vo = 800 V, fs = 30 kHz and Po = 500 W, the conduction losses of semiconductors are calculated. It should be noted that the parameters Ron and VF are chosen from the datasheet of the selected components. The conduction losses of semiconductors of the proposed bridgeless PFC converter and its conventional counterpart are presented in Figure 7. From this figure, it can be found that the total conduction losses of semiconductors in the proposed bridgeless PFC converter is much lower than its conventional bridge counterpart. The conduction losses of power switches in the proposed bridgeless PFC converter are higher, while it has no conduction losses of input rectifier diodes.

The Control Principle
This proposed bridgeless PFC converter is designed in DCM. The DCM possesses the merit of a naturally current-sharping ability, which contributes to a simple control method. Thereby, the voltage control loop is applied in order to obtain the constant DC output voltage. The control principle is displayed in Figure 8. From this figure, the controller mainly contains one compensator, one PWM generator and four drivers. It should be noted that the four power switches in the proposed bridgeless PFC converter can be driven by one same control signal, which simplifies the controller, significantly. Notably, the signal Vg1, Vg2, Vg3 and Vg4 drive the power switches S1, S2, S3 and S4, respectively.

The Control Principle
This proposed bridgeless PFC converter is designed in DCM. The DCM possesses the merit of a naturally current-sharping ability, which contributes to a simple control method. Thereby, the voltage control loop is applied in order to obtain the constant DC output voltage. The control principle is displayed in Figure 8. From this figure, the controller mainly contains one compensator, one PWM generator and four drivers. It should be noted that the four power switches in the proposed bridgeless PFC converter can be driven by one same control signal, which simplifies the controller, significantly. Notably, the signal V g1 , V g2 , V g3 and V g4 drive the power switches S 1 , S 2 , S 3 and S 4 , respectively.

Simulation Results
The effectiveness of the proposed bridgeless PFC converter is validated in the SIMetrix/SIMPLIS (version 8.00, company SIMetrix Technologies Ltd, UK) environment. The simulation program with integrated circuit emphasis (SPICE) models of practical components are employed in this simulation.
The key operation parameters of the proposed bridgeless PFC converter is vin = universal line 95-265 Vrms, vo = 800 V, fs = 30 kHz and Po = 500 W. The selected components are shown in Table 2. Considering the voltage stress, current stress and safety margin, the SPP17N80C3 (company Infineon, GER) with Ron = 0.29 Ω and VDS = 800 V is chosen as the power switches. The MUR490 (company On Semiconductor, USA) with VF = 1.85 V and VD = 900 V is chosen as the fast-recovery diodes in the proposed bridgeless PFC converter. Since the voltage stress of the fast-recovery diode in the conventional bridge counterpart is up to around 1200 V, which is much larger than the voltage stress 800 V of the fast-recovery diode in the proposed bridgeless PFC converter, we have to choose two series MUR490 as the fast-recovery diode in the conventional bridge counterpart. In the conventional bridge converter, 8EWS08 (company International Rectifier, USA) with VF = 1 V is used as the input rectifier diodes. The input current after the input LC filter at the typical input line is displayed in Figure 9. From this figure, the input current is shaped to be almost sinusoidal at the typical low line 110 Vrms and the typical high line 220 Vrms. Thereby, it is validated that the proposed bridgeless PFC converter owns a good current-shaping ability. Figure 10 presents the key time-domain waveforms of the proposed bridgeless PFC converter. It can be figure out that the simulated waveforms are in agreement with the theoretical analysis. The key waveforms also validate that the proposed bridgeless PFC converter operates in DCM. Figure 11 presents the simulated PF and THD under the universal line. From this figure, one can see that nearly unity PF is achieved and the THD is low under the universal line. The high PF and low THD validate that the proposed bridgeless PFC converter owns a good PFC performance.
The simulated efficiency of the proposed bridgeless PFC converter and its conventional bridge counterpart under the universal line is shown in Figure 12. From this figure, it is clear that the efficiency of the proposed bridgeless PFC converter is higher than its conventional bridge counterpart, due to the reduced semiconductors and the reduced current. Also, the efficiency of other state of the art high step-up voltage gain converter in [12] is simulated. Under the same operation parameters and components, the efficiency of the converter in [12] is 97.42% at the typical line Vin = 220 Vrms, while the efficiency of the proposed bridgeless PFC converter can reach up to 98.78% at the typical line Vin = 220 Vrms. Therefore, the proposed bridgeless PFC converter is more suitable for the practical application.

Simulation Results
The effectiveness of the proposed bridgeless PFC converter is validated in the SIMetrix/SIMPLIS (version 8.00, company SIMetrix Technologies Ltd., Thatcham, UK) environment. The simulation program with integrated circuit emphasis (SPICE) models of practical components are employed in this simulation. The key operation parameters of the proposed bridgeless PFC converter is v in = universal line 95-265 V rms , v o = 800 V, f s = 30 kHz and P o = 500 W. The selected components are shown in Table 2. Considering the voltage stress, current stress and safety margin, the SPP17N80C3 (company Infineon, GER) with R on = 0.29 Ω and V DS = 800 V is chosen as the power switches. The MUR490 (company On Semiconductor, Phoenix, AZ, USA) with V F = 1.85 V and V D = 900 V is chosen as the fast-recovery diodes in the proposed bridgeless PFC converter. Since the voltage stress of the fast-recovery diode in the conventional bridge counterpart is up to around 1200 V, which is much larger than the voltage stress 800 V of the fast-recovery diode in the proposed bridgeless PFC converter, we have to choose two series MUR490 as the fast-recovery diode in the conventional bridge counterpart. In the conventional bridge converter, 8EWS08 (company International Rectifier, El Segundo, CA, USA) with V F = 1 V is used as the input rectifier diodes. The input current after the input LC filter at the typical input line is displayed in Figure 9. From this figure, the input current is shaped to be almost sinusoidal at the typical low line 110 V rms and the typical high line 220 V rms . Thereby, it is validated that the proposed bridgeless PFC converter owns a good current-shaping ability. Figure 10 presents the key time-domain waveforms of the proposed bridgeless PFC converter. It can be figure out that the simulated waveforms are in agreement with the theoretical analysis. The key waveforms also validate that the proposed bridgeless PFC converter operates in DCM. Figure 11 presents the simulated PF and THD under the universal line. From this figure, one can see that nearly unity PF is achieved and the THD is low under the universal line. The high PF and low THD validate that the proposed bridgeless PFC converter owns a good PFC performance.
The simulated efficiency of the proposed bridgeless PFC converter and its conventional bridge counterpart under the universal line is shown in Figure 12. From this figure, it is clear that the efficiency of the proposed bridgeless PFC converter is higher than its conventional bridge counterpart, due to the reduced semiconductors and the reduced current. Also, the efficiency of other state of the art high step-up voltage gain converter in [12] is simulated. Under the same operation parameters and components, the efficiency of the converter in [12] is 97.42% at the typical line V in = 220 V rms , while the efficiency of the proposed bridgeless PFC converter can reach up to 98.78% at the typical line V in = 220 V rms . Therefore, the proposed bridgeless PFC converter is more suitable for the practical application. Figure 13 displays the simulated input current harmonics compared with the IEC 61000-3-2 class D limits. From this figure, the input current harmonics of the proposed bridgeless PFC converter are much lower than the IEC 61000-3-2 class D limits under both the typical low line and high line. Namely, the proposed bridgeless PFC converter can easily satisfy the international harmonic standards, which is very beneficial to practical application.
Energies 2018, 11, 2640 10 of 14 Figure 13 displays the simulated input current harmonics compared with the IEC 61000-3-2 class D limits. From this figure, the input current harmonics of the proposed bridgeless PFC converter are much lower than the IEC 61000-3-2 class D limits under both the typical low line and high line. Namely, the proposed bridgeless PFC converter can easily satisfy the international harmonic standards, which is very beneficial to practical application.

Conclusions
A new bridgeless high step-up voltage gain PFC converter with low conduction losses and low voltage stresses for high voltage applications is proposed, analyzed and verified in this paper. The theoretical analysis and design consideration in DCM are presented. The simulated results validate that the proposed bridgeless PFC converter has a higher efficiency than its conventional bridge counterpart. Moreover, the proposed bridgeless PFC converter can achieve a very high PF and low THD, and it can easily satisfy the IEC 61000-3-2 class D limits, thereby, the proposed bridgeless PFC converter is a competitive option for the high voltage applications.

Conflicts of Interest:
The authors declare no conflict of interest. Figure 13. The simulated input current harmonics of the proposed bridgeless high step-up voltage gain PFC converter compared with the IEC 61000-3-2 class D limits: (a) v in = 110 V rms ; (b) v in = 220 V rms .

Conclusions
A new bridgeless high step-up voltage gain PFC converter with low conduction losses and low voltage stresses for high voltage applications is proposed, analyzed and verified in this paper. The theoretical analysis and design consideration in DCM are presented. The simulated results validate that the proposed bridgeless PFC converter has a higher efficiency than its conventional bridge counterpart. Moreover, the proposed bridgeless PFC converter can achieve a very high PF and low THD, and it can easily satisfy the IEC 61000-3-2 class D limits, thereby, the proposed bridgeless PFC converter is a competitive option for the high voltage applications.