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A Fast Approach for Generating Efficient Parsers on FPGAs

College of Computer, National University of Defense Technology, Changsha 410073, China
School of Computer Science and Engineering, Nanyang Technological University, Singapore 639798, Singapore
Author to whom correspondence should be addressed.
Symmetry 2019, 11(10), 1265;
Received: 9 September 2019 / Revised: 24 September 2019 / Accepted: 3 October 2019 / Published: 10 October 2019
The development of modern networking requires that high-performance network processors be designed quickly and efficiently to support new protocols. As a very important part of the processor, the parser parses the headers of the packets—this is the precondition for further processing and finally forwarding these packets. This paper presents a framework designed to transform P4 programs to VHDL and to generate parsers on Field Programmable Gate Arrays (FPGAs). The framework includes a pipeline-based hardware architecture and a back-end compiler. The hardware architecture comprises many components with varying functionality, each of which has its own optimized VHDL template. By using the output of a standard frontend P4 compiler, our proposed compiler extracts the parameters and relationships from within the used components, which can then be mapped to corresponding templates by configuring, optimizing, and instantiating them. Finally, these templates are connected to output VHDL code. When a prototype of this framework is implemented and evaluated, the results demonstrate that the throughputs of the generated parsers achieve nearly 320 Gbps at a clock rate of around 300 MHz. Compared with state-of-the-art solutions, our proposed parsers achieve an average of twice the throughput when similar amounts of resources are being used. View Full-Text
Keywords: packet parser; pipeline; P4; FPGA packet parser; pipeline; P4; FPGA
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Cao, Z.; Zhang, H.; Li, J.; Wen, M.; Zhang, C. A Fast Approach for Generating Efficient Parsers on FPGAs. Symmetry 2019, 11, 1265.

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