Negative Capacitance Effect at Interface Between Si Wafers with Undulating Surfaces

Abstract

The field emission current in a vacuum ($I_T=\alpha E^2/e^{\beta /E}$, where $\mathsf{\alpha }$ and $\beta$ are constants) depends on the electric field strength E. In other words, the differential resistance ${(d{I}_T/dV)}^{-1}$ in a vacuum does not follow Ohm’s law. Therefore, the relationship governing the capacitance and current between two electrodes in a vacuum is an intriguing research topic. In this study, we constructed an interface structure in which contact areas and non-contact vacuum areas coexisted by adhering two Si wafers and measuring the capacitance characteristics of this structure. A volatile capacitance appeared at the interface, with the contact areas contributing to positive capacitance and the vacuum areas contributing to negative capacitance. The tunneling current passing through the interface played an important role in the formation of the negative capacitance.

1. Introduction

Recently, research concerning negative capacitance has attracted considerable interest [1,2,3,4,5,6]. In these studies, the negative capacitance is related to the physical properties of the dielectric material between the electrodes. This type of negative capacitance has been observed in only a limited number of materials, such as Zr_0.5Hf_0.5O₂, and typically exhibits a low capacitance value. Moreover, integrating this phenomenon into silicon-based materials commonly used in electronic devices remains a significant challenge [1,7,8]. Unlike the negative capacitance due to material properties, our research group proposed a two-resistor structure model and generated negative capacitance by controlling the tunneling current across the interface of the two-resistor structure [9]. Ohm’s law does not apply to the tunneling current, which behaves as a field emission current in relation to the potential difference across the two resistors. In other words, the differential conductance $d{I}_T/dV$ is not constant. As a result, the amount of free charge accumulated on the electrodes varies with changes in current and voltage, indicating that this two-resistor structure exhibits volatile capacitance. When the charge decreases with increasing voltage, the volatile capacitance becomes negative. Conversely, when the charge increases, the capacitance becomes positive. Since these are free charges, they dissipate through conductive pathways once the circuit power is turned off, causing the capacitance to vanish [9].

The equivalent circuit of a resistor $R$ with two parallel-plate electrodes consists of the parallel circuit of $R$ and the capacitor $C$. The capacitance $C$ varies depending on the value of resistance $R$. If $R$ is infinite, the capacitance $C$ is determined by the dielectric constant of the insulator $R$. Moreover, when $R$ depends on the potential difference $V$ across the resistor—that is, when $dR/dV\ne 0$—the relationship between the electrode charge $Q$ and $V$ does not follow Ohm’s proportional relationship. As $Q$ leaks through the resistor $R$, the capacitance becomes volatile. Our theoretical study revealed that the volatile capacitance $C$ is determined by the correlation between the differential current $dV/dR$ and the Ohmic current $V/R$. The conclusions are that when $dV/dR>V/R$, $C<0$; when $dV/dR=V/R$, $C=0$; and when $dV/dR<V/R$, $C>0$ [9]. Furthermore, our experiments confirmed the transition between positive and negative capacitance in the interface structure of a multi-walled carbon nanotube resistor and vacuum, and the results obtained were consistent with theoretical predictions [9].

In this study, we investigated the volatile capacitance characteristics of a two-resistor structure constructed using Si crystals. Valuable results were obtained regarding the role of the tunneling current in the capacitance characteristics.

2. Experimental

The p-type Si (100) wafers of thickness 520 μm and resistivity 10 Ω·cm have undulations on one side. Figure 1a,b show an SEM image of the surface and a cross-sectional schematic diagram of the undulating Si wafer, respectively. Figure 1c shows the pattern of the contact area between the undulating wafers, and Figure 1d shows the pattern of the contact area between the undulating wafer and the untreated wafer. As shown in Figure 1a,b, the cross section was an equilateral triangle with a 4 μm distance between vertices. An aluminum thin film of thickness 100 nm was fabricated on one side of the Si wafer to form Ohmic contact, as shown in Figure 1b. The undulating surfaces of the two wafers faced each other, set at 90° in the γ direction, to form sample A with point contact, as shown in Figure 1c. The contact points were assumed to be circular with a diameter of ${\Phi }_a$. Additionally, sample B with line contact, as shown in Figure 1d, was formed by facing an undulating and a non-undulating wafer. The contact line width was assumed to be $l_a$. Samples A and B were square with a side length of 3 mm. A conceptual diagram of the two-resistor structure is shown in Figure 2. The average distance between the two resistors is denoted by $d$. The surface roughness of the silicon wafers was evaluated using a 3D scanning electron microscope (ELIONIX Inc. ERA-8800, Tokyo, Japan), revealing an average roughness of 0.20 μm. It was confirmed that the undulation treatment significantly increased the roughness of the wafers. The current $I$ passing through the interface is the sum of the conduction current $I_E$ and the polarization current $I_P$ through the contact areas and the tunneling current $I_T$ through the non-contact vacuum areas. This interface, composed of contact and non-contact areas, formed the core of the negative capacitor structure. Based on the average separation distance $d$ and the potential difference between the two resistors, the interfacial electric field strength was determined to exceed 6.25 V/μm. The field emission threshold of p-type Si micro-tip arrays is 4.0–5.0 V/μm [10,11]. Therefore, it is feasible to generate a tunneling current passing through the interface of a two-Si wafer structure.

Samples A and B were placed in a vacuum chamber with a base vacuum of $2.0\times {10}^{-5}\mathrm{P}\mathrm{a}$, and their electrical characteristics were measured with an impedance analyzer (HIOKI, IM3570, Nagano, Japan) while varying the distance $d$, DC bias, and AC amplitude. To overcome the difficulty of controlling the distance $d$, it was adjusted using screws. The screw was rotated approximately 2° to change the distance $d$. Due to the presence of contact areas between the wafers caused solely by gravity, accurately measuring the average separation distance d was challenging. Additionally, tightening the screws altered the roughness of the surface, making it difficult to reproduce consistent measurement values. Therefore, we chose to keep the screws tightened throughout the experiment without loosening them. In addition, a constant-current source was employed during the measurements in this study.

3. Results and Discussion

The frequency dependence of the capacitance for samples A and B at various $d$ is shown in Figure 3a,b, respectively. The color bar in the figure represents the number of measurements taken. For sample A, in the frequency range below ${10}^3\mathrm{H}\mathrm{z}$, the capacitance changed from negative to positive and then back to negative with decreasing $d$, in the order of ${10}^{-8}\mathrm{F}$. In the frequency range above ${10}^3\mathrm{H}\mathrm{z}$, the capacitance remained almost constant at $3.5\times {10}^{-10}\mathrm{F}$ at 1 MHz.

For sample B, negative capacitance appeared in the frequency range below ${10}^2\mathrm{H}\mathrm{z}$, increasing to positive with decreasing $d$, up to the order of ${10}^{-8}\mathrm{F}$. Above ${10}^2\mathrm{H}\mathrm{z}$, the capacitance remained almost constant at $2.5\times {10}^{-10}\mathrm{F}$ at 1 MHz. These results suggest that the process of the two resistors approaching one another could be divided into two stages. In the first stage, with zero contact area between the two resistors, a tunneling current can occur if the resistors become sufficiently close. The initial negative capacitance with decreasing $d$ can be attributed to the tunneling current. In the second stage, contact occurs between the two resistors, generating conduction and polarization currents in addition to the tunneling current, forming a positive capacitance component. A further reduction in the distance $d$ between the two resistors changes the contact area and the proportion of tunneling current. As shown in Figure 1, the contact area patterns of samples A and B are point and line, respectively. Assuming the diameter of the tunneling current point and the width of the tunneling current line to be ${\Phi }_b$ and $l_{\mathrm{b}}$, respectively, the area ratio of the tunneling current can be estimated. For sample A, the ratio is ${\alpha }_A=S_T/S_{E+P}=\pi {\left({\Phi }_b/2\right)}^2/\pi {({\Phi }_a/2)}^2={({\Phi }_b/{\Phi }_a)}^2$. For sample B, the ratio is ${\alpha }_B=s_t/s_{e+p}=l_b/l_a$. Assuming that ${\Phi }_a=l_a$ and ${\Phi }_b=l_b$, we obtain ${\alpha }_A/{\alpha }_B={({\Phi }_b/{\Phi }_a)}^2/(l_b/l_a)={\Phi }_b/{\Phi }_a$, where ${\Phi }_b>{\Phi }_a$. In consideration of the resistance of the conduction and polarization currents, the proportion of tunneling current in sample A was greater than that in sample B. Thus, the smaller negative capacitance in sample B can be attributed to a smaller proportion of tunneling current. Assuming $I_T$ decreases $Q$ and $I_E$ and $I_P$ increase $Q$, the condition $dV/dR<V/R$ holds in sample B with the larger contact area, resulting in positive capacitance. This explains the results observed in Figure 3.

The frequency dependence of the capacitance for samples A and B at various DC biases is shown in Figure 4a,b, respectively. Here, the AC amplitude is 2.5 V, $d$ is set to its minimum value, and the color bar indicates the DC bias. The DC bias dependence of negative capacitance was strong in sample A, which had a large proportion of tunneling current. In contrast, in sample B, where the conduction and polarization currents were dominant, there was almost no DC bias dependence of capacitance. It is understood that the DC bias does not affect the differential current of the conduction and polarization currents $(dV/dR=V/R=constant)$, but does affect the differential resistance ${(d{I}_T/dV)}^{-1}$ corresponding to the tunneling current.

The frequency dependence of the capacitance for samples A and B at various AC amplitudes is shown in Figure 5a,b, respectively. Here, the DC bias is 2.5 V, $d$ is set to its minimum value, and the color bar indicates the AC amplitude. It was confirmed that the AC signal was periodic and did not affect the charge $Q$. This resembles the behavior typically observed in dielectric capacitors [12,13].

The results indicate that negative capacitance, i.e., inductance without a coil, may be achieved. Furthermore, it was confirmed that the phase delay of the current relative to potential $V$ is related to the time constant $\tau$ of an RC circuit. The frequency dependence of the time constant $\tau =R_s{C}_s$ for samples A and B at various $d$ is shown in Figure 6a,b, respectively. Here, $R_s$ and $C_s$ represent the resistance and capacitance of the series equivalent circuit of the samples. Additionally, the straight lines in the figure indicate the half-periods of the AC signal. As can be observed by comparing Figure 3 and Figure 6, negative capacitance occurred in the low-frequency region where the half-periods of the AC signal were greater than $\tau$. In other words, the relationship $\tau >halfperiod$ must be established to form a negative capacitance. Under this condition, the tunneling current is sustained along with the AC signal. Conversely, when $\tau <halfperiod$, the duration of sustained tunneling current during the AC signal is shorter, with periods where it reaches zero. In other words, the sustained tunneling current plays a crucial role in forming negative capacitance. Furthermore, peaks in the time constant can be observed in Figure 6a,b under conditions where negative capacitance was generated. This can be attributed to the resonance between the negative capacitance (inductance) of the two-resistor structure and the positive capacitance of the Al electrodes [14,15].

Figure 7a,b present the Cole–Cole plots for samples A and B at various $d$ values, respectively, with enlarged insets on the vertical axes. Corresponding to the results of Figure 3 and Figure 6, negative capacitance was observed in both samples A and B in the low-frequency region below ${10}^3\mathrm{H}\mathrm{z}$. As the frequency increased, the imaginary part of the impedance traced a semicircular path. The absolute value of the negative capacitance decreased with increasing frequency, passing through a minimum value and eventually becoming positive capacitance. As the −$1/\omega C$ approached zero, $C$ reached its maximum value, corresponding to the peak of $\tau =R_s{C}_s$ in Figure 6a,b.

Based on these results, we now examined the characteristics of negative capacitance. Notably, negative capacitance was observed only in the low-frequency region within the two-silicon-resistor structure. At low frequencies, sufficient time was available for the charge $Q$ to respond to conduction current, polarization current, and tunneling current, which is essential for the emergence of negative capacitance.

Second, negative capacitance was influenced by the applied DC bias yet remained unaffected by variations in the AC signal amplitude. This suggests that the phenomenon is governed primarily by the steady-state electric field rather than dynamic excitation.

Third, by adjusting the spacing between the two resistors, the interface capacitance can be modulated, transitioning between positive and negative values. This tunability highlights the critical role of geometric configuration in controlling interfacial charge dynamics.

Fourth, tunneling current played a pivotal role in the emergence of negative capacitance. By facilitating charge leakage, it enabled the condition $dQ/dV<0$, which is fundamental to the manifestation of negative capacitance. This behavior underscores the importance of quantum mechanical effects in modulating interfacial charge dynamics within the two-resistor structure.

Fifth, contact resistance at the interface of the two-resistor structure contributed to the accumulation of charge $Q$, thereby enabling the condition $dQ/dV>0$, which leads to positive capacitance. This effect highlights the role of resistive interfaces in stabilizing charge buildup and promoting conventional capacitive behavior.

Finally, the capacitance of the two-resistor structure exhibited volatility. Conduction and tunneling currents diminished to zero only when the contact resistance approached infinity. Under this condition, charge accumulation driven solely by the polarization current became observable, marking a transition to a purely capacitive response. This behavior underscores the dynamic interplay between resistive and quantum transport mechanisms in determining the system’s capacitive state.

4. Conclusions

In conclusion, we fabricated an interface structure by applying angulation processing to the surface of a silicon crystal, enabling contact between two resistors. Our findings reveal that contact regions, where conduction and polarization currents dominate, contribute to positive capacitance. In contrast, non-contact regions, characterized by tunneling current flow, give rise to negative capacitance. This dual behavior underscores the spatial dependence of charge transport mechanisms within the structure. Notably, the observed negative capacitance effect holds significant potential for the development of two-dimensional inductor devices and coil-free integrated circuits, offering a promising pathway toward compact and energy-efficient electronic components.