The Atomic Layer Etching Technique with Surface Treatment Function for InAlN/GaN Heterostructure

Abstract

This paper studied an atomic layer etching (ALE) technique with a surface treatment function for InAlN/GaN heterostructures with AlN spacer layers. Various parameters were attempted, and 30 s O₂ + 15 W BCl₃ was chosen as the optimal recipe. The optimal ALE approach exhibited satisfactory etching results, with regard to the etch-stop effect, compared with other techniques. The atomic force microscopy (AFM) results showed an etching per cycle (EPC) value of 0.15 nm/cycle, with a 0.996 fit coefficient and root mean square (RMS) surface roughness of around 0.61 nm (0.71 nm for as-grown sample), which was the lowest in comparison with digital etching (0.69 nm), Cl₂/BCl₃ continuous etching (0.91 nm) and BCl₃ continuous etching (0.89 nm). X-ray photoelectron spectroscopy (XPS) and scanning transmission electron microscopy with energy dispersive X-ray spectroscopy measurements (STEM/EDS) verified the indium clustered phenomena at the bottom apex of V-pit defects in the epi structure of InAlN/GaN high electron mobility transistors (HEMTs) for the first time, in addition to the surface morphology optimization for the ALE under-etching technique used in this work. The resistor hall effect (Hall) and AFM measurements demonstrated that after 4 or 5 ALE cycles, the two-dimensional electron gas (2-DEG) density and RMS roughness were improved by 15% and 11.4%, respectively, while the sheet resistance (R_sh) was reduced by 6.7%, suggesting a good surface treatment function. These findings were important for realizing high-performance InAlN/GaN HEMTs.

1. Introduction

InAlN/GaN-based high electron mobility transistors (HEMTs) have recently attracted much attention. Compared to the commonly used AlGaN/GaN heterostructure, the stronger spontaneous polarization effect of the InAlN/GaN heterostructure provides higher two-dimensional electron gas (2-DEG) density, leading to lower on-resistance (R_on) and a higher output current. Moreover, the lattice-matched In_0.17Al_0.83N/GaN heterostructure could also enhance device reliability. At the same time, enough 2-DEG density of InAlN/GaN contributes to a thinner barrier layer thickness, improving the radio frequency (RF) characteristics by reducing the short-channel effects of a deeply scaled device [1,2,3,4,5]. Owing to the advantages mentioned above, the InAlN/GaN heterostructure is considered as the most competitive candidate for GaN-based power and RF devices [6].

The etching technique is critical in GaN-based device fabrication, including the gate recess process, source/drain ohmic contact with a low annealing temperature, and regrown ohmic contact preparation. To relieve the serious etching damage and the resulting device reliability issues, an etching technique with a precisely controlled etching depth and low surface damage is urgently needed. In recent years, atomic layer etching (ALE) with two sequential quasi-self-limiting steps (O₂ plasma modification step and BCl₃ plasma removal step) has been used in the fabrication of AlGaN/GaN HEMTs, to obtain a well-controlled recess process and leakage current suppression, becoming a potential alternative to continuous dry etching and digital etching techniques [7,8,9,10,11,12,13,14,15,16]. However, little work has been reported on the study of ALE for the InAlN/GaN heterostructure. In our previous report, the O₂/BCl₃-based ALE technique for InAlN/GaN was proposed with good etching results [17]. However, systematic comparative studies among ALE, continuous dry etching, and digital etching techniques are still absent.

O₂-based plasma treatment applied to InAlN/GaN HEMTs is an efficient surface treatment method for optimizing the output performance and leakage current of a device [2,18,19,20,21]. In 2011, Wang et al. reported, after 2 min of O₂/Ar plasma treatment for the access region of the InAlN/GaN HEMTs, a high output current (2.1 A/mm) and low gate leakage (1 mA/mm), due to improvements in the electrical properties and trap state passivation. The electrical property optimizations of 2-DEG density and sheet resistance (R_sh) were similar to the AlGaN/GaN heterostructure passivated by SiN [18]. Moreover, in 2011, Lee et al. reduced the gate leakage of InAlN/GaN HEMTs by more than two orders of magnitude by using O₂ plasma inductively coupled plasma (ICP) Asher treatment on the InAlN surface after ohmic preparation, which was similar to the results in the AlGaN device [19]. In 2016, using 5 min of O₂ reactive ion etching (RIE) plasma treatment before gate metallization, Ma et al. fabricated InAlN/GaN HEMT with an output current of 2.18 A/mm and gate leakage of 10⁻² mA/mm, which resulted in defect suppression and barrier height increase [2]. In 2021, with 1 min of O₂ RIE plasma treatment prior to gate deposition by Asher, Cui et al. realized an InAlN/GaN HEMT with a high I_on/I_off ratio of ~10⁷ and low surface leakage [21]. A thin In₂O₃ and Al₂O₃ mixed oxide layer on the InAlN surface could increase the effective barrier height of InAlN and decrease the trap density of the surface, optimizing the electrical properties (2-DEG density and R_sh) of the epitaxy, while also leading to enhancement of the device performances, such as the output current and R_on, and suppressing the gate leakage [18,22,23,24]. Therefore, the ALE technique with an O₂ modification step has potential for surface treatment functions.

In this paper, an O₂/BCl₃-based ALE technique for the InAlN/GaN heterostructure with a surface treatment function was studied. An etching per cycle (EPC) value of 0.15 nm/cycle, with a fit (R²) coefficient of 0.996, was obtained. The InAlN surface root mean square (RMS) roughness after the ALE (0.61 nm) process was lower than the samples obtained using digital etching (0.69 nm), Cl₂/BCl₃ (0.91 nm) etching, and BCl₃ (0.89 nm) etching techniques. Four or five cycles of ALE surface treatment on an as-grown InAlN wafer resulted in the 2-DEG density improving by 15%, R_sh reducing by 6.7%, and surface RMS roughness optimizing by 11.4%. The mechanism was systematically investigated by the following measurements: atomic force microscopy (AFM), resistor Hall effect (Hall) measurement, X-ray photoelectron spectroscopy (XPS), and scanning transmission electron microscopy (STEM) with energy dispersive X-ray spectroscopy (EDS).

2. Experimental

Sample preparation: The 6″ In_0.17Al_0.83N/GaN wafer was grown on high-resistivity Si substrate for device fabrication, which was purchased from NTT AT Corporation. As shown in Figure 1a, a 10.6 nm In_0.17Al_0.83N barrier layer and a 1 nm AlN spacer layer were grown on a 1000 nm i-GaN channel layer to form the 2-DEG characterization. Figure 1b and c show the STEM image of the InAlN wafer. The 6″ wafer was diced into 2 × 2 cm² and 1 × 1 cm² samples. The former were used for etching experiments with AFM measurement, and the latter were used for XPS, STEM/EDS measurements and surface treatment experiments with AFM and Hall measurements.

As shown in Figure 2(a₁), a 300 nm SiO₂ hard mask for the ALE process was deposited on 2 × 2 cm² samples by plasma-enhanced chemical vapor deposition (PECVD) at 350 °C. Photolithography was utilized for determining the desired pattern. In order to remove the SiO₂ mask selectively, SF₆ plasma ICP-RIE was performed.

Parameter settings: The O₂ plasma modification step and BCl₃ plasma removal step of the O₂/BCl₃ ALE approach are shown in Figure 2(a₂,a₃), respectively. For the modification step, the parameters were set at the following: ICP power = 100 W and RF power = 50 W, while the modification time was variable. For the removal step, the parameters were set at the following: ICP power = 0 W and RF power = 15 W, with the removal time at 30 s. These two steps were performed in sequence, alternatively, in the Corial 210IL 200 mm ICP system at a chamber pressure of 10 mTorr and gas flow rate of 50 sccm, with 30 s switching time. After the whole etching process, the SiO₂ hard mask was removed by buffered oxide etch (BOE), as shown in Figure 2(a₄)_.

The EPC and surface roughness were measured for samples with various O₂ modification times to determine the optimal parameters for the ALE technique. In Figure 3a, as the modification time increased, EPC firstly increased and then tended to saturate, while the RMS roughness firstly reduced and then stabilized gradually. Given the production efficiency, an O₂ modification time of 30 s was determined for the ALE recipe. Figure 3b demonstrates the initial calibration of this ALE technique with optimal parameters (30 s O₂ modification time), and good repeatability of single atomic-level EPC (0.15 nm/cycle) was confirmed by R² = 0.996 and low dispersion.

Three representative etching techniques were used as the control groups for the ALE technique. For the digital etching technique, the process combined O₂ plasma oxidation followed by the oxidation layer being removed using diluted HCl solution, as shown in Figure 2(b₁–b₄). For the Cl₂/BCl₃ and BCl₃ continuous etching techniques shown in Figure 2(c₁–c₃), the RF/ICP power was set at 15/100 W and 15/0 W, respectively. Thus, five samples were prepared accordingly: as-grown (sample 0, S₀), ALE (sample 1, S₁), digital etching (sample 2, S₂), Cl₂/BCl₃ continuous etching (sample 3, S₃), and BCl₃ continuous etching (sample 4, S₄).

Characterization: The surface roughness was measured immediately after etching, and then after removing the SiO₂ mask, the etching depth was measured by AFM. XPS measurements were performed to investigate the ALE mechanism. Moreover, the as-grown epi wafer was measured by STEM/EDS to verify the epitaxy characteristics of the InAlN/GaN heterostructure. To explore the effect of ALE surface treatment, Ti/Al/Ti/Au (20/110/40/50 nm) metal electrodes were deposited at four corners of the samples after variable cycles of ALE surface treatment, and 45 s of 860 °C N₂ rapid thermal annealing (RTA) was used to reduce the contact resistance for Hall measurements.

3. Results and Discussion

The etching depth vs. etching cycles for samples S_1–2 and the etching depth vs. etching time for samples S_3–4 are shown in Figure 4, while the corresponding EPCs (nm/cycle) or etching rates (nm/min) for the InAlN, AlN and GaN layers are listed in

Table 1. The EPC and etching rate of the InAlN, AlN and GaN layers for samples S_1–4.

Etching Method	InAlN Etching Rate	AlN Etching Rate	GaN Etching Rate
Sample S1	0.15 nm/cycle (EPC)	0.03 nm/cycle (EPC)	0.46 nm/cycle (EPC)
Sample S2	7.46 nm/cycle (EPC)	-1	-1
Sample S3	17.88 nm/min	-1	-1
Sample S4	0.28 nm/min	-1	0.32 nm/min

¹ Due to the fact that these samples will be directly etched through the InAlN/GaN layer, the partial etching rate could not be calculated for samples S_2–4.

. The EPCs of the InAlN, AlN and GaN layers for sample S₁ were 0.15, 0.03 and 0.46 nm/cycle, respectively. An obvious etch-stop phenomenon was observed during the ALE process, as shown in Figure 4a, which could be explained by the efficient blocking function of the AlN layer with poor oxidation properties [17,25]. For sample S₂ in Figure 4b, the EPC of the InAlN layer was up to 7.46 nm/cycle, and the InAlN layer could be over etched by only two cycles of digital etching. Although the EPC of sample S₂ decreased around the AlN layer, no etch-stop effect was observed, as opposed to AlGaN/GaN. This suggests that only the ALE technique can provide an etch-stop effect on the InAlN/GaN heterostructure, further explained below by the STEM image of the InAlN/GaN heterojunction. As shown in Figure 4c,d, due to the existence of Cl₂ plasma, the etching rate of sample S₃ (17.88 nm/min) was much bigger than that of sample S₄ (0.28 nm/min). Nevertheless, both these continuous etching techniques consisted of linear etching processes during the whole InAlN/GaN etching process. With the stable InAlN EPC shown in Figure 3b and etch-stop effect at the AlN layer, the ALE technique of sample S₁ was confirmed as the most effective way for controlling the InAlN/GaN etching depth precisely, compared to the other three etching techniques.

Figure 5a−f show the surface morphology for the as-grown InAlN surface of sample S₀, InAlN etched surface of sample S_1–4, and AlN etched surface of sample S₁. All the InAlN etched surface morphologies were obtained at an etching depth of approximately 9 nm, while the AlN etched surface morphology of sample S₁ was measured at an etching depth of around 11.5 nm, which is in the AlN layer. The corresponding RMS and mean roughness are listed in

Table 2. The surface roughness for InAlN surface of samples S_0–4 and AlN etched surface of sample S₁.

Etching Method	RMS Roughness (nm)	Mean Roughness (nm)
Sample S0	0.71	0.47
Sample S1	0.61	0.44
Sample S2	0.69	0.47
Sample S3	0.91	0.75
Sample S4	0.89	0.66
Sample S1_AlN	0.60	0.45

. For sample S₁, the InAlN and AlN etched surfaces after the ALE process showed similar RMS roughness values (0.61 nm and 0.60 nm), which were even lower than that of sample S₀ (0.71 nm). Compared to sample S₂ (0.69 nm), obtained using the digital etching technique, sample S₁ had lower roughness and dispersion (as shown in Figure 5g,h), further demonstrating that the ALE technique with quasi-self-limiting characteristics is more stable in controlling the surface morphology. Compared to samples S₃ (0.91 nm) and S₄ (0.89 nm), the ALE technique provided a much smoother surface by effectively overcoming the continuous etching limitations, such as transport-limited phenomena, highly coupled parameters, and propagation of the damaged etch front, which could be beneficial to decrease the interface trap density and device leakage current [7,12]. The ALE technique was the most effective way to control the InAlN/GaN etching surface morphology.

To systematically explore the mechanism of the ALE technique, XPS measurements of Al and In oxides were performed on an InAlN/GaN wafer for one cycle of ALE, as shown in Figure 6. For the Al element in Figure 6a, after one O₂ modification step of sample S₁, the Al₂O₃ content increased significantly compared to sample S₀, whereas a substantially reduced Al₂O₃ content was observed after the following BCl₃ etching of sample S₁. The In₂O₃ content shown in Figure 6b had the same change as Al₂O₃. These results indicate the oxidation function of the ALE modification step and the effective etching of the ALE removal step. Moreover, the Al₂O₃ and In₂O₃ contents after one ALE cycle of sample S₁ were more than the as-grown sample S₀. This implies that the ALE technique used in this work was an under-etching approach, which did not completely remove the oxides formed by the O₂ modification step.

For the first time, Figure 7a shows the STEM image of an epi structure of InAlN/GaN HEMTs with V-pit defects penetrating through the whole InAlN barrier layer. V-pits are usually generated on the dislocations of bottom GaN, leading to poor surface morphology (as shown in Figure 5) of the InAlN epilayer, and were hardly observed in the AlGaN/GaN heterojunction [26,27]. Figure 7c,d show the EDS results of the indium (In) atomic fraction for the InAlN/GaN heterostructure at the V-pit position (line-1) and general position (line-2) (Figure 7b). The In element was observed in the AlN/GaN region below the V-pits and was absent in the general position, verifying the In clustered phenomenon was the origin of V-pit defects [28,29]. The In elements involvement made the AlN more easily oxidized, due to the lower binding energy of In-O, and the large number of V-pits provided excessive oxidation paths of AlN in the digital etching technique, leading to loss of the etch-stop effect. The ALE technique with only 30 s of oxidation could effectively avoid this problem, which was well matched with the results shown in Figure 4a,b. Furthermore, the observed In clustered phenomenon at the V-pit apex could demonstrate why the under-etching ALE technique (oxide residue after etching) achieved better surface morphology than the over-etching ALE technique (no oxide residue after etching) in our previous work [17].

The surface treatment function of the ALE process for an InAlN/GaN heterostructure was also investigated. In Figure 8 and

Table 3. The 5 × 5 μm² RMS roughness and electrical properties of samples with 0–5 cycles of ALE surface treatment followed by RTA.

Surface Treatment Method	RMS Roughness (nm)	Rsh (Ω/sq)	2-DEG Mobility (cm2·V−1·s)	2-DEG Density (×1013 cm−2)
Sample S0	0.44	386	1210	1.33
1 cycle sample S1	0.56	454	954	1.44
2 cycles sample S1	0.47	440	1000	1.41
3 cycles sample S1	0.45	401	1030	1.51
4 cycles sample S1	0.39	360	1150	1.50
5 cycles sample S1	0.40	363	1120	1.53

, the electrical properties, including the R_sh, 2-DEG mobility and density, of the as-grown sample S₀ and sample S₁ with 1–5 cycles of ALE surface treatment are demonstrated. The R_sh increased to 454 Ω/sq for one cycle of treatment, which was above the as-grown R_sh (386 Ω/sq), and then decreased steadily from 454 Ω/sq to around 360 Ω/sq from one cycle to five cycles of treatment, while the 2-DEG mobility exhibited an almost opposite trend to R_sh, and finally recovered close to the as-grown 2-DEG mobility (1210 cm²·V⁻¹·s) for treatment of 1–5 cycles. These trends are closely related to the interface scattering changes represented by the surface morphology roughness shown in Table 3. The increasement in RMS roughness enhanced the interface scattering, thus causing R_sh and 2-DEG mobility to worsen, and vice versa. However, the 2-DEG density continuously increased from 1.33 × 10¹³ cm⁻² to 1.53 × 10¹³ cm⁻² for 1–5 cycles of ALE surface treatment with only 0.75 nm InAlN etch amount. Since the ALE technique in this work was an under-etching approach, it would gradually generate a thin oxide layer with a high O content for 1–5 cycles of treatment, similarly to O₂-based plasma surface treatment, which could reduce the surface barrier height of the nitrides and increase the effective barrier height, thereby subsequently increasing the 2-DEG density [18,22]. Thus, compared to sample S₀, sample S₁ with four or five cycles of ALE surface treatment could reduce R_sh by 6.7% and increase the 2-DEG density by 15%, which was comparable to the optimization ability of the reported O₂ plasma surface treatment and other treatment approaches [18,30,31]. In addition, lower RMS roughness of 0.39 nm was obtained after four or five cycles of treatment, compared to sample S₀ (0.44 nm). This demonstrates that the ALE technique had an efficient surface treatment function to make InAlN/GaN HEMTs reduce R_on, gate leakage and increase output current density.

4. Conclusions

In summary, this paper demonstrates an ALE technique with a surface treatment function for InAlN/GaN heterostructures. This ALE technique obtained well-controlled EPC (0.15 nm/cycle) and improved the surface RMS roughness (0.61 nm), which was much lower than that of the as-grown sample (0.71 nm), digital etching (0.69 nm), Cl₂/BCl₃ etching (0.91 nm) and BCl₃ etching techniques (0.89 nm). The XPS and STEM/EDS results confirmed the In clustered phenomenon below the V-pit defects, which was related to the surface morphology optimization of the under-etching ALE technology used in this work. Hall and AFM measurements verified the effective ALE surface treatment function on the InAlN/GaN heterostructure. A maximum reduction of 6.7% in R_sh and a maximum increasement of 15% in 2-DEG density, with surface roughness optimization of 11.4%, were obtained after four or five cycles of treatment. This enabled high-performance InAlN/GaN HEMTs designs to be obtained.