Channel Mobility Model of Nano-Node MOSFETs Incorporating Drain-and-Gate Electric Fields

Abstract

A novel channel mobility model with two-dimensional (2D) aspect is presented covering the effects of source/drain voltage (V_DS) and gate voltage (V_GS), and incorporating the drift and diffusion current on the surface channel at the nano-node level, at the 28-nm node. The effect of the diffusion current is satisfactory to describe the behavior of the drive current in nano-node MOSFETs under the operations of two-dimensional electrical fields. This breakthrough in the model’s establishment opens up the integrity of long-and-short channel devices. By introducing the variables V_DS and V_GS, the mixed drift and diffusion current model effectively and meaningfully demonstrates the drive current of MOSFETs under the operation of horizontal, vertical, or 2D electrical fields. When comparing the simulated and experimental consequences, the electrical performance is impressive. The error between the simulation and experiment is less than 0.3%, better than the empirical adjustment required to issue a set of drive current models.

1. Introduction

In conventional device models for metal-oxide-semiconductor field-effect transistors (MOSFETs), the drive current (ON current) [1,2] mainly considers the moving carriers with the drift effect, as shown in Figure 1a. Due to this simple assumption, the pseudo-ideal device models can easily and quickly be assigned to the design houses. For the long-channel devices, this strategy is commercially acceptable. As the channel length of a MOSFET decreases, the saturation current of MOSFETs increases with the increase in the drain voltage or decrease in the channel length, which is known as channel length modulation [3,4,5] or velocity overshoot [6,7,8,9]. However, the proposed conduction mechanisms do not seem to entirely fit the physically measured current-voltage results. The device models in semiconductor foundries usually assist in making an empirical adjustment to compensate for this drawback, but have no physical meaning. Previously, a new concept incorporating the diffusion effect at each channel point was proposed due to the gradient of inversion charge density, especially near the pinch-off point [10]. At this pinch-off point, the inversion charge density approaches zero, indicating zero drift current, but the real drive current is not zero.

As a result, the drive current rises as the drain voltage increases for a nano-scale MOSFET. Adding the diffusion effect to the drive current model, the contribution of the diffusion current to the entire drive current is distinctly enhanced, especially in the current behavior of short-channel devices [11,12]. In other words, a larger source/drain voltage V_DS will make a larger gradient of inversion charge density, causing a larger surface diffusion current. However, as the V_GS was fixed, the previous work [11] only changed one parameter (V_DS), in long- or short-channel devices, to fit the equivalent mobility μ_eq accurately. The previous work treated it as a one-dimensional (1D) issue. In terms of the real operation of MOSFETs, the electrical field with gate bias V_GS still and strongly influences the channel mobility dominating the drive current. Thus, it is necessary to give this deeper consideration, modulating all the parameters (V_DS, V_GS, and L_mask) at once to fully satisfy the μ_eq correlated to the V_DS, V_GS, and channel length on drawn mask L_mask. Moreover, by consolidating the adjustment of V_DS and L_mask correlated to the horizontal electric field and V_GS influencing the vertical electric field, the drive current of MOSFETs can be more meaningful and beneficial in providing a set of accurate nano-node device models, especially beyond 28-nm node fabrication or entering 3-nm node processes [13,14,15,16]. The gate bias, which conducts the moving carriers in the channel, induces more carrier scattering, especially in surface roughness. This paper presents a 2D investigation, as shown in Figure 1b.

Furthermore, the dielectric gate in this work was a sandwich stack of high-k (HK) materials HfO_x/ZrO_y/HfO_z [17,18,19,20] deposited with atomic layer deposition (ALD) technology [21,22,23]. The physical thickness deposited with ALD technology was about 2.4 nm. The gate electrode was made of low-resistance aluminum, also called a metal gate (MG) [24,25], as shown in Figure 2, where L_Gate is the real gate length on the wafer. ΔL_E is the error of L_mask and L_Gate. L_OL is the overlap difference of L_Gate and the end of the n⁻ doping region at the source site. L_met and L_Dep are the distances between both n⁻ regions and the depletion width due to the V_DS bias. L_Real equivalent to (L_met − L_Dep) is the really effective inversion channel length. The orders of p-well, n⁻, and n⁺ in doping levels with unit 1/cm² are 13, 14, and 15, respectively. The physical extraction and fitting metrology of equivalent channel mobility is demonstrated in Section 2. The measurement and simulation characteristics of drive current for long-and-short channel MOSFET devices are illustrated in Section 3. The discussion of this equivalent mobility model in precision investigation and the possible extension applications beyond the 28-nm node is demonstrated in Section 4. In the end, we did a conclusion in Section 5.

2. Experimental and Mobility Fitting

Based on the previous work [11], five checking points A, B, C, D, and E, as shown in Figure 3, were utilized to expose the carrier mobility μ(x) and the drift current (see Figure 3), where μ(x) was the function of the position x in the surface channel and the range of position x was from point B to point D. However, it was not enough to describe the whole behavior of an equivalent mobility μ_eq correlated to V_DS, V_GS, and L_mask, independent of position x.

We incorporated various conditions with V_DS, V_GS, and L_mask to reasonably describe the whole drive current and fit μ_eq in Equations (1)–(6),

$$I_{\mathrm{Drift}}=W{Q}_i(x)v_d(x)$$

(1)

$$I_{\mathrm{Diff}}=D_{n}W\frac{d{Q}_i(x)}{dx}$$

(2)

$$\mathrm{where} D_n={\mu }_{eq}\frac{kT}{q}$$

(3)

$$I_{\mathrm{total}}=I_{drift}+I_{diff}$$

(4)

$$\frac{I_{\mathrm{total}}}{W}=-Q_i(x)v_d(x)+D_n\frac{d{Q}_i(x)}{dx}$$

(5)

$$\frac{I_{\mathrm{total}}}{W}=\frac{{\mu }_{eq}{E}_{ast}{Q}_i(x)\frac{d{Q}_i(x)}{dx}}{m{c}_{ox}{E}_{ast}+\frac{d{Q}_i(x)}{dx}}+D_n\frac{d{Q}_i(x)}{dx}$$

(6)

where Q_i(x) is the inversion charge at position x with unit Coulomb/cm², q is the unit charge, W is the channel width, ν_d is the carrier drift velocity, D_n is the diffusion coefficient of the electron carrier, E_sat is the horizontal electric field at saturation, k is the Boltzmann constant, T is the absolute temperature, and m is the body factor.

Under specific conditions, such as fixing a channel length and tuning the gate voltages to sense the I_DS − V_DS characteristics, the relationship between μ_eq and the drain bias can be derived, as shown in Figure 4. When changing the fixed channel length and the drain bias, the drain current conducted at the linear or saturation region is obviously represented for any tested channel device. We seek to accurately determine the relationship between the μ_eq and these three parameters, V_DS, V_GS, and L_mask to establish a set of more precise device models for high-end design customers. Considering these measurement results, the equivalent mobility should contain the drift and diffusion effects and the contributions of both have usually changed at position x. In this work, there were four separate sections (a, b, c, d), illustrating the long-and-short channel devices and the split of electrical characteristics at linear and saturation regions as L_mask = 120 nm. Under a series of tested devices, L_mask = 0.033, 0.05, 0.09, 0.12, 0.5, and 1 μm when the channel width was fixed as W = 10 μm. Two distribution trends of equivalent mobility were seen, related to the V_DS and V_GS variables. Choosing this device as a dividing crest was similar to the observation of a roll-off effect of threshold voltage in the pilot-run stage. The classification of electrical measurement is demonstrated at

Table 1. Four separated sections are classified as long-short devices and linear-saturation regions.

Channel Length	Operation Mode	Section
Long (>120 nm)	Linear region	X = a
Long (>120 nm)	Saturation region	X = b
Short (<120 nm)	Linear region	X = c
Short (<120 nm)	Saturation region	X = d

.

First of all, μ_eq is written as a function of V_DS in terms of different V_GS at a fixed L_mask, which is described by a third-order polynomial using Taylor’s expansion in Equation (7), where X_i is the coefficient of the ith polynomial with i = 0, 1, 2, 3.

$${\mu }_{eq}\left(V_{DS}\right)={{\displaystyle \sum }}_{i=0}^3{X}_i\times {\left(V_{DS}\right)}^i$$

(7)

X is attributed to each section (a, b, c, or d). X_i is strongly related to the gate voltages as L_mask is fixed. This is given in Equation (8) by using Taylor’s expansion, where X_ij is the coefficient of V_GS polynomials with j = 0, 1, 2, 3.

$$X_i\left(V_{GS}\right)={{\displaystyle \sum }}_{j=0}^3{X}_{ij}\times {\left(V_{GS}\right)}^j$$

(8)

Ultimately, if the impact factor L_mask to the coefficient X_ij is observed, it can be entirely represented as Equation (9), where X_ij is the coefficient of the L_mask variable with k = 0, 1, 2.

$$X_{ij}\left(L_{mask}\right)={{\displaystyle \sum }}_{k=0}^2{X}_{ijk}\times {\left(L_{mask}\right)}^k$$

(9)

The flow charts of the X-coefficients in the simulation and the μ_eq values in the extraction are demonstrated in Figure 5 and Figure 6 with section X = a as an example, respectively. The other sections in the parameter extraction also follow the same procedures to determine accurate μ_eq values correlated to the V_DS, V_GS, and L_mask variables.

Table 2. The relationship between each parameter and the coefficient in Taylor’s expansion.

Coefficient Type	Variables Xi, Xij, and Xijk	Index Range
μeq (VDS)	Xi: functions of VGS	i = 0, 1, 2, 3
Xi (VGS)	Xij: functions of Lmask	j = 0, 1, 2, 3
Xij (Lmask)	Xijk: fitted constant	k = 0, 1, 2

exhibits the whole relationship between parameters and X-coefficients. After extracting the equivalent channel mobility and replacing it into Equations (5) and (6), the inversion charge Q_i(x) can be quantitatively achieved and exhibited in the central zone of Figure 3.

3. Results

Following the previous flow charts to obtain the coefficients of X_i, X_ij, and X_ijk, the μ_eq(V_DS, V_GS, L_mask) at a variable perturbation could be effectively and meaningfully extracted. The equivalent mobility was immediately substituted into Equation (5) to simulate the corresponding drive current. The simulated and experimental results of curves I–V with long-and-short channel devices are shown in Figure 7a–d.

For precise observation of the contribution of μ_eq correlated to V_DS, V_GS, and L_mask, one three-dimensional (3D) plot was established, as shown in Figure 8, incorporating all of these extracted data linked as lines and extending these lines as a continuous plane.

In this work, the tested channel-length devices were 33, 50, 90, 120, and 500 nm, as well as 1 μm. When the channel length L was greater than 120 nm, the section was defined as a long-channel section. Thus, the plot in Figure 8a with L = 500 nm is a long-channel section and L = 33 nm is a short-channel one. The equivalent mobility of the other devices with V_DS and V_GS variables are exhibited in Figure 8b–e. Furthermore, the V_DS and V_GS we sensed range from 0.1 to 0.8 V and from 0.5 to 0.8 V with a step voltage 0.1 V, respectively. The error between simulated and real measurement data is less than 0.3%, no matter what channel-length devices and whether there is a linear or saturation region operation mode.

Table 3. The values of the coefficients in section X = a under V_GS = 0.8 V and L_mask = 500 nm.

Coefficient Value	Extracted Sub-Coefficients
The value of a3	a3 = −247.999
The values of a3j	a33 = 19,833.33
	a32 = −5150
	a31 = −29,383.3
	a30 = 16,400
The values of a3jk	a332 = −3,283,858.592
	a331 = 5,452,922.151
	a330 = −1,885,663.094
	a322 = 6,422,679
	a321 = −10,725,100.45
	a320 = 3,751,730.477
	a312 = −4,094,362.073
	a311 = 6,889,789.134
	a310 = −2,450,687.382
	a302 = 840,872.7189
	a301 = −1,430,708.191
	a300 = 521,535.9158

provides an example of extracting the coefficients in section X = a under V_GS = 0.8 V and L_mask = 500 nm.

4. Discussion

For 1D model of MOSFET, it was developed in the late 1960s [26]. Nevertheless, including the vertical field V_GS factor to promote the accuracy of device models for high-performance-computing (HPC) IC products is less exposed, especially in deep nano-node logic devices. This benefit is similar to silicon purification. If the wafer is metallurgic-grade silicon, the purity is about 98–99% [27], applied to solar panels. However, as the purity is enhanced to 99.9999999%, treated as electronic-grade silicon, this silicon material can be applied to submicron or nano-node wafers to form advanced performance ICs. In Huang’s team [11], the device performance could achieve simulated and physical measurement data errors of around 1–2%. This kind of device model essentially satisfies most of the design houses in nano-node manufacturing. However, considering the lower power consumption and higher electrical performance needed for some advanced products, it seems the device model should be more precise. Here, considering the gate-field variable and interaction with V_DS, the error was fantastically reduced to 0.3% or below, which meant the accuracy in simulation reached 99.7% or more. Generally, this accuracy was sufficient to fit the requirements of HPC products with planar MOSFETs. In Figure 8, as V_DS increases, μ_eq(x) is also increased, but not linearly. This phenomenon is also observed as V_GS increases. As the gate field increases, the entire channel field also increases. Hence, the equivalent mobility is increased, no matter what the increase in gate voltage or drain voltage. However, the threshold voltage V_T is not a constant as the V_DS is scanned from 0 to Vcc (=0.8 V). Due to this effort, compared with the conventional method treated V_T as a constant, this equivalent mobility model provides a more precise consequence. The range of V_T extracted with constant current metrology is from 0.296 to 0.271 V as V_DS set from 0.05 to 0.8 V at L_mask = 1 μm. The drain-induced barrier lowering (DIBL) value defined as (V_{T_lin} − V_{T_sat})/(Vcc − 0.05), a good index to expose the short-channel effect, is 33.36 mV/V, where V_{T_lin} is the threshold voltage at the linear region and V_{T_sat} at the saturation region. All of DIBL values in these tested devices are shown at

Table 4. The DIBL effect with different channel lengths.

Lmask	VT_lin (V)	VT_sat (V)	DIBL (mV/V)
1 μm	0.296	0.271	33.36
500 nm	0.307	0.277	39.01
120 nm	0.332	0.298	46.12
90 nm	0.353	0.306	62.87
50 nm	0.395	0.305	120.38
33 nm	0.384	0.228	208.09

. The DIBL values are increased and, in the meanwhile, the short-channel effect is more significant. In addition, while the V_GS is lower and the I_DS characteristics are located at the linear region, the equivalent mobility decreases due to the contribution of scattering effect of channel surface roughness, as shown in Figure 4. Thus, as the V_DS increases, the μ_eq decreased distinctly until at the pinch-off point V_DS ≈ V_GS − V_T. However, as V_DS increases more, entering the saturation region, the conducted carriers gain more energy and the moving speed of the carriers increases. Thus, the μ_eq increases. Furthermore, as the V_GS is increased, the channel depth of inversion charge is also increased. Most of the conducted carriers in channel choose the low-resistant path. Therefore, the contribution ratio of channel surface scattering effect is slightly reduced. The sunken phenomena are gradually unapparent as the V_GS is increased.

Continuously, establishing a full model incorporating the diffusion and drift effects is a huge challenge. The alternative, describing the equivalent mobility related to V_GS and V_DS with a linear relationship, is also tough. In the short-channel device, the difference of equivalent mobility between sections X = c and X = d can be up to 54 cm²/V-s. For the long-channel device, the maximum difference between the two sections is around 97 cm²/V-s. The minimum difference between linear sections X = a and X = c is about 109 cm²/V-s. However, the maximum difference at these two saturation sections is approximate 153 cm²/V-s. These interesting values are beneficial to the establishment of device models or to process improvement if needed.

The distribution of inversion charge coming from the drift effect under checking points B to D, with a percentage variation related to position x, is shown in Figure 3. The inversion charge is not uniform in each position, and the diffusion current is turned on as the drain voltage is triggered. Thus, the inversion charge with a log scale at x = 0 is not 100%. This consequence opportunely reflects the equivalent mobility contributed by the drift and diffusion effects similarly to a leverage. However, the drift effect at the smallest channel-length device is unapparent, and the diffusion effect is dominant, similarly to ballistic carrier behavior [28,29]. This phenomenon at L_mask = 33 nm is similar to the depletion effect coming from the channel punch-through, not the enhancement effect [1]. Although the importance of the diffusion effect is enhanced, the degradation of channel surface roughness or surface scattering is increasing, which impacts the channel mobility. This effect is probably due to the increase in gate field slightly retarding the flowing of surface current. From checking points B to D, the current density is treated as line density (A/cm). At checking points A and E, there is no diffusion or drive current dominated by the drift effect. The unit of current density is recovered as A/cm².

Extension work to establish the precise device models for 3D devices such as FinFETs [30,31,32] or gate-all-around FETs [33,34] is still outstanding. Even though the device format is multi-nano-sheet (mNS) or multi-bridge-channel [16,35,36,37], this concept of providing a great set of device models considering the contribution of the gate field is rather feasible. Of course, entering the 10-nm process or beyond, the current performance can be disturbed by quantum confinement effects [38,39,40]. These effects are useful to consider in modelling 5-nm FinFET devices or beyond as the device dimension of semiconductors approaches near to or moves below the exciton Bohr radius (EBR) of bulk semiconductors [41], where EBR is defined as the separation distance between the hole and electron around 1–10 nm. The charge carriers can freely move in a bulk semiconductor, and, thus, the wave function is similar to a hydrogen atom. In addition, Dr. Mark Liu, president of TSMC, in February 2021 [13], addressed the manufacturing products adopted the FinFET structure at the 3-nm process era. Hence, this extension task from 1D to 2D device-model improvement is impressive. In the future, separately considering the channel-length modulation and overshoot of drift velocity in the device model should enable us to obtain accurate device models beyond 10-nm field-effect transistors. Here, these two factors were temporarily incorporated into equivalent mobility in calculation, not separated as variables in discussion. For the new devices, such as mNSFETs or complementary FETs (CFETs) in the 1- or 2-nm process [42,43,44], advanced device models will be more complicated and the quantum mechanics effect in carrier movement [2] must be included in calculation. Ultimately, the contribution of the channel length as a variable can probably be considered if needed.

5. Conclusions

Integrating the effects of channel length modulation and drift velocity overshoot into the equivalent mobility, the mixed current model, including surface drift and diffusion current, has been created to describe the electrical behavior of the drive current of nano-node MOSFETs. The existence of a diffusion current addresses why the drive current enters the saturation region but does not reach zero at the pinch-off point. The diffusion contribution to the drive current becomes more apparent, especially for short-channel MOSFETs. For devices operating normally, the parameters (V_DS, V_GS, and L_mask) independent of channel position are strongly correlated to the μ_eq variable. It is thus necessary to investigate the mutual interaction among them. This work successfully determined the physical and meaningful consequences for nano-node HK/MG MOSFET devices fabricated with ALD technology. The error between simulated and experimental results was less than 0.3%, which is suitable for 28-nm devices or beyond to build up a more accurate set of device models in circuit design consideration. This performance is also better than that achieved in a previous project [11]. In the future, this methodology can be employed for the device model of 3D FinFETs or gate-all-around FETs for sub-10-nm manufacturing technology.