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Computers 2018, 7(4), 53; https://doi.org/10.3390/computers7040053

Automatic Configurable Hardware Code Generation for Software-Defined Radios

Software Defined Radio Group, Electrical Engineering Department, University of Cape Town, Cape Town 7701, South Africa
This paper is an extended version of our paper published in the International Conference on Field Programmable Technologies (FPT 2017).
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Received: 3 September 2018 / Revised: 16 October 2018 / Accepted: 17 October 2018 / Published: 19 October 2018
(This article belongs to the Special Issue Reconfigurable Computing Technologies and Applications)
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Abstract

The development of software-defined radio (SDR) systems using field-programmable gate arrays (FPGAs) compels designers to reuse pre-existing Intellectual Property (IP) cores in order to meet time-to-market and design efficiency requirements. However, the low-level development difficulties associated with FPGAs hinder productivity, even when the designer is experienced with hardware design. These low-level difficulties include non-standard interfacing methods, component communication and synchronization challenges, complicated timing constraints and processing blocks that need to be customized through time-consuming design tweaks. In this paper, we present a methodology for automated and behavioral integration of dedicated IP cores for rapid prototyping of SDR applications. To maintain high performance of the SDR designs, our methodology integrates IP cores using characteristics of the dataflow model of computation (MoC), namely the static dataflow with access patterns (SDF-AP). We show how the dataflow is mapped onto the low-level model of hardware by efficiently applying low-level based optimizations and using a formal analysis technique that guarantees the correctness of the generated solutions. Furthermore, we demonstrate the capability of our automated hardware design approach by developing eight SDR applications in VHDL. The results show that well-optimized designs are generated and that this can improve productivity while also conserving the hardware resources used. View Full-Text
Keywords: reconfigurable computing; field programmable technologies; field programmable gate arrays; FPGAs; design automation; software-defined radio; domain-specific language; high-level synthesis reconfigurable computing; field programmable technologies; field programmable gate arrays; FPGAs; design automation; software-defined radio; domain-specific language; high-level synthesis
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).
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Tsoeunyane, L.; Winberg, S.; Inggs, M. Automatic Configurable Hardware Code Generation for Software-Defined Radios. Computers 2018, 7, 53.

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