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Computers 2018, 7(4), 52; https://doi.org/10.3390/computers7040052

Run-Time Mitigation of Power Budget Variations and Hardware Faults by Structural Adaptation of FPGA-Based Multi-Modal SoPC

1
Electrical and Computer Engineering Department, Ryerson University, Toronto, ON M5B 2K3, Canada
2
MDA Corporation, Brampton, ON L6S 0B6, Canada
*
Author to whom correspondence should be addressed.
Received: 13 July 2018 / Revised: 5 October 2018 / Accepted: 7 October 2018 / Published: 11 October 2018
(This article belongs to the Special Issue Reconfigurable Computing Technologies and Applications)
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Abstract

Systems for application domains like robotics, aerospace, defense, autonomous vehicles, etc. are usually developed on System-on-Programmable Chip (SoPC) platforms, capable of supporting several multi-modal computation-intensive tasks on their FPGAs. Since such systems are mostly autonomous and mobile, they have rechargeable power sources and therefore, varying power budgets. They may also develop hardware faults due to radiation, thermal cycling, aging, etc. Systems must be able to sustain the performance requirements of their multi-task multi-modal workload in the presence of variations in available power or occurrence of hardware faults. This paper presents an approach for mitigating power budget variations and hardware faults (transient and permanent) by run-time structural adaptation of the SoPC. The proposed method is based on dynamically allocating, relocating and re-integrating task-specific processing circuits inside the partially reconfigurable FPGA to accommodate the available power budget, satisfy tasks’ performances and hardware resource constraints, and/or to restore task functionality affected by hardware faults. The proposed method has been experimentally implemented on the ARM Cortex-A9 processor of Xilinx Zynq XC7Z020 FPGA. Results have shown that structural adaptation can be done in units of milliseconds since the worst-case decision-making process does not exceed the reconfiguration time of a partial bit-stream. View Full-Text
Keywords: run-time structural adaptation; run-time design space exploration; multi-task multi-modal FPGA-based systems run-time structural adaptation; run-time design space exploration; multi-task multi-modal FPGA-based systems
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).
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Sharma, D.; Kirischian, L.; Kirischian, V. Run-Time Mitigation of Power Budget Variations and Hardware Faults by Structural Adaptation of FPGA-Based Multi-Modal SoPC. Computers 2018, 7, 52.

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