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Computers 2018, 7(2), 31;

Hardware-Assisted Secure Communication in Embedded and Multi-Core Computing Systems

Department of Electrical Engineering, COMSATS Institute of Information Technology, 54000 Lahore, Pakistan
Department of Computer Science and Information Systems, California State University San Marcos, San Marcos, CA 92096, USA
School of Mathematical and Computer Sciences, Heriot-Watt University, Edinburgh EH14 4AS, UK
Author to whom correspondence should be addressed.
Received: 16 April 2018 / Revised: 7 May 2018 / Accepted: 12 May 2018 / Published: 15 May 2018
(This article belongs to the Special Issue Multi-Core Systems-On-Chips Design and Optimization)
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With the sharp rise of functionalities and connectivities in multi-core embedded systems, these systems have become notably vulnerable to security attacks. Conventional software security mechanisms fail to deliver full safety and also affect the system performance significantly. In this paper, a hardware-based security procedure is proposed to handle critical information in real-time through comprehensive separation without needing any help from the software. To evaluate the proposed system, an authentication system based on an image procession solution has been implemented on a reconfigurable device. In addition, the proposed security mechanism is evaluated for the Networks-on-chips, where minimal area, power consumption and performance overheads are achieved. View Full-Text
Keywords: secure communication; embedded computing; hardware security; network-on-chip secure communication; embedded computing; hardware security; network-on-chip

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Saeed, A.; Ahmadinia, A.; Just, M. Hardware-Assisted Secure Communication in Embedded and Multi-Core Computing Systems. Computers 2018, 7, 31.

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