A Weighted NBTI/HCD Coupling Model in Full VG/VD Bias Space with Applications to SRAM Aging Simulation

Abstract

In this paper, a coupled negative bias temperature instability (NBTI)/hot carrier degradation (HCD) failure model is proposed on the 2-D voltage plane for aging simulation of SRAM circuits. According to the physical mechanism of failure, based on the reaction–diffusion and hot carrier energy-driven theory, revised degradation models of threshold voltage shift (∆Vth) for the NBTI and HCD are established, respectively, with explicit expressions for gate voltage (V_G)/drain voltage (V_D). An NBTI/HCD coupling model is built on the 2-D {V_G, V_D} voltage plane with a weighting factor in the form of V_G and V_D power law. The model also takes into account the AC effect and long-term saturation behavior. The predicted ∆Vth under various stress conditions shows an average relative error of 11.6% with experimental data across the entire bias space. SRAM circuit simulation shows that the read static noise margin (RSNM) and write static noise margin (WSNM) have a maximum absolute error of 4.2% and 3.1%, respectively. This research provides a valuable reference for the reliability simulation of nanoscale integrated circuits.

1. Introduction

As technology develops, reliability concerns have become more significant [1]. Under real operating conditions in circuits, transistors often experience negative bias temperature instability (NBTI), hot carrier degradation (HCD), and mixed-mode aging, which result in changes to circuit delay and a reduction in design margins [2,3,4,5]. Precise predictions of aging-related temporal shifts and effective EDA solutions are essential for designing with reliability in mind [6].

Extensive research has been dedicated to independently elucidating the degradation mechanisms of NBTI and HCD. NBTI modeling is typically categorized into reaction–diffusion (R-D) [7] and trapping–detrapping (T-D) [8] models. The R-D model effectively captures the power-law dependence of ∆Vth, whereas the T-D framework explains charge-trapping dynamics through first-principles-based formulations. A recent advancement in the defect-centric model (DCM) uses statistical methods to analyze the random aging phenomenon in NBTI [9]. Some investigations have developed the four-state nonradiative multiphonon (NMP) model, which accurately captures charge T-D dynamics [10]. For HCD, predictive models include the lucky electron model [11,12] and the energy-driven model [13]. Many new studies have been conducted on HCD as technology has advanced. Under extended stress, the time-dynamic shape returns to a power-law trend with soft saturation [14,15]. The carrier energy distribution function (EDF) is linked to the mechanism of defect generation, and the ab initio quantum chemistry method is employed to reveal and describe the intricate physics underlying HCD [16]. In addition, the time variability [17] and Joule heating effect [18] cannot be ignored when studying NBTI/HCD. In ultrathin oxide MOSFETs, process engineering enables suppression of hole traps (N_HT), thereby establishing interface traps (N_IT) as the dominant degradation pathway. R-D formulations offer computationally efficient long-term predictions by approximating N_IT generation as a diffusion-limited process. This simplification obviates the need for exhaustive experimental calibration while maintaining predictive accuracy across extended stress durations.

However, real circuits are often affected by both NBTI and HCD simultaneously, making the modeling of their coupling effects crucial. Devices under real circuit operation are exposed to varying V_G and V_D (from 0 to VDD), and simulation extrapolation of independent degradation mechanisms yields inaccurate lifetime predictions. If NBTI and HCD are independent, experiments with alternating them stress should yield the same degree of degradation, but there are differences in the experimental results [19]. An acceleration factor method is used to sum the failure rates of various known failure mechanisms, combining their observed effects under high/low temperature and high-/low-voltage stress [20]. There is no interaction between high-energy and low-energy HCD, off-state stresses, and other modes, whereas there is a complete interaction between BTI stresses and the low-energy HCD modes [21]. Considering the influence of process variability, the contribution of N_IT and oxide traps (N_OT) in BTI and HCD has been analyzed, and the entire framework has been modeled as the superposition of interdependent aging effects [22]. Recent studies have determined the contribution of different types of traps using advanced characterization techniques, identifying three types of traps from HCD experiments to model the coupling effect [23]. If a single failure model is used to predict ∆Vth in the mixed-mode region, it would lead to overly optimistic predictions [24]. In addition, the strongly correlated weighting coefficients used to superimpose the NBTI and HCD may lead to questionable estimation [25]. Two fundamental limitations persist in reliability modeling. First, existing frameworks predominantly treat NBTI and HCD as mutually independent phenomena, thereby neglecting the nonlinear interplay between defect generation and evolution under the concurrent, time-varying V_G and V_D. Second, the voltage-coupling effect remains physically uncharacterized; the empirical expressions currently in use embed V_G and V_D as implicit variables, precluding the quantitative assessment of defect evolution path dependence across distinct bias spaces.

This paper first establishes the NBTI/HCD model as a function of bias voltage and builds the NBTI/HCD coupling model on the 2-D {V_G, V_D} voltage plane through voltage weights that consider additional effects. The coupling model is equivalent to a voltage-controlled voltage source (VCVS) injected into the gate of a critical MOSFET to simulate the effect of voltage stresses, enabling the prediction of degradation in SRAM-related circuit parameters.

2. Model

We focus on modeling the effects of N_IT. N_OT is usually associated with high-field stresses (e.g., time-dependent dielectric breakdown (TDDB)). Typical stress conditions in NBTI and HCD have a relatively weak contribution from N_OT. These charges can be released through tunneling or annealing, both of which have a lesser impact on long-term degradation. N_HT is mainly found in P-type devices and is associated with hole trapping in NBTI. However, its effect is often considered transient, and irreversible degradation is mainly caused by the accumulation of N_IT. Of course, the contributions of N_HT and N_OT can also be considered similarly to N_IT [26].

We assume that the concentration of interfacial traps (ΔN_IT) is proportional to the hole concentration (P) in the antipattern layer [27], where ΔV_th = qΔN_IT/Cox and P = Cox (V_G − Vth). To facilitate the subsequent coupling model construction, the separate voltage-dependent models of NBTI and HCD need to be corrected first.

2.1. Revision of Independent Mechanism Modeling

The proposed modified NBTI model is

$$\Delta V_{\text{th-NBTI}}~V_{\mathrm{G}}^{\alpha } \exp (\beta ·V_{\mathrm{G}}) t^{n_{\mathrm{NBTI}}}{\left(\frac{\gamma ·\mathrm{PDC}}{1+\sqrt{\delta ·\left(1-\mathrm{PDC}\right)}}\right)}^{\epsilon }$$

(1)

where n_NBTI is the time index, PDC is the pulse duty cycle, and α, β, γ, δ, and ε are the fitting parameters.

N_IT is functionally related to the fracture rate of the Si-H bond (k_F). Some works model k_F as an exponential function of the perpendicular electric field in the gate oxide [27,28]. We present its relation to the oxide electric field (E_ox) in the exponential form of V_G, where the power-law form of V_G represents the relationship between ΔN_IT and P. The R-D model for N_IT is widely accepted by experimental validation, which illustrates the power-law time dependence of NBTI degradation and n_NBTI = 1/6 [29,30]. Based on the DC model, PDC is modeled as a scaling factor for AC degradation prediction [31]. In the frequency range of Hz–GHz, NBTI is independent of the input signal frequency [32,33].

The proposed modified HCD model is

$$\Delta V_{\text{th-HCD}} ~ V_{\mathrm{G}}^{\theta } \exp \left(\lambda ·V_{\mathrm{D}}\right)·\left(1-\exp \left(-\rho · t^{n_{\mathrm{HCD}}}\right)\right) · f^{\sigma }$$

(2)

where n_HCD is the time index, f is the AC frequency, and θ, λ, ρ, and σ are the fitting parameters.

The recovery effect is neglected since the trap is generated only near the drain of the transistor [34]. The power-law form of V_G characterizes the effect of carrier concentration, and the exponential form of V_D characterizes the effect of carrier energy. A larger leakage voltage results in a stronger horizontal electric field in the channel, which increases the carrier energy and the probability of N_IT. The obtained generation rate of N_IT is a power law with respect to time, where n_HCD = 0.5 [12,35]. The time shift of the Si-H bond breaking position and the dispersion of the Si-O bond energy are used to explain the degenerate saturation behavior of HCD [14,36]. From the energy point of view, the frequency is modeled as a simple power-law form [37,38]. The delay degradation of the circuit is approximately the same for different duty cycles at a fixed frequency; HCD is independent of the input signal duty cycle [39].

2.2. Coupling Model

Based on the voltage forms derived from the independent NBTI and HCD models, we propose the coupling weight V_G^x · V_D^y is composed of the power-law form V_G and V_D to capture the NBTI/HCD interaction, where x and y are fitting parameters. We combine the power law of V_G and V_D, and the final simplified coupling model is

$$\begin{gathered} \Delta V_{\text{th-total} }={ A}_{\mathrm{NBTI}} · V_{\mathrm{G}}^{\mathit{\alpha }} \exp \left(\beta · V_{\mathrm{G}}\right) ·{{{ V}_{\mathrm{D}}}^{y1} · t}^{n_{\mathrm{NBTI}}}·{\left(\frac{\gamma ·\mathrm{PDC}}{1+\sqrt{\delta ·\left(1-\mathrm{PDC}\right)}}\right)}^{\epsilon } \\ \begin{array}{c}+{ A}_{\mathrm{HCD}} · V_{\mathrm{G}}^{\theta } \exp \left(\lambda · V_{\mathrm{D}}\right)·{V_{\mathrm{D}}}^{y2}· \left(1-\exp \left(-\rho · t^{n_{\mathrm{HCD}}}\right)\right) · f^{\sigma }\end{array} \end{gathered}$$

(3)

where A_NBTI and A_HCD are fitting parameters. In NBTI experiments (e.g., time-dependent defect spectroscopy, TDDS), V_D is typically set to a low value, keeping the transistor in the linear region [40]. At this point, the channel carrier concentration is uniform, and the electric field is predominantly perpendicular to the gate, with a relatively weak lateral electric field. In contrast, HCD occurs at high V_D, where the transistor enters the saturation region, channel pinch-off points appear, and the lateral electric field intensifies. High-energy carriers (hot electrons or holes) generate interface states or oxide defects through collision ionization. High V_D enhances the lateral electric field, affecting defect dynamics by shifting the defect energy level [41]. This alters the capture/emission energy barrier, thereby influencing capture/emission time. High-stress regions cause rapid trap capture, leading to significant threshold voltage degradation [16]. Therefore, the V_D term not only reflects the influence on the NMP process in NBTI but also demonstrates its impact on energy in HCD. HCD affects the channel carrier EDF via the V_D, thereby altering the nonradiative multiphonon transition rates that govern NBTI. The channel carrier concentration is directly influenced by NBTI through V_G, and it then impacts the HCD process through the energy-driven mechanism. When V_D is fixed and V_G increases, or V_G is fixed and V_D increases, both NBTI and HCD will increase.

Figure 1 shows a schematic of the circuit aging simulation based on the coupling failure injection equivalent voltage source model. This paper uses the commercial 28 nm process library at standard temperature. The PMOS transistor aspect ratio is set to 100 nm/30 nm, and the NMOS transistor aspect ratio is set to 200 nm/30 nm, where VDD = 1.8 V. The coupling model is written as an algorithmic module using Verilog-A, and the VCVS is added to the gate of the critical PMOS transistor to simulate the NBTI and HCD failure stresses applied at the relevant times.

3. Results and Discussion

Figure 2 gives the fitting results of ΔV_th on the 2-D {V_G, V_D} voltage plane. Figure 2a shows the NBTI model fitting results. In the high-voltage combination region, the maximum relative error is 23.306%, while the minimum is recorded at 0.017%. In the low-voltage combination region, the simulation data is marginally lower than the experimental data [42] and is appropriate when V_G = V_D = 2 V. Figure 2b shows the HCD model fitting result, with a maximum relative error of 39.106% and a minimum of 15.595% in the high-voltage combination region. The predicted values are higher than the experimental data [42] in the low-voltage combination region (V_G > 1.5 V, V_D < 1 V or V_G < 1.5 V, V_D > 1 V). This is due to not accounting for the contribution of NBTI under high-stress conditions. As illustrated in Figure 2c, the coupling model demonstrates a substantial discrepancy between the simulated and experimental data [42] in the low-voltage region (V_G < 1 V, V_D < 1 V), attributable to Vth degradation. Due to the smaller ΔV_th in the low-voltage region, minor measurement errors or model deviations are amplified, leading to poor fitting results. Therefore, we focus on the decay trend of the threshold voltage. The coupling model’s entire region has a mean square error that is normalized to 0.0641. In the region where V_G > 1.5 V and V_D > 1.5 V, the maximum value is 23.3%, and the minimum is 0.017%. The coupling weight mechanism plays a crucial compensatory and corrective role. In the range of 0–2 V across the entire bias space, Figure 2d is a plot of the effect of the fitted relative error, which is within 15% of the experimental data.

Figure 2. Results of fitting analysis of ∆Vth on the 2-D {V_G, V_D} voltage plane [42]. (a) NBTI model, (b) HCD model, (c) NBTI and HCD coupling model, (d) relative error.

Figure 2. Results of fitting analysis of ∆Vth on the 2-D {V_G, V_D} voltage plane [42]. (a) NBTI model, (b) HCD model, (c) NBTI and HCD coupling model, (d) relative error.

Figure 3 shows the variation curves of ∆Vth with model parameters. Figure 3a shows validation of the saturation effect of the HCD, where A_HCD = 3.245, θ = 0.436, λ = 3.518, and ρ = 0.050. It has a similar trend of variation as the experimental data [43]. Only a single degradation mechanism of HCD is considered here, which is somewhat different in magnitude from the coupled experimental data. When the long-term saturation of HCD is not considered, the prediction after 100 s continues as a straight line [44]. The results in Figure 3b are consistent with the experimental data [45] on the HCD frequency effect. Figure 3c shows that the model is able to predict experimental data [46] for smaller and larger ranges of duty cycle, such as ranges with a duty cycle between 0.2 and 0.8.

Figure 4 shows the failure of NBTI/HCD coupling in the model curves of ∆Vth with time for different bias voltages, and the relevant fitting parameters are shown in

Table 1. List of coupling failure model parameters for V_G = V_D = 1.4 V and 1.6 V.

VG = VD = 1.4 V
ANBTI	0.979	AHCD	2.448
α	0.723	θ	5.967
β	1.645	λ	1.710
γ	1.140	ρ	0.114
δ	263.495	nNBTI	0.16
ε	0.333	nHCD	0.5
y1	4.129	y2	63.316
VG = VD = 1.6 V
ANBTI	1.245	AHCD	5.052
α	1.096	θ	7.221
β	2.068	λ	0.483
γ	1.140	ρ	0.048
δ	263.495	nNBTI	0.16
ε	0.333	nHCD	0.5
y1	12.632	y2	87.137

. It shows that ∆Vth has a power law that depends on time during the initial stage, while a trend of degradation saturation appears in the later stage. The failure models proposed in other works [47] cannot predict the long-term saturation behavior and differ greatly from the experimental data [43]. With the increase in stress time, the prediction error gradually decreases, indicating that the proposed coupling model has a relatively accurate long-term prediction effect.

Figure 3. Variation curves of ∆Vth with model parameters. (a) HCD long-term saturation [43,44], (b) HCD frequency [45], (c) NBTI duty cycle effect [46].

Figure 3. Variation curves of ∆Vth with model parameters. (a) HCD long-term saturation [43,44], (b) HCD frequency [45], (c) NBTI duty cycle effect [46].

Figure 4. Model validation and comparison of threshold voltage degradation (∆Vth) curves with time, considering NBTI/HCD coupling failure [43,47]. (a) V_G = V_D = 1.4 V, (b) V_G = V_D = 1.6 V.

Figure 4. Model validation and comparison of threshold voltage degradation (∆Vth) curves with time, considering NBTI/HCD coupling failure [43,47]. (a) V_G = V_D = 1.4 V, (b) V_G = V_D = 1.6 V.

Figure 5 shows the simulated performance parameters for inverter NBTI/HCD coupling failure. With increasing stress voltage time, the rise delay (Figure 5a) is degraded from 5.316 ps to 8.019 ps between 0 s and 7000 s. The fall delay (Figure 5b) is basically unchanged and degraded from 2.082 ps to 2.145 ps for the same degradation time. This is due to the fact that the rise delay is affected by the PMOS, while the fall delay is dominated by NMOS. As the severity of the PMOS transistor ∆Vth increases, the rise delay of the inverter also increases. This is consistent with the experimental results. The coupling failure leads to a leftward shift of the DC voltage transfer characteristic curve and a decrease in the switching Vth, as shown in Figure 5c. When ∆Vth shifts caused by subjecting the PMOS transistor to stress for 1000 s, 3000 s, and 5000 s are applied to the PMOS transistor, the SNMs at the four times are 0.524 V, 0.512 V, 0.47 V, and 0.457 V, respectively. As the stress time decreases from 0 s to 5000 s, the SNM of the inverter decreases from 0.524 V to 0.457 V, as shown in Figure 5d. Coupling failure leads to the weakening of the driving capability of the PMOS transistor.

Figure 6 shows the simulated performance parameters associated with NBTI/HCD coupling failure in 6T-SRAM. Figure 6a plots the butterfly curves of RSNM at different times. As the stress time changes from 0 s to 3000 s, the RSNM simulation data from 0.325 V to 0.267 V demonstrates an 18% degradation, and the experimental data [48] demonstrates a 13.8% degradation. Figure 6b plots the butterfly curve of the WSNM at different times. As the stress time changes from 0 s to 2000 s, the WSNM simulation data from 0.568 V to 0.559 V demonstrates a 16.2% degradation, and the experimental data [48] demonstrates a 13.1% degradation. It can be seen that ∆Vth deepens with increasing stress time, and Vth of the PMOS transistor increases, thereby gradually reducing the stability of the circuit.

Figure 6. Simulation results of NBTI/HCD coupled aging and failure of a 6T-SRAM cell. (a) RSNM butterfly curve, (b) WSNM butterfly curve, (c) comparison of RSNM simulation results with experimental data [48], (d) comparison of WSNM simulation results with experimental data [48].

Figure 6. Simulation results of NBTI/HCD coupled aging and failure of a 6T-SRAM cell. (a) RSNM butterfly curve, (b) WSNM butterfly curve, (c) comparison of RSNM simulation results with experimental data [48], (d) comparison of WSNM simulation results with experimental data [48].

Figure 7 shows the simulation results for the degradation parameters and failure performance of the sensitive amplifier under NBTI/HCD coupling. In order to investigate the effect of coupling failure on sensing delay at low power consumption, different VDD simulations are scanned, where the BTI effect is considered in the experimental data. At the 2 ns moment in Figure 7b, SE changes from 0 to 1, P3 and P4 turn off, N3 conducts, and the inverter pair begins to amplify the voltage difference on the bit line. In order to calculate the value of the sensing delay, the time difference between the moment of swing stabilization and t = 2 ns is determined. For 100 s stress time, Figure 7c shows that the sensing delay decreases with increasing VDD. The coupling failure leads to an increase in sensing delay at the same VDD. The simulation data differs from the experimental data [49] by 0.75% at VDD = 0.9 V. This is due to the fact that the N1 transistor Vth is degraded under the effect of coupling failure, so the QN voltage takes longer to drop to (VDD-Vth_-N1). The time for the bit line to amplify to the full swing is increased, and the read speed is reduced. Figure 7d shows that the degradation of dynamic power consumption increases with increasing VDD for 800 s stress time. The bit line is connected to a large number of memory cells, making the load capacitance and load resistance increase significantly. When the sensitive amplifier performs a read operation, turning on only one row of memory cells will not only greatly prolong the data reading time but also consume a lot of power during the charging and discharging process. In low-power operating scenarios, the significant impact of coupling failure on sensing delay and power consumption must also be taken into consideration.

Figure 7. Sensitive amplifier circuit simulation results under NBTI/HCD coupling aging and failure. (a) Schematic, (b) timing simulation schematic, (c) sense delay degradation simulation with comparative verification at different VDDs [49], (d) power consumption degradation simulation with comparative verification at different VDDs [49].

Figure 7. Sensitive amplifier circuit simulation results under NBTI/HCD coupling aging and failure. (a) Schematic, (b) timing simulation schematic, (c) sense delay degradation simulation with comparative verification at different VDDs [49], (d) power consumption degradation simulation with comparative verification at different VDDs [49].

4. Conclusions

To explicitly account for the concurrent influence of the interface electric field (controlled by V_G) and the hot carrier injection energy (driven by V_D) on defect generation, the cross-coupling term V_G/V_D is incorporated into both the R-D and hot carrier energy-driven frameworks. This augmentation yields a unified NBTI/HCD model whose analytical formulation explicitly contains V_G and V_D, thereby enabling accurate prediction of defect density under arbitrary bias conditions. The final coupling model is constructed by using the voltage weight factor on the 2-D {V_G, V_D} voltage plane.

By calibrating with the experimental data of the 28 nm process, the proposed coupling model predicts the magnitude of degradation well under different stress conditions. The results of the circuit-level simulation method show that the errors between the simulation data and the experimental data for different metrics are within reasonable limits, which could be used to predict the performance degradation of nanoscale integrated circuits in real operating environments.