Scalable, Modular Three-Dimensional Silicon Microelectrode Assembly via Electroless Plating
Abstract
:1. Introduction
1.1. Overview of 3-D Approaches
1.2. Creating a Scalable 3-D Probe Design
1.3. Scope of the Design
2. Materials and Methods
2.1. Fabrication and Assembly Overview
2.2. Mechanical Assembly Procedures
2.2.1. Inserts and Holder Plate
2.2.2. Self-Locking Hook
2.2.3. Self-Alignment Combs
2.2.4. Improvements to the Self-Alignment Combs
2.2.5. Alternative Assembly Methods
2.3. Electrical Assembly Procedures
2.3.1. Post-Package Electrolytic Plating
2.3.2. Electrolytic Plating with Seed Layer and Mask
2.3.3. Seedless Plating with Temporary Short Circuits
2.3.4. Electroless Plating
2.3.5. Comparison
3. Results
3.1. Example Designs
3.2. Mechanical Characterization
3.3. Electrical Characterization
4. Discussion
5. Conclusions
Author Contributions
Funding
Acknowledgments
Conflicts of Interest
References
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Reference | Method a | Design b | Total Sites | Connection k Count Pitch | |
---|---|---|---|---|---|
Nordhausen 1996 [9] | Monolithic | 10 × 10 × 1 | 100 | n/a | n/a |
Hoogerwerf 1991 [14] | Electrolytic | 4 × 4 × 16 | 256 | 16 g | - |
Hoogerwerf 1994 [24] | Electrolytic | 4 × 4 × 8 | 128 | 16 g | - |
Barz 2013 [25] | Electrolytic | 4 × 4 × 4 | 64 | 64 | 70 µm |
Herwik 2009 [18] | Pressed | 4 × 4 × 5 | 80 | 80 | 70 µm |
Kisban 2010 [20] | Pressed | 2 × 4 × 5 | 80 | 80 | 35 µm d |
Aarts 2011 [19] | Pressed | 4 × 4 × 5 | 80 | 80 | 70 µm e |
Bai 2000 [16] | Ultrasonic | 4 × 4 × 4 | 32 | 32 g | - |
Yao 2007 [17] | Ultrasonic | 4 × 8 × 32 | 1024 | 32 g | - |
Perlin 2008 [15] | Ultrasonic | 4 × 4 × 4 | 64 | 64 | 40 µm |
Malhi 1987 c [22] | Solder | 9 × 1 × 22 | 198 | 198 | - |
Cheng 2014 [21] | Solder | 5 × 4 × 5 | 100 | 100 | 150 µm |
Lee 2009 [23] | Silver Paste | 4 × 4 × 1 | 16 | 16 | 800 µm e |
Takeuchi 2004 [30] | Folding | 2 × 3 × 3 | 18 | n/a | n/a |
Wang 2010 [28] | Folding | 2 × 2 × 4 | 32 | n/a | n/a |
John 2011 [26] | Folding | 3 × 3 × 2 | 18 | n/a | n/a |
Chen 2011 [29] | Folding | 2 × 2 × 2 | 8 | n/a | n/a |
Merriam 2011 a [27] | Folding | 4 × 4 × 4 | 64 | n/a | n/a |
Chiou 2010 [31] | Die Stacking | 4 × 4 × 4 | 64 | n/a | n/a |
Rios 2016 [37] | Die Stacking | 4 × 4 × 64 | 1024 | 256 | 200 µm |
Du 2009 [33] | Package | 4 × 2 × 8 h | 64 | n/a | n/a |
Langhals 2009 [35] | Package | 4 × 4 × 4 | 64 | n/a | n/a |
Merriam 2011 b [32] | Package | 5 × 4 × 8 | 160 | n/a | n/a |
Barz 2014 [34] | Package | 2 × 2 × 8 | 32 | n/a | n/a |
Barz 2017 [34] | Package | 2 × 2 × 8 | 32 | n/a | n/a |
Shobe 2015 [10] | Package | 4 × 4 × 64 f | 1024 | n/a | n/a |
Michon 2016 [38] | Micro-Drive | 16 × 2 × 8 | 256 | n/a | n/a |
Step | 2-D Inserts (A) | Holder Plate (B) | Mechanical Supports (C,D) |
---|---|---|---|
Starting material | 150 mm SOI wafer, thicknesses: 15 µm device layer, 0.8 µm buried oxide, 510 µm handle | 150 mm wafer, 525 µm thick, double-sided polished | 150 mm wafer, 525 µm thick, double-sided polished |
Clean wafers and insulation | Piranha clean 1 µm of PECVD SiO2 | Piranha clean 1 µm of PECVD SiO2 | Omitted |
Electron beam lithography metallization (liftoff) | 10 nm Ti/150 nm Au/5 nm Ti, mask is 400 nm of PMMA 495A8 | 10 nm Ti/150 nm Au/5 nm Ti mask is 400 nm of PMMA 495A8 | Omitted |
Optical lithography metallization (liftoff) | 50 nm Ti/400 nm Al, mask is 1.5 µm of AZ5214E | 50 nm Ti/400 nm Al mask is 1.5 µm of AZ5214E | Omitted |
Upper insulation | 1 µm of PECVD TEOS | 1 µm of PECVD TEOS | Omitted |
Electron beam lithography small recording site etch | CF4/CHF3 based SiO2 etch, mask is 800 nm of PMMA 495A11 | CF4/CHF3 based SiO2 etch, mask is 800 nm of PMMA 495A11 | Omitted |
Optical lithography large pad etch | CF4/CHF3 based SiO2 etch, mask is 1 µm of SPR-700 | CF4/CHF3 based SiO2 etch, mask is 1 µm of SPR-700 | Omitted |
Frontside DRIE etch a | CF4/CHF3 based etch of frontside SiO2, then 15 µm etch of Si device layer to buried oxide. Mask is 8 µm of AZ4620. | CF4/CHF3 based etch of frontside SiO2, then 15 µm etch of Si device layer to buried oxide. Mask is 8 µm of AZ4620. | Etch 525 µm through wafer, mask is 8 µm of AZ4620 |
SOI wafer buried oxide etch | CF4/CHF3 based etch of 0.8 µm of buried oxide. | Omitted | Omitted |
Backside DRIE etch | Etch 510 µm through wafer from the backside, mask is 8 µm of AZ4620 | Omitted | Omitted |
Clean wafers | Barrel ash in oxygen plasma | Barrel ash in oxygen plasma | Barrel ash in oxygen plasma |
Insulation on full wafer | Omitted | Omitted | 0.1 µm c of PECVD SiO2 1 µm of Parylene-C |
Remove parts | Break out devices | Break out devices | Break out devices |
Insulation on individual parts | (optional) Place dies facing down onto a Si wafer and deposit 100 nm PECVD Si3N4 to insulate backside b | Place dies facing down onto a Si wafer and deposit 100 nm PECVD Si3N4 to insulate backside b | Omitted |
Detail | Packaged Plating | Short-Circuited Breakout Beams | Seed and Mask | Electroless |
---|---|---|---|---|
Method | Electrolytic | Electrolytic | Electrolytic | Electroless |
Common metal choices | Au, Ni, Cu | Au, Ni, Cu | Au, Ni, Cu | Ni, Cu |
Holder plate design type (see Figure 7) | “A” | “C” | “B” | “A” |
Can be plated before packaging | No | Yes | Yes | Yes |
Requires further processing after plating | No | Yes | Yes | No |
Minimum pitch a | Wpad + 2 Wgap | Wpad + 2 Wgap | Wpad + 2 Wgap | Wpad + Wgap |
Requires direct wiring access to plating pads | Yes | Yes | No | No |
Advantages |
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Disadvantages |
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ID | Design (Part Names) | Recording Site Configuration a | 3-D Array Configuration b | Connections per 2-D Insertc | Total Connections | Connection Pitch | Device Purpose | |
---|---|---|---|---|---|---|---|---|
1a | B160–F160 | 2 × 20 @ 13.0 µm | 9 × 4 | 160 | 1440 | 60 µm | Conservative design | |
1b | B160–F20 | 2 × 2 @ 9.5/14 µm | 9 × 40 | 160 | 1440 | 60 µm | Large shank count, tetrode tips | |
2 | B160–F30 | 1 × 9 @ 250.0 µm | 9 × 17 | 160 | 1440 | 60 µm | Optical-only lithography | |
3 | 3a | B408–F408 | 2 × 34 @ 13.0 µm | 11 × 6 | 408 | 4488 | 40 µm | Standard design |
3b | B409–F408 | 2 × 34 @ 13.0 µm | 11 × 6 | 408 | 4488 | 40 µm | Compact holder plate | |
4 | B1000–F1006 | 4 × 42 @ 13.0 µm | 10 × 6 | 1008 | 10,080 | 26 µm | Aggressive design | |
5 | B1000–F1010 | 2 × 50 @ 13.0 µm | 10 × 10 | 1008 | 10,080 | 26 µm | Aggressive design | |
6 | B10–F10 | 1 × 1 | 8 × 80 | 149 | 1192 | 16.5 to 113.7 µm | Pitch and DRIE etch testing |
Design | Wire Length (mm) | Wire Aspect Ratio (nsq = L/W) | Resistance (kΩ) | Capacitance (pF) |
---|---|---|---|---|
Holder B10 | 5.6 | 1900 | 1.02 | 0.56 |
Insert F10 a | 1.9 | 1050 | n/a | 0.08 |
Holder B160 | 11.3 | 7200 | 8.53 | 1.39 |
Insert F30 | 2.1 | 950 | 0.29 | 0.09 |
Insert F160 | 4.0 | 7700 | 9.30 | 0.28 |
Holder B408 | 13.0 | 14,200 | 21.7 | 1.82 |
Holder B409 | 13.9 | 34,750 | 55.1 | 1.28 |
Insert F408 | 5.3 | 8700 | 9.45 | 0.48 |
Holder B1000 | 15.8 | 39,400 | 66.1 | 1.88 |
Insert F1006 | 8.2 | 14,100 | 18.1 | 0.71 |
Insert F1010 | 5.4 | 11,300 | 12.8 | 0.63 |
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Share and Cite
Scholvin, J.; Zorzos, A.; Kinney, J.; Bernstein, J.; Moore-Kochlacs, C.; Kopell, N.; Fonstad, C.; Boyden, E.S. Scalable, Modular Three-Dimensional Silicon Microelectrode Assembly via Electroless Plating. Micromachines 2018, 9, 436. https://doi.org/10.3390/mi9090436
Scholvin J, Zorzos A, Kinney J, Bernstein J, Moore-Kochlacs C, Kopell N, Fonstad C, Boyden ES. Scalable, Modular Three-Dimensional Silicon Microelectrode Assembly via Electroless Plating. Micromachines. 2018; 9(9):436. https://doi.org/10.3390/mi9090436
Chicago/Turabian StyleScholvin, Jörg, Anthony Zorzos, Justin Kinney, Jacob Bernstein, Caroline Moore-Kochlacs, Nancy Kopell, Clifton Fonstad, and Edward S. Boyden. 2018. "Scalable, Modular Three-Dimensional Silicon Microelectrode Assembly via Electroless Plating" Micromachines 9, no. 9: 436. https://doi.org/10.3390/mi9090436