2D and 3D Interdigital Capacitors and Bias Tees Technologies on MnM Interposer for mmWave Applications ^†

Abstract

This paper presents two capacitors fabricated using the metallic nanowire membrane (MnM) interposer technology operating at mmWaves. Standard 2D interdigital capacitors (IDCs) are designed to operate up to 70 GHz, which presents a straightforward and non-complex fabrication. In comparison, this work also proposes an improved device that is more compact and exhibits large capacitance density, as high-performance vias enable the realization of high-depth capacitors. The fabrication process of 3D devices presents advanced maturity and innovation as it takes advantage of the porous nature of the interposer material to overcome the device complexity, and is also described in detail. Both capacitor types are modeled by a numerical lumped-element model that also considers parasitics. The 3D capacitors were successfully fabricated and characterized up to 70 GHz, displaying capacitance values between 30 fF and 160 fF and self-resonant frequencies in good agreement with mmWave applications. The quality factor of these devices, measured at 40 GHz, lies between 16 and 4, and the superficial capacitance density is between 4 pF/mm² and 8 pF/mm², showing that these devices are indeed promising for mmWave applications. These devices present considerably larger capacitance density compared to 2D traditional capacitors fabricated on the high-performance substrate, highlighting the advantage of 3D fabrication using nanowire growth. In addition, thin-film resistances are simulated and fabricated, projecting their functions as an RF-choke in a bias tee configuration using Ti thin film sputtering deposition step that is also part of the capacitors fabrication.

1. Introduction

In the millimeter-wave (mmWave) range, various unlicensed frequency bands are being selected for very high-bandwidth point-to-point communication links. The main focus of development is not solely on the unlicensed 60 GHz band [1], as applications such as automotive radars and road transport can also be found working at 77 GHz [2] and 120 GHz [3], respectively. Even at higher frequencies than 140 GHz, applications such as RF imaging, security, or medical applications can be found. Since mmWave communication requires a line of sight and free-space attenuation is high, transmissions are limited to a short range of tens of centimeters if only a single antenna is used.

This kind of system requires baluns, diplexers, filters, matching networks, and distribution networks for high-performance antenna arrays. It is clear that wavelength-based passive circuits (baluns, diplexers, filters, couplers, and antennas) should be implemented off-chip for reasons of efficiency and cost. One alternative solution is the use of 3D hybrid integration, either by placing the passive circuits above the integrated circuit (IC) or by using an interposer that supports passive circuits. However, for mmWave systems based on hybrid integration technologies, the overall system cost must be significantly reduced while maintaining adequate RF performance, since packaging and interconnection processes often represent a major fraction of the total system cost [4,5]. In this context, the development of a new generation of interposers capable of producing miniaturized and high-performance transmission lines and vias using a simple and low-cost manufacturing process represents a significant advancement for future 3D hybrid mmWave circuits and systems.

For mmWave and RF circuits, passive lumped components, such as capacitors, are an important element, being used in impedance matching, DC decoupling, filtering, biasing networks, DC blocking, etc. [6,7]. Traditionally, capacitors are realized in parallel-plate structures, where two metallic plates are separated by a thin insulator, metal–insulator–metal (MIM) devices. These devices are present both in monolithic technologies, such as (Bi)CMOS [8] and III–V processes [9], and in non-monolithic processes, such as interposers [10,11] and hybrid microwave integrated circuit (MIC) technologies, traditionally implemented using discrete or thin-film passive components on dielectric substrates [12]. MIM capacitors either require large areas to realize a target capacitance using standard process layers or extra fabrication steps using intermediate metal layers and thinner, high-K dielectrics to increase capacitance density. Multi-layer processes can use vertically stacked parallel plate (VPP) to increase capacitance density [13]; thus, vertical metal walls or mesh could be fabricated using multiple metal layers connected by vias. An example of these structures in CMOS technologies is the metal–oxide–metal (MOM) capacitors that result in compact devices that retain high capacitance density with high-frequency operation [14]. Single-layer processes can also employ interdigital capacitors (IDC) to realize capacitors [15,16], but in comparison with the MIM device, they show lower capacitance densities.

In this letter, a compact, interposer-embedded, 3D IDC operating at mmWave fabricated in a metal-filled nanoporous alumina membrane (MnM) is proposed. The technology was first introduced in [17] for the realization of slow-wave transmission lines. The advantage of this technology is the low complexity and low cost of the realization of Through Substrate Vias (TSVs), ref. [18]. Not only the fabrication of transmission lines and vias but also the precise modeling of these structures [19] and several other basic mmWave devices, such as 3D inductors [20], transformers [21], and crossovers [22], have achieved cutting-edge results. The availability of these small and high-performance vias operating up to 110 GHz [23] enables the fabrication of compact, mmWave-capable capacitors that require no complex or labor-intensive intermediate fabrication steps, and without the need for high-definition processes, maintaining a high density.

One of the main applications of capacitors in the field is the realization of bias tees for active circuits such as signal amplifiers, oscillators, and mixers. While the ideal RF choke relies on high-Q inductors, their realization in general presents narrow bandwidths and a high footprint area. As an alternative, we propose the thin-film Ti resistances that work as RF chokes, especially for small current biasing and ultrawide bandwidth.

This paper is organized as follows. In Section 2, characteristics of the device are explained, and the lumped-element model used for simulation and device layout is presented. Then, in Section 3, fabrication, measurement, and characterization results of the IDCs are given. In Section 4, a discussion on the proposed capacitors is drawn, followed in Section 5 by the concept of fabrication of the thin-film resistance—measurements of the resistance are presented, and how it can be applied on bias tees with simulation. Finally, a conclusion is drawn in Section 6.

2. Capacitor Device, Model, and Design

2.1. Device

The MnM interdigital capacitor proposed in this work is shown in Figure 1. Two-dimensional devices present only the top conductor surface thickness, which consists of a 3 μm Cu layer—they also present a microstrip with ground plane design (Figure 1a). In contrast to the typical fabrication, the 3D device presents thick walls that consist of through-substrate vias in the porous membrane of nanowires and are fabricated as CPW lines (Figure 1b). This way, the height (h_f) of each wall is fixed at 50 µm, which corresponds to the height of the membrane. The other geometrical parameters are identical for both IDCs, and their capacitance can be controlled by changing the number of nanowire walls (n_w), their length (L_f), the width of the walls (w_f), and the distance between the walls (g_f).

For this structure, the capacitance of the device is directly proportional to the overlap area between the walls and the electrical permittivity and indirectly proportional to the distance between the walls. This way, for a 3D device, the structure can achieve higher capacitance density than a traditional interdigital capacitor.

To fabricate the walls, the nanopores of the alumina substrate were selectively filled with copper using an electrochemical process. Details about the fabrication process are shown in Section 3.

2.2. Model

The proposed lumped-element model and a view of the device are presented in Figure 2a and Figure 2b, respectively. The capacitor itself (C_s), called an intrinsic capacitor, is modeled as a series RLC circuit, which encompasses the following: the series capacitance (C_M), formed by the nanowire walls; the access inductance (L_M); resistance (R_OHM); and the dielectric resistance (1/G_diel) in parallel with C_M. Although the capacitor model is an RLC circuit, we need to evaluate the path return effects (GND return) for mmWave applications. For that reason, the model, shown in Figure 2a, represents the return path as a series-shunt RLCG network. It includes a series RL circuit modeling ground inductance and resistance (L_GND and R_GND, respectively) and a shunt parallel RC circuit modeling the capacitive coupling and dielectric losses between the nanowire walls and the ground (C_SH and R_SH, respectively). Consequently, the complete model can be described by a π-type equivalent topology including series parasitic elements and is represented using Y parameters. Equations (1)–(7) show the model variables and, where applicable, relate them to Y parameters or to the layout dimensions. This model is applied to both 2D and 3D devices, as both present the same conceptualization.

$${\mathrm{C}}_{\mathrm{M}}={\mathsf{\epsilon }}_0{\mathsf{\epsilon }}_{\mathrm{r}}{\displaystyle \frac{{\mathrm{h}}_{\mathrm{f}}}{{\mathrm{g}}_{\mathrm{f}}}}·\left({\mathrm{n}}_{\mathrm{W}}-1\right)·{\mathrm{L}}_{\mathrm{f}}=\mathrm{ }\underset{\mathrm{f}\to 0}{\lim }{\displaystyle \frac{\mathrm{I}\mathrm{m}\left\{{\mathrm{Y}}_{21}\right\}}{2\mathsf{\pi }\mathrm{f}}}\mathrm{ }$$

(1)

$${\mathrm{R}}_{\mathrm{t}\mathrm{o}\mathrm{t}}=\mathrm{ }{\mathrm{R}}_{\mathrm{O}\mathrm{H}\mathrm{M}}+{\displaystyle \frac{1}{{\mathrm{G}}_{\mathrm{d}\mathrm{i}\mathrm{e}\mathrm{l}}}}+\mathrm{ }{\mathrm{R}}_{\mathrm{G}\mathrm{N}\mathrm{D}}=-{\displaystyle \frac{1}{\mathrm{R}\mathrm{e}\left\{{\mathrm{Y}}_{21}\right\}}}$$

(2)

$${\mathrm{G}}_{\mathrm{d}\mathrm{i}\mathrm{e}\mathrm{l}}=\mathrm{ }\mathsf{\omega }·{\mathrm{C}}_{\mathrm{M}}·\mathrm{t}\mathrm{a}\mathrm{n}\left(\mathsf{\delta }\right)$$

(3)

$${\mathrm{L}}_{\mathrm{M}}={\mathrm{L}}_{\mathrm{S}\mathrm{S}}-{\mathrm{M}}_{\mathrm{S}\mathrm{G}\mathrm{i}}=\mathrm{ }{\displaystyle \frac{1}{{\mathrm{C}}_{\mathrm{M}}·{\left(2\mathsf{\pi }\mathrm{S}\mathrm{R}\mathrm{F}\right)}^2}}$$

(4)

$${\mathrm{L}}_{\mathrm{G}\mathrm{N}\mathrm{D}}=\mathrm{ }{\displaystyle \frac{{\mathrm{L}}_{\mathrm{G}\mathrm{i}\mathrm{G}\mathrm{i}}}{2}}+{\displaystyle \frac{{\mathrm{M}}_{\mathrm{G}\mathrm{i}\mathrm{G}\mathrm{i}}}{2}}-{\mathrm{M}}_{\mathrm{S}\mathrm{G}\mathrm{i}}$$

(5)

$${\mathrm{C}}_{\mathrm{S}\mathrm{H}\mathrm{i}}=\underset{\mathrm{f}\to 0}{\mathrm{l}\mathrm{i}\mathrm{m}}{\displaystyle \frac{\mathrm{I}\mathrm{m}\{{\mathrm{Y}}_{\mathrm{i}\mathrm{i}}-{\mathrm{Y}}_{\mathrm{i}\mathrm{j}}\}}{2\mathsf{\pi }\mathrm{f}}}$$

(6)

$${\mathrm{R}}_{\mathrm{S}\mathrm{H}\mathrm{i}}=\mathrm{ }{\displaystyle \frac{1}{{\mathsf{\omega }·\mathrm{C}}_{\mathrm{S}\mathrm{H}\mathrm{i}}·\mathrm{t}\mathrm{a}\mathrm{n}\left(\mathsf{\delta }\right)}}={\displaystyle \frac{1}{\mathrm{R}\mathrm{e}\left\{{\mathrm{Y}}_{\mathrm{i}\mathrm{i}}-{\mathrm{Y}}_{\mathrm{i}\mathrm{j}}\right\}}},\mathrm{ }\mathrm{i}\in \{\mathrm{1,2}\}$$

(7)

In Equation (1), C_M is the low-frequency capacitance, and ε₀ and ε_r are the vacuum and substrate relative electric permittivity. In Equation (2), R_tot is the total series resistive component, and R_OHM and R_GND are the ohmic losses of the intrinsic capacitor and ground network, respectively. In Equations (2) and (3). G_DIEL is the equivalent dielectric loss of the substrate, and tan(δ) is the loss tangent for the substrate. In Equation (4), L_M is the total series inductance of the intrinsic capacitor, L_SS is the self-inductance of the intrinsic capacitor, M_SGi is the mutual inductance between the capacitor and ground, and SRF is the self-resonant frequency. In Equation (5), L_GND is the ground return inductance, L_GiGi is the self-inductance of one of the ground tracks, and M_GiGj is the mutual inductance between ground tracks. The equations for modeling the capacitive coupling and dielectric losses between the nanowire walls and the ground (C_SH and R_SH, respectively) are shown in Equations (6) and (7). For the MnM substrate, ε_r = 6.7 and tan(δ) = 0.015.

The performance of a capacitor could be evaluated in function of the main capacitance (C_S), its SRF, and quality factor (Q). Equations (8) and (9) give the Q and SRF as a function of model parameters.

$$\mathrm{Q}=\mathrm{ }{\displaystyle \frac{\mathrm{I}\mathrm{m}\left\{{\mathrm{Y}}_{12}\right\}}{\mathrm{R}\mathrm{e}\left\{{\mathrm{Y}}_{12}\right\}}}=\mathrm{ }{\displaystyle \frac{\frac{1}{\mathsf{\omega }{\mathrm{C}}_{\mathrm{M}}}-\mathsf{\omega }{\mathrm{L}}_{\mathrm{M}}}{{\mathrm{R}}_{\mathrm{t}\mathrm{o}\mathrm{t}}+\frac{1}{\mathsf{\omega }{\mathrm{C}}_{\mathrm{M}}·\mathrm{t}\mathrm{a}\mathrm{n}\left(\mathsf{\delta }\right)}}}$$

(8)

$$\mathrm{S}\mathrm{R}\mathrm{F}=\mathrm{ }{\displaystyle \frac{1}{2·\mathsf{\pi }·\sqrt{{\mathrm{L}}_{\mathrm{M}}{\mathrm{C}}_{\mathrm{M}}}}}$$

(9)

3. Fabrication, Measurement, and Characterization

The fabrication process of the proposed three-dimensional (3D) interdigital capacitor on the MnM substrate is illustrated in Figure 3. The MnM substrate is based on a porous anodic aluminum oxide (AAO) membrane supplied by InRedox. The fabrication process begins with membrane cleaning using acetone and isopropanol, followed by the deposition of a 300 nm thick SiO₂ mask layer by reactive magnetron sputtering. A copper seed layer is then sputtered onto the backside of the membrane. Subsequent steps include photolithographic patterning and buffered oxide etch (BOE) of the SiO₂ layer, electrodeposition of nanowires, deposition and thickening of a copper layer on the top side of the membrane, and final patterning and etching of the copper layers. These steps define the top and bottom electrodes of the interdigital capacitor. In contrast to 3D CPW capacitors, microstrip 2D capacitors do not include the bottom copper deposition and nanowire growth, and basically consist of the top copper deposition. The final result of fabrication is presented in Figure 4.

For 2D devices, the sets of designs are shown in

Table 1. Set of 2D-manufactured devices.

Set	nw	Lf (μm)	gf (μm)	wf (μm)
1	3	175	10	10
2	3	325	10	10
3	3	625	10	10

with three different sets. Four different sets of 3D devices are also shown in

Table 2. Set of 3D-manufactured devices.

Set	nw	Lf (μm)	gf (μm)	wf (μm)
1	2	50, 150, 250, and 350	10	10
2	3	50, 150, 250, and 350	10	10
3	5	150	10, 15, and 20	5, 10, 15, and 20
4	6	150	10, 15, and 20	5, 10, 15, and 20

. These were fabricated successfully to test both the extraction of model parameters and to validate the model itself. For 2D capacitors, the number of fingers was limited to three, since EM simulations presented parasitic resonance frequencies besides the SRF up to 70 GHz with similar lengths. As length becomes large enough, capacitive and inductive coupling introduce spurious spikes in S-parameters, as shown in [24].

The MnM capacitors were characterized up to 70 GHz using GSG probes (MPI Titan probes with 100 μm pitch) in a Cascade manual probe station EPS-150MMW (Cascade Microtech, Beaverton, OR, USA) and a Keysight PNA 5227B vector network analyzer (Keysight, Santa Rosa, CA, USA). A Line–Reflect–Reflect–Match (LRRM) calibration was conducted. To avoid short-circuiting the bottom of the transformers with the metallic chuck of the probe station, a 5 mm thick ROHACELL 51 IG foam was employed as a spacer.

The devices were simulated in Advanced Design System (ADS) Momentum and in the Ansys Q3D parasitic extractor to obtain the extracted values of inductances, resistances, and capacitances for the devices. The raw S-parameter data of the DUTs plus accesses were de-embedded in the ADS schematic to enable the extraction of the model parameters.

The de-embedded S-parameters for both types of capacitors are presented in Figure 5 together with the corresponding nominal (simulation), model (with the extracted parameters), and measurement results. The 2D capacitor corresponds to w_f = g_f = 10 µm and L_f = 625 µm, while the 3D capacitor corresponds to n_w = 4 and L_f = 125 µm. The results show good overall agreement between the model and the measurements across most of the analyzed frequency range, confirming the validity of the modeling approach and the parameter-extraction method. Some deviations are observed at the highest frequencies, mainly due to measurement-related limitations. In particular, the oscillation observed near 70 GHz is attributed to calibration uncertainties and measurement limitations as the frequency approaches the upper operating limit of the measurement equipment and is therefore considered a measurement artifact rather than an intrinsic device behavior.

The results comparing simulation and extraction from measurements in

Table 3. Comparison between nominal and extracted parameters.

		CS (fF)	CSH1 (fF)	CSH2 (fF)	LS (pH)	SFR (GHz)	RTOT (Ω)
2D: Lf 625 μm, wf 10 μm, gf 10 μm, nw 3 walls	Nominal	39.9	60.1	23.1	149.8	65.10	2.12
	Extraction	51.8	99.4	45.5	130.5	61.20	0.30
3D: Lf 125 μm, wf 10 μm, gf 10 μm, nw 4 walls	Nominal	123.25	9.73	9.88	47.9	55.05	1.065
	Extraction	163.6	14	12	47.9	49.80	1

show that the extracted capacitance is larger than expected according to simulations, and at the same time, the extracted results show higher losses. The authors attribute these divergences to process variations and to the de-embedding method used, specifically noting that the pad structures were not de-embedded, which adds parasitic effects and increases the apparent losses and capacitance in the measurements. It is highlighted that the five times shorter in length 3D capacitor presents three times higher capacitance and three times lower inductance—this occurs due to a higher capacitance area, expanded by the 3D walls that are fabricated through the substrate. The lower inductance is due to the shorter conductor length.

4. Discussion on IDCs

Results of C_S, SRF, and Q for capacitors at 40 GHz with different values of L_f and n_w are shown in Figure 6. The results in Figure 6a show that the 3D capacitors with n_w = 3 exhibit values of Cs between 30 fF and 130 fF for L_f values ranging from 50 µm to 150 µm. On the other hand, the capacitors with n_w = 4 show Cs values ranging from 70 fF to 160 fF for L_f values between 50 µm and 125 µm. It is also highlighted that the much larger intrinsic capacitance of 3D devices, when compared to traditional 2D, as 2D 625 µm long IDCs are comparable with 3D 50 µm long in C_s.

These results show that larger values of capacitance are obtainable by increasing n_w and L_f. The correlation between extracted and simulated capacitance values is generally good, although deviations are observed for some devices. The agreement regarding the SRF (Figure 6b) remains very good for all device lengths. However, for Q (Figure 6c), the extracted values for devices with ${\mathrm{L}}_{\mathrm{f}}<100 \mathsf{\mu }\mathrm{m}$ show a significant deviation from the simulated values.

The discrepancy in C_s may be attributed to manufacturing variations, such as nanowire wall thickness and a reduction in the gap between walls caused by over-etching during the patterning of the nanowire structures. This leads to a smaller gap between the IDC fingers, which leads to a stronger electric field and larger capacitance. This effect was also observed during the fabrication of devices with 5 µm, which resulted in short circuits by joining fingers and walls.

In the case of the quality factor, discrepancies are mainly attributed to the small value of the resistive losses of these devices, which become comparable to the probe contact resistance and to possible resistive via contacts introduced during on-wafer measurements.

These parasitic contributions introduce an additional series resistance, which is approximately constant for all measurements, while the intrinsic device resistance increases with the finger length ${\mathrm{L}}_{\mathrm{f}}$. For short devices (${\mathrm{L}}_{\mathrm{f}}<100 \mathsf{\mu }\mathrm{m}$), device resistance is very small, and the total resistance is dominated by the series resistance, leading to an underestimation of the extracted Q values.

As ${\mathrm{L}}_{\mathrm{f}}$ increases, the intrinsic resistive losses become larger and the relative impact of the contact resistance decreases, improving the agreement between simulated and extracted values. For the much larger 2D reference devices, the intrinsic resistive losses are sufficiently high for this approximation to become accurate.

Considering C_s values close to 100 fF, Figure 7 shows the extracted values for SRF (Figure 7a), Q at 40 GHz (Figure 7b), and capacitance density (Figure 7c) for different values of n_w and L_f, only focusing on 3D devices. These devices exhibit a peak Q of 11.58 and an SRF of 79 GHz, demonstrating their suitability for mmWave applications. It can also be observed that the capacitors show better performance for shorter L_f, which may be attributed to the fact that longer lengths introduce more parasitic effects.

The results for the surface capacitance density for capacitors of L_f = 50 µm for n_w between 3 and 6 show values between 4 pF/mm² and 8 pF/mm².

Table 4. Comparison of mmWave capacitors in the literature and this work in nF/mm².

MIM (CMOS [3,8], MMIC [4])	MOM (CMOS [8])	MIM (Interposer)	IDC	MnM 2D IDC (This Work)	MnM 3D IDC (This Work)
1–25 (“free” device) 21 (high K)	2.5 (130nm) 9 (14nm)	0.0015 [11] (free) 0.2 [7]-0,4 [4] (thin film)	5.8 × 10−4 [10] 6.4 × 10−4 [11]	0.0016–0.0017	0.004–0.008

contains the capacitance density of MIM, MOM, planar IDC, and MnM IDC.

The MnM IDC has about 10 times the capacitance density (surface) when compared to standard IDCs on traditional Si substrates, 2.5 to 5 times compared to 2D IDCs on the MnM substrate, and 6 to 3 times the surface density of interlayer MIM devices on interposers. However, compared to thin-film MIM devices, the MnM 3D IDC shows about 30 times less capacitance density. The capacitance density of monolithic capacitors is also included for reference, where it can be seen that these devices display about 1000 times denser than devices on interposers or MICs. Thus, the MnM 3D IDC is more compact than devices on comparable technologies while operating at mmWaves.

5. Application Study Case: Thin-Film Resistances and Bias Tee Application

One of the main applications of capacitive elements in the mmWave field is the realization of bias tees. Although commercial bias tees are widely available for mmWave instrumentation, designs for integrated mmWave systems are more challenging and often present narrow bands using spiral inductors and λ/4-long transmission lines as RF chokes. Therefore, it is proposed to fabricate and characterize an alternative by using high-resistance thin-film lines that work as RF chokes and can be integrated along the capacitors that work as DC blocks. Before the fabrication process of Cu deposition mentioned in Section 3, a thin Ti layer is deposited by sputtering for 50 s, corresponding to around 1.5 nm thickness, for the primary function of adherence between the MnM substrate and Cu conductor. Taking advantage of this thin-film, the proposed resistances use this Ti layer as the main conductor.

The fabricated devices are shown in

Table 5. Set of thin-film resistances.

Sample	20 μm	30 μm
1	3.9 kΩ	2.8 kΩ
2	4.2 kΩ	3.1 kΩ
3	4.5 kΩ	3.1 kΩ
4	5.0 kΩ	2.9 kΩ
Average	4.4 kΩ	3.0 kΩ

. The manufactured devices present a fixed length of 285 μm. Lines fabricated as shown in Figure 8 were measured with a bench multimeter and DC probes in a Cascade manual probe station (EPS-150MMW).

Due to the small thickness of the thin-film (1.5 nm), very limited current is supported. Indeed, current densities on the order of 10⁶ A/cm² represent a threshold for failure caused by electromigration and subsequent short-circuiting [25]. Using a conservative limit of 0.5 × 10⁶ A/cm² and a width of 30 μm, the maximum current supported for biasing results in 225 μA.

The resistance value of 3.0 kΩ resulted in an attenuation between 28 and 42 dB up to 70 GHz, stating its isolation function in wideband computed by Momentum Simulation on ADS, as shown in Figure 9, providing enough isolation between RF signals and DC sources.

To highlight an application of this bias tee in a feasible context, the open-source HBT model NPN13G2 provided by IHP [26] is used. With the SPICE model on ADS schematic simulation, a scenario in a CE configuration with an ideal bias tee is compared with one bias composed of (1) 30 μm wide and 285 μm long resistance and (2) L_f 625 μm, w_f 10 μm, g_f 10 μm, n_w 3 walls, and a 2D capacitor—both simulated on Momentum—as shown in Figure 10. The base current is 51.4 μA, which is below the reference value of 225 μA. In the real-world scenario, the thin-film resistor can be used in an HBT base, where current remains low enough, and by the collector, an ideal choice is an inductor to handle mA-order currents. In terms of HBT performance regarding S-parameters, this is exhibited in Figure 11, comparing both scenarios. As expected, the real-world scenario biasing only works beyond 50 GHz, since it is the range where the capacitance is large enough to act as a DC block. The maximum gain for the proposed real-world scenario occurs at 54 GHz, with S₄₃ equal to 2.67 dB, whereas the ideal scenario presents S₂₁ of 4.09 dB. The loss is mainly attributed to the IDC.

Figure 12 exhibits a simulation with both components integrated in the layout tool and simulated in momentum on ADS—it is possible to observe a high transmission between fingers of both ends of the capacitor and a high isolation over the thin-film resistor. While simulation presents a functional bias tee, the fabrication of the entire structure is currently in progress in the mmWave Center at USP.

6. Conclusions

In this paper, a low-cost technology is used to fabricate a novel, 3D, substrate-embedded IDC that features a quality factor and self-resonant frequency compatible with mmWave applications, as well as higher capacitance density than other non-monolithic capacitors. This structure is, to the author’s knowledge, the first occurrence of a 3D interdigital capacitor that is not fabricated on monolithic technologies that can operate in mmWaves with adequate performance. These devices, thus, can bridge the gap between integrated, mmWave-oriented capacitors and interposer-based, DC filtering-oriented capacitors. In order to compare to traditional devices in the MnM material, which is promising in these frequencies, those were compared to 2D devices, and the novel material proved to increase capacitance and quality factor significantly. As these devices in such lengths and capacitances can be used as bias tees, it is also proposed that resistances be fabricated at the same step to introduce RF chokes in a straightforward way, which are expected to be suitable for small current biasing while providing isolation of around 30 dB. Although capacitors and resistors were fabricated as separate structures, a case study shows by simulation that this approach can be used for HBT base biasing. Fabrication with the integration of the entire structure is in progress in the mmWave Center at USP for future work.