# Self-Consistent Enhanced S/D Tunneling Implementation in a 2D MS-EMC Nanodevice Simulator

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## Abstract

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## 1. Introduction

## 2. Simulation Framework and Device Structures

#### 2.1. Description of the Simulated Devices

_{2}gate oxide (EOT $=1$ nm) and metal gate work function ($4.385$ eV).

#### 2.2. General Overview of the 2D MS-EMC Tool

#### 2.3. S/D Tunneling Implementation inside the 2D MC-EMC Tool

#### 2.3.1. Standpoint 1. Reformulation of the Tunneling Probability

#### 2.3.2. Standpoint 2. Tunneling Current Computation by Means of the Landauer Formula

## 3. Results

#### 3.1. Comparison between the Different Implementations of the S/D Tunneling Probability in MS-EMC and the Simulation Results from NEGF

#### 3.2. Comparison between the Different Current Computation Strategies in MS-EMC and the Simulation Results from NEGF

## 4. Conclusions

## Author Contributions

## Funding

## Acknowledgments

## Conflicts of Interest

## References

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**Figure 1.**Schematic illustration of the Si DGSOI and FinFET structures with ${L}_{G}$ ranging from 5 nm to 15 nm. The rest of the parameters remains fixed: source length (${L}_{S}$ = 10 nm), drain length (${L}_{D}$ = 10 nm), Si thickness (${T}_{Si}=3$ nm), and Equivalent Oxide Thickness (EOT $=1$ nm). The confinement direction for these devices on standard wafers [100] changed from (100) for DGSOI to ($0\overline{1}1$) for FinFET, whereas the transport direction <011> was the same for both. 1D Schrödinger equation was solved for each grid point in the transport direction, and BTE was solved by the MC method in the transport plane.

**Figure 2.**Flowchart of the S/D tunneling computation inside the MS-EMC simulator through its corresponding add-on module. In the diagram, x and z are the transport and confinement directions, respectively. $n(x,z)$ and $p(x,z)$ stand for the electron and hole concentrations, respectively. $V(x,z)$ is the potential profile, and ${S}_{ij}$ is the scattering rates. ${E}_{j}\left(x\right)$ is the energy profile of the jth subband, and ${\Psi}_{j}(x,z)$ represents the corresponding eigenfunctions. The subscript n stands for the iteration number, and ${t}_{n}$ together with ${t}_{\mathrm{max}}$ is the successive time steps and the final time, respectively.

**Figure 3.**Example of the procedure that restores self-consistency in the MS-EMC simulation by means of ${T}_{\mathrm{DT}}$ by defining a suitable value for $\Delta y$ that also works as a normalization factor for the probability. (

**a**) After solving the Schrödinger equation in each time step, we computed ${T}_{\mathrm{DT}}\left({E}_{x}\right)$ taking $\Delta y=1$ m. (

**b**) We took the maximum of this initial estimation of ${T}_{\mathrm{DT}}$ and defined $\Delta y$ as its inverse, which led to ${T}_{\mathrm{DT}}$ probabilities between 0 and 1. (

**c**) We plotted ${T}_{\mathrm{DT}}$ as a function of the total energy considering different choices of $\Delta y$ (self-consistent and dependent on $\Delta x$).

**Figure 4.**(

**a**) Behavior of the average self-consistent $\Delta y$ estimation as a function of ${V}_{\mathrm{G}}$ for the DGSOI and FinFET with ${L}_{\mathrm{G}}$ ranging from 5 nm to 15 nm. (

**b**) Effect of gate length increase on the different $\Delta y$ definitions (self-consistent and dependent on $\Delta x$).

**Figure 5.**Average number of electrons (in arbitrary units) affected by S/D tunneling as a function of ${V}_{\mathrm{G}}$ in the DGSOI (

**a**) and the FinFET (

**b**) with ${L}_{\mathrm{G}}=7.5$ nm. The results compare the utilization of the WKB probability with respect to ${T}_{\mathrm{DT}}$ with different choices of $\Delta y$ (self-consistent and predefinedly dependent on $\Delta x$).

**Figure 6.**${I}_{\mathrm{D}}-{V}_{\mathrm{G}}$ characteristics for the DGSOI (

**a**) and FinFET (

**b**) with ${L}_{\mathrm{G}}=7.5$ nm employing different methods for computing S/D tunneling. On one hand, we display the set of curves obtained from the MS-EMC tool using ${T}_{\mathrm{WKB}}$ and ${T}_{\mathrm{DT}}$ (with various $\Delta y$ choices) and, on the other, the curve calculated using the NEGF formalism of NESS.

**Figure 7.**Subthreshold current loss as a function of ${L}_{\mathrm{G}}$ in the DGSOI (

**a**) and FinFET (

**b**) between NESS and MS-EMC with the different implementations of the tunneling probability in the Latter.

**Figure 8.**${I}_{\mathrm{D}}-{V}_{\mathrm{G}}$ characteristics for the DGSOI and FinFET with the shortest and longest gate lengths considered in our work, respectively: (

**a**) DGSOI with ${L}_{\mathrm{G}}=5$ nm, (

**b**) DGSOI with ${L}_{\mathrm{G}}=15$ nm, (

**c**) FinFET with ${L}_{\mathrm{G}}=5$ nm, and (

**d**) FinFET with ${L}_{\mathrm{G}}=15$ nm. The plots compare the results from NEGF with those from MS-EMC employing the Landauer approach for the current computation. The total current reported from MS-EMC was also broken down into its tunneling and thermionic contributions.

**Figure 9.**${I}_{\mathrm{D}}-{V}_{\mathrm{G}}$ characteristics for the DGSOI device with (

**a**) ${L}_{\mathrm{G}}=5$ nm, (

**b**) ${L}_{\mathrm{G}}=7.5$ nm, (

**c**) ${L}_{\mathrm{G}}=10$ nm, and (

**d**) ${L}_{\mathrm{G}}=15$ nm. The displayed current curves correspond to: NEGF, MS-EMC with the standard current computation (with and without S/D tunneling), and MS-EMC using the Landauer approach.

**Figure 10.**${I}_{\mathrm{D}}-{V}_{\mathrm{G}}$ characteristics for the FinFET with different gate lengths: (

**a**) ${L}_{\mathrm{G}}=5$ nm, (

**b**) ${L}_{\mathrm{G}}=7.5$ nm, (

**c**) ${L}_{\mathrm{G}}=10$ nm, and (

**d**) ${L}_{\mathrm{G}}=15$ nm. Analogously to the DGSOI, the displayed current curves correspond to: NEGF, MS-EMC with the standard current computation (with and without S/D tunneling), and MS-EMC using the Landauer approach.

**Figure 11.**Subthreshold swing values (SS) as a function of the gate length for the DGSOI and FinFET considering different drain voltages: (

**a**) DGSOI with ${V}_{\mathrm{DS}}=0.1$ V, (

**b**) DGSOI with ${V}_{\mathrm{DS}}=0.5$ V, (

**c**) DGSOI with ${V}_{\mathrm{DS}}=1$ V, (

**d**) FinFET with ${V}_{\mathrm{DS}}=0.1$ V, (

**e**) FinFET with ${V}_{\mathrm{DS}}=0.5$ V, and (

**f**) FinFET with ${V}_{\mathrm{DS}}=1$ V. Current computation corresponds to the different techniques analyzed in our work: NEGF, MS-EMC with the standard approach (with and without S/D tunneling), and MS-EMC incorporating Landauer.

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**MDPI and ACS Style**

Medina-Bailon, C.; Padilla, J.L.; Sampedro, C.; Donetti, L.; Gergiev, V.P.; Gamiz, F.; Asenov, A.
Self-Consistent Enhanced S/D Tunneling Implementation in a 2D MS-EMC Nanodevice Simulator. *Micromachines* **2021**, *12*, 601.
https://doi.org/10.3390/mi12060601

**AMA Style**

Medina-Bailon C, Padilla JL, Sampedro C, Donetti L, Gergiev VP, Gamiz F, Asenov A.
Self-Consistent Enhanced S/D Tunneling Implementation in a 2D MS-EMC Nanodevice Simulator. *Micromachines*. 2021; 12(6):601.
https://doi.org/10.3390/mi12060601

**Chicago/Turabian Style**

Medina-Bailon, Cristina, José Luis Padilla, Carlos Sampedro, Luca Donetti, Vihar P. Gergiev, Francisco Gamiz, and Asen Asenov.
2021. "Self-Consistent Enhanced S/D Tunneling Implementation in a 2D MS-EMC Nanodevice Simulator" *Micromachines* 12, no. 6: 601.
https://doi.org/10.3390/mi12060601