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Open AccessArticle

An Ultra-Area-Efficient 1024-Point In-Memory FFT Processor

1
Sensors Lab, Advanced Membranes & Porous Materials Center (AMPMC), Computer, Electrical and Mathematical Sciences and Engineering Division, King Abdullah University of Science and Technology (KAUST), Thuwal 23955-6900, Saudi Arabia
2
Center for Embedded and Cyber-physical Systems, University of California, Irvine, CA 92697, USA
*
Authors to whom correspondence should be addressed.
Micromachines 2019, 10(8), 509; https://doi.org/10.3390/mi10080509
Received: 30 June 2019 / Revised: 19 July 2019 / Accepted: 30 July 2019 / Published: 31 July 2019
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PDF [2174 KB, uploaded 9 August 2019]
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Abstract

Current computation architectures rely on more processor-centric design principles. On the other hand, the inevitable increase in the amount of data that applications need forces researchers to design novel processor architectures that are more data-centric. By following this principle, this study proposes an area-efficient Fast Fourier Transform (FFT) processor through in-memory computing. The proposed architecture occupies the smallest footprint of around 0.1 mm2 inside its class together with acceptable power efficiency. According to the results, the processor exhibits the highest area efficiency (FFT/s/area) among the existing FFT processors in the current literature. View Full-Text
Keywords: Fast Fourier Transform; in-memory computing; associative processor; non-von neumann architecture Fast Fourier Transform; in-memory computing; associative processor; non-von neumann architecture
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).
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Yantir, H.E.; Guo, W.; Eltawil, A.M.; Kurdahi, F.J.; Salama, K.N. An Ultra-Area-Efficient 1024-Point In-Memory FFT Processor. Micromachines 2019, 10, 509.

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