Next Article in Journal
Flexible Metal/Polymer Composite Films Embedded with Silver Nanowires as a Stretchable and Conductive Strain Sensor for Human Motion Monitoring
Next Article in Special Issue
Memristor Neural Network Training with Clock Synchronous Neuromorphic System
Previous Article in Journal
Magnetic Micromachine Using Nickel Nanoparticles for Propelling and Releasing in Indirect Assembly of Cell-Laden Micromodules
Previous Article in Special Issue
Resistance Switching Statistics and Mechanisms of Pt Dispersed Silicon Oxide-Based Memristors
Article

Tight Evaluation of Real-Time Task Schedulability for Processor’s DVS and Nonvolatile Memory Allocation

1
Department of Computer Engineering, Ewha University, Seoul 03760, Korea
2
Embedded Software Research Center, Ewha University, Seoul 03760, Korea
*
Author to whom correspondence should be addressed.
Micromachines 2019, 10(6), 371; https://doi.org/10.3390/mi10060371
Received: 1 May 2019 / Revised: 27 May 2019 / Accepted: 1 June 2019 / Published: 3 June 2019
A power-saving approach for real-time systems that combines processor voltage scaling and task placement in hybrid memory is presented. The proposed approach incorporates the task’s memory placement problem between the DRAM (dynamic random access memory) and NVRAM (nonvolatile random access memory) into the task model of the processor’s voltage scaling and adopts power-saving techniques for processor and memory selectively without violating the deadline constraints. Unlike previous work, our model tightly evaluates the worst-case execution time of a task, considering the time delay that may overlap between the processor and memory, thereby reducing the power consumption of real-time systems by 18–88%. View Full-Text
Keywords: real-time system; dynamic voltage scaling; task placement; low-power technique; nonvolatile memory real-time system; dynamic voltage scaling; task placement; low-power technique; nonvolatile memory
Show Figures

Figure 1

MDPI and ACS Style

Nam, S.A.; Cho, K.; Bahn, H. Tight Evaluation of Real-Time Task Schedulability for Processor’s DVS and Nonvolatile Memory Allocation. Micromachines 2019, 10, 371. https://doi.org/10.3390/mi10060371

AMA Style

Nam SA, Cho K, Bahn H. Tight Evaluation of Real-Time Task Schedulability for Processor’s DVS and Nonvolatile Memory Allocation. Micromachines. 2019; 10(6):371. https://doi.org/10.3390/mi10060371

Chicago/Turabian Style

Nam, Sunhwa A., Kyungwoon Cho, and Hyokyung Bahn. 2019. "Tight Evaluation of Real-Time Task Schedulability for Processor’s DVS and Nonvolatile Memory Allocation" Micromachines 10, no. 6: 371. https://doi.org/10.3390/mi10060371

Find Other Styles
Note that from the first issue of 2016, MDPI journals use article numbers instead of page numbers. See further details here.

Article Access Map by Country/Region

1
Back to TopTop