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Partial-Gated Memristor Crossbar for Fast and Power-Efficient Defect-Tolerant Training

School of Electrical Engineering, Kookmin University, Seoul 02707, South Korea
Author to whom correspondence should be addressed.
Micromachines 2019, 10(4), 245;
Received: 28 February 2019 / Revised: 9 April 2019 / Accepted: 12 April 2019 / Published: 13 April 2019
(This article belongs to the Special Issue Nanoscale Switches)
PDF [2699 KB, uploaded 23 April 2019]


A real memristor crossbar has defects, which should be considered during the retraining time after the pre-training of the crossbar. For retraining the crossbar with defects, memristors should be updated with the weights that are calculated by the back-propagation algorithm. Unfortunately, programming the memristors takes a very long time and consumes a large amount of power, because of the incremental behavior of memristor’s program-verify scheme for the fine-tuning of memristor’s conductance. To reduce the programming time and power, the partial gating scheme is proposed here to realize the partial training, where only some part of neurons are trained, which are more responsible in the recognition error. By retraining the part, rather than the entire crossbar, the programming time and power of memristor crossbar can be significantly reduced. The proposed scheme has been verified by CADENCE circuit simulation with the real memristor’s Verilog-A model. When compared to retraining the entire crossbar, the loss of recognition rate of the partial gating scheme has been estimated only as small as 2.5% and 2.9%, for the MNIST and CIFAR-10 datasets, respectively. However, the programming time and power can be saved by 86% and 89.5% than the 100% retraining, respectively. View Full-Text
Keywords: memristor crossbar; partial-gated; fast and power-efficient training; defect-tolerant training memristor crossbar; partial-gated; fast and power-efficient training; defect-tolerant training

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Pham, K.V.; Nguyen, T.V.; Min, K.-S. Partial-Gated Memristor Crossbar for Fast and Power-Efficient Defect-Tolerant Training. Micromachines 2019, 10, 245.

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