1. Introduction
The steady growth of population density in megacities and urban agglomerations observed in recent decades necessitates a radical transformation of most urban infrastructures using information and telecommunication technologies. In the transport sector, classical technologies of freight and passenger transportation are being replaced by new technologies, such as the Intelligent Transport System (ITS). ITS includes modern information, communication and telematics technologies. It makes it possible to improve the efficiency of management of the region’s transportation and road complex, as well as to reduce the number of accidents on the road [
1]. One of the main elements of ITS is the vehicular ad hoc network (VANET), which is a highly dynamic, self-organizing vehicular network structure. The increased interest in VANET is due to the fact that it is assigned tasks such as transferring information to drivers about road traffic, vehicle status and incidents, managing road transport in the city, improving the safety of transport processes, as well as the level of comfort for drivers and transport users [
2].
To solve the above mentioned tasks, VANET includes Roadside Unit (RSU) base stations located along roads and On Board Unit (OBU) modules that are placed on the vehicle. To organize information exchange between moving vehicles and base stations, RSUs and OBUs contain wireless telecommunication devices and specialized computing devices. Various communication interfaces are used to organize the exchange in VANET. Thus Vehicle-to-Vehicle (V2V) interface is used for data exchange between vehicles. The Vehicle-to-Infrastructure (V2I) interface was developed to organize OBU-RSU interaction. RSU base stations also communicate with each other using the Infrastructure-to-Infrastructure (I2I) interface. The Vehicle-to-X (V2X) interface is the result of combining IoT and VANET technologies [
3,
4].
However, despite the ever-increasing integration of communication technologies and applications aimed at improving the efficiency of data exchange between vehicles, there are many challenges still unresolved in VANET. Such a challenge is ensuring the cybersecurity of the nodes in VANET. Since the data exchange between nodes is performed in real time over an open broadband radio channel, it has many vulnerabilities. Therefore, there has been a recent trend of continuous increase in the number of cyberattacks. According to Juniper Research analysts, the global damage from cyberattacks increases by an average of 11% annually [
5].
An integrated approach is needed to effectively counter cyberattacks on the VANET. Obviously, before starting data exchange between objects in V2I and V2V, it is necessary to authenticate them. Message authentication code (MAC) [
6,
7], zero-knowledge proof protocols [
8,
9], padding [
10,
11] and timestamps [
12,
13] are widely used as authentication methods. After that, encryption is used to counter cyberattacks aimed at reducing confidentiality, which must be performed on a real-time scale. Advanced Encryption Standard (AES) block symmetric cipher, which has a fairly simple implementation and high speed, is now widely used to solve this problem [
14]. However, failures and malfunctions may occur during the operation of the encryptors included in RSUs and OBUs. This results in the problem of data retransmission. This situation is quite critical if high-priority emergency messages are transmitted over the VANET. Thus, when using NR-V2X radio access technology, the end-to-end transmission delay should be within the range from 3 to 10 ms [
15]. The end-to-end transmission delay is the time it takes for a packet to be transmitted from the sending device to the receiving one. The value of this parameter is affected by both constant delays associated with packet processing, including data encryption and transmission, and variable delays associated with queues on interfaces. In the 802.11p standard, the maximum frame length is 2346 bytes. If universal processors are used in the implementation of the OBU and RSU, the time for encryption and decryption will significantly delay the processing of the message. It was shown in [
16] that it takes 11 microseconds to encrypt a 128-bit block of text. Therefore, it will take 1.612 ms to encrypt a frame of 2346 bytes alone. We believe that a similar time is required for decryption. If an error occurs during the encryption process, it becomes necessary to re-encrypt the message, transmit it over the communication channel, and re-decrypt it. As a result, the message processing time increases to a value of 6.448 ms, which exceeds the minimum value of the end-to-end transmission delay of 3 ms. Thus, the use of a fault-tolerant encryptor makes it possible not to exceed the delay time by correcting the error. Obviously, repeated transmission of the message reduces the safety on the road especially at high density of vehicle traffic. This problem can be solved by giving AES the property of fault tolerance. The use of residue codes in the polynomial ring (RCPR) can ensure the operable state of the encryptor by correcting errors arising from failures. Therefore, the development of a method to improve the cybersecurity of the process of data exchange in the VANET through the implementation of AES encryption with a modular code is an urgent task.
The purpose of the article is to develop a method to improve the fault tolerance of AES encryption systems based on RCPR. The application of this method will increase the cybersecurity of VANET by maintaining the operable state of encryptors and decryptors of RSUs and OBUs.
The new scientific results of the article are:
A new error correction algorithm for redundant RCPR that allows us to correct errors occurring in the residue of a code combination using a single control module.
Mathematical model of fault-tolerant block implementing nonlinear SubBytes transformation with residue codes in the polynomial ring.
Mathematical model of a fault-tolerant block implementing linear MixColumns transformation with residue codes in the polynomial ring.
Structure of the article goes as follows.
Section 2 analyzes related works.
Section 3 is devoted to the development of error correction algorithm for RCPR with one control module.
Section 4 presents descriptions of mathematical models of fault-tolerant blocks implementing linear and nonlinear transformations in AES cipher.
Section 5 presents the results of the efficiency evaluation of the developed method of improving the fault tolerance of AES encryption systems based on RCPR.
2. Related Works
A characteristic feature of VANET is the use of an open broadband radio channel for data exchange between RSUs and OBUs. In this network, the channel length usually does not exceed 1–5 km. Nevertheless, a number of attacks to which it is susceptible are known. A description of the main types of attacks on availability is presented in [
17,
18,
19,
20,
21,
22,
23,
24]. It is known that one of the common cyberattacks are Denial-of-Service (DOS) and Distributed Denial-of-Service (DDOS) attacks. In [
17], the authors presented a classification of DDOS attacks and described the main effects of these attacks on the VANET. The presented information allows us to understand the attacker’s tactics and choose appropriate countermeasures. Countering Denial-of-Service (DOS) attacks using AES encryption algorithm are shown in [
18,
19]. In [
20,
21], types of jamming attacks are discussed. Such attacks aim to disrupt or hinder the reception of information by legitimate nodes in VANET. The papers present countermeasures against passive and active jamming. A description of broadcast tampering attacks in VANET and remedial measures are given in [
22]. In [
23], research results on the impact of black hole attacks on VANET security are presented. In [
24], an effective countermeasure against black hole attacks is described based on the developed AODV routing protocol, which is used to detect these attacks.
When considering the cybersecurity of VANET, attacks on integrity [
25,
26,
27,
28,
29,
30] cannot be overlooked. In [
25,
26], the authors considered the main types of prankster attacks. To counteract such attacks, Ref. [
25] proposes to use a genetic algorithm, and ref. [
26] proposes to use a developed GPS module that shows the location of the prankster’s vehicle. Countering node impersonation attacks is described in [
27,
28]. Methods of countering application attacks on safety and non-safety messages are presented in [
29,
30].
It is known that authentication methods are quite effective means of countering cyberattacks. Thus, Ref. [
31] shows an authentication scheme using AES encryption algorithm. Ref. [
32] describes an authentication scheme to improve the security of vehicles in VANET. The authors based the developed scheme on the joint use of AES and RSA ciphers. This allows us to ensure the integrity and confidentiality of transmitted messages.
In [
33,
34], the authors described effective methods for countering sybil attacks, i.e., generating false identities that allow an intruder to control network resources. In a tunnel attack, legitimate nodes that are far away from each other begin to communicate as if they were close to each other. The method presented in [
35] allows to eliminate the effects of such an attack. Countering cyberattacks that utilize spoofing interference is shown in [
36,
37,
38]. In [
36], a protocol is presented which reduces the time cost of authentication by reducing its cryptographic strength. This allows us to select the parameters of the protocol depending on the traffic intensity. In [
37], a noise-resistant authentication protocol implemented with residue codes is presented. The use of these codes allows to simultaneously increase the imitation resistance of the protocol and ensure its effective operation in a complex interference environment. In [
38], the authors propose a new method using machine learning algorithms aimed at combating the falsification of vehicle’s location.
A special place among cyberattacks is occupied by attacks on confidentiality. In [
39] the authors considered the issues of ensuring the security of the 6G network. Special attention was paid to the use of artificial intelligence (AI) and machine learning (ML) methods in the network, thanks to which this network makes it possible to increase the efficiency of data exchange between subscribers. For effective operation of AI and ML, it is necessary to use a large amount of data obtained using the Internet of Everything (IoE) technology. However, using IoE reduces network privacy. The authors propose to use the intelligent zero trust (ZT) model, which protects the radio access network (RAN) from potential threats, for quick and easy threat detection in real time. The model is designed taking into account the distributed nature of 6G networks and includes security modules in various nodes, such as the base station, the main network and the cloud. In [
28], an analysis of the main attacks’ confidentiality is presented. Their intensity is shown, and the main countermeasures are described. In [
40,
41], it is proposed to use symmetric cryptographic ciphers to counter eavesdropping and traffic analysis attacks. AES encryption algorithm is quite effective in countering brute force cyberattacks. The application of AES in VANET against these cyberattacks is presented in [
42,
43,
44].
In [
45,
46,
47,
48], the main types of man-in-the-middle attacks are analyzed and the proposed methods for countering them in VANET and IoV network are described.
In addition, there is a fairly large body of work that considers the joint application of AES and RSA encryption algorithms [
48,
49,
50,
51].
In [
48], the developed message delivery protocol is described, in which authentication and confidentiality are implemented via AES cipher. In [
49,
50,
51], schemes of encryption key management systems for VANET based on RSA and AES are presented. In [
52], a homomorphic privacy-preserving encryption scheme using AES cipher is proposed to protect vehicle location privacy.
Summarizing the analysis of related works, we can conclude that AES encryption algorithm is widely used as a countermeasure against multiple cyberattacks on VANET. At the same time, VANET encryption is performed at different levels: at the node level and at the message level. The article considers the situation when encryption is performed at the node level, i.e., at the data link layer. Obviously, the effectiveness of the cryptosecurity of VANET largely depends on the reliability of AES encryptors and decryptors. Therefore, error correction and detection during an operation of AES encryptor and decryptor is an urgent task.
Currently, there is a tendency to increase the number of articles in which ML methods are used to eliminate computational errors [
53,
54,
55,
56]. This is due to the fact that ML algorithms have the property of implementing self-correction due to their iteratively convergent nature. This makes it possible to increase the reliability and adaptability of computing tools, eliminating computational errors. However, ML methods effectively eliminate only certain calculation errors. These include the obsolescence of training data, a decrease in its accuracy and asynchrony. Therefore, these methods cannot be used to detect and correct errors in AES encryption algorithm.
In order to increase the fault tolerance of AES encryptor and decryptor, it is advisable to use classical methods that can be divided into two groups. The first group includes structural redundancy methods, the advantage of which is simple implementation. For example, it is proposed in [
57,
58,
59] to use the Triple Modular Redundancy (TMR) method to increase fault tolerance. This method allows one to effectively correct single calculation errors that are caused by hardware failure or malfunction. However, this method has a disadvantage: in order to implement it, it is necessary to use three encryptors and decryptors that will work in parallel.
In order to reduce hardware costs, it is proposed in a number of works to use the method of equipment duplication to increase fault tolerance [
60,
61]. When using this method, there will be two encryptors and decryptors in the OBU and RSU. In this case, the second encryptor/decryptor will be in cold mode, that is, it will be turned on if a functioning encryptor/decryptor fails. The disadvantage of this method is the need to constantly check the operability of functioning devices.
The second group consists of methods using information redundancy. Redundant codes are used in these methods to increase fault tolerance. Cyclic redundancy check (CRC) is proposed in [
62,
63] to detect errors in the operation of devices caused by failures and malfunctions. This code is based on calculating a checksum for a block of data in order to detect accidental changes in information during transmission or storage. However, this code cannot be used to correct errors during the operation of AES encryptor, because CRC only detects them. Error correction codes (ECCs) have higher error correction abilities. As a rule, such codes are used to increase the noise immunity of data transmission systems [
64,
65,
66]. However, it is impossible to use noise-resistant ECCs to increase the fault tolerance of AES encryptor, since these codes are not arithmetic ones.
Arithmetic residue codes, RCPR in particular, can solve this problem of increasing fault tolerance. These codes perform arithmetic operations in the ring of polynomials. Since calculations take place in parallel and independently on the modules of the code, RCPR allows not only to increase the speed of calculations but is also able to detect and correct errors.
Currently, there are many algorithms for detecting and correcting errors in RCPR. For example, in [
67] it is proposed to use the projection method. A modification of this algorithm, which makes it possible to reduce the time required for correction, is presented in [
68]. In [
69], an algorithm for calculating the interval-index characteristic was proposed. In order to correct errors in the residue code, it was proposed in [
70,
71] to use the mixed radix system (MRS). However, these methods have significant disadvantages. Their implementation requires large hardware and time costs. Therefore, the development of a method that allows hardware to remain operational in the event of failures and malfunctions is an urgent task.
5. Results
Let us consider the execution of one round of encryption in AES algorithm as bytes in the first case and as RCPR in the second case. Let the encryptor input be a set of 16 bytes:
Figure 1a shows the data that is input to the SubBytes transformer. The output of the SubBytes transformer produces the result shown in
Figure 1b.
Figure 1c shows the state at the output of the ShiftRows transformer.
Figure 2 shows the state at the output of the MixColumns linear transformer and the execution of the AddRoundKey transformation with the following key:
The result of performing an AddRoundKey transformation is 16 bytes of cipher text:
Let us consider the decryption process in AES. The decryptor input is a cipher text containing 16 bytes, which is summed modulo two with the key. The process of InvAddRoundKey conversion is shown in
Figure 3. The obtained result is fed to the input of the InvMixColumns transformer.
The byte values obtained after executing the InvMixColumns transformation are shown in
Figure 4a. The results of the InvShiftRows transformation are shown in
Figure 4b. The result of executing InvSubBytes transformation is the text shown in
Figure 4c.
Let us consider the performance of AES encryption procedure with the RCPR. For this purpose, the input data are represented as RCPR CCs. The first byte
is passed to the input of the AES encryptor. Then it is passed to the forward converter from positional code to RCPR. Let us present this byte in binary and polynomial forms:
Then, the following RCPR CC consisting of two residues is obtained at the output of the converter:
In other words, we have
. Similarly, the rest of the 15 input bytes are converted, so we obtain the following:
Let us present the key consisting of 16 bytes in RCPR. As a result, we obtain the following:
Let us consider a nonlinear SubBytes transformation using a byte. The byte
is input to the transformer. At the intersection of row “9” and column “0” of
Table A9 in the
Appendix C, there is a number
, which is passed to the output of the SubBytes transformer.
Let us consider the operation of the fault-tolerant SubBytes transformer with RCPR. According to
Section 4.1, the nonlinear transformation is implemented as follows:
The first byte, in the form of two residues , arrives at the input of the fault-tolerant SubBytes transformer, which contains four tables of bits.
In the
Appendix A,
Table A1 and
Table A2 show the informational residues of the output byte
.
Table A3 and
Table A4 show the control residues of the output byte
. There are informational residues
and
at the intersection of row «8» and column «E» in
Table A1 and
Table A2. There are control residues
and
at the intersection of row «8» and column «E» in
Table A3 and
Table A4. As a result of transformation (39), we obtain the following:
Using the informational residues of the output byte, let us calculate new control residues according to (40). We obtain the following:
We calculate the error syndrome according to (41) using two adders modulo two. We obtain the following:
The residues of the output byte are fed to the corrective adders modulo two. Since the error syndrome is , the combination does not contain errors.
Let us suppose an error occurs in the first residue when reading the data and its depth is equal to
. Then the distorted residue, according to (25), will take the following form:
Then, the distorted CC has the following form:
Using the informational residues of the output byte, let us calculate new control residues according to (40). We obtain the following:
Using two adders modulo two we calculate the error syndrome according to (41). We obtain the following:
Since
, the error vector
is used in error correction. According to (42), we have the following:
The error is corrected.
Let us consider the operation of the fault-tolerant MixColumns transformer with RCPR. First, let us perform this operation using bytes. Let MixColumns transformer has four bytes as the input:
,
,
,
. Then, according to (45), we have the following:
According to
Section 4.2, the linear transformation is implemented as follows:
The input of the fault-tolerant transformer receives four bytes, represented in RCPR as , , , .
Then, using the four tables, we obtain the CC for the product of a byte and a constant {02}. In the
Appendix B,
Table A5 and
Table A6 show the informational residues after the multiplication operation.
Table A7 and
Table A8 show the control residues. In the considered example, the computation of the zero byte represented in RCPR is implemented according to (46). Then
where
.
From (50), we can see that
S(00) and
S(10) are subjected to multiplication by a constant. In this case, the inputs of
Table A5,
Table A6,
Table A7 and
Table A8 first receive two informational residues
. The residues of the resulting product
are at the intersection of row «A» and column «4». Then the inputs of
Table A5,
Table A6,
Table A7 and
Table A8 receives two informational residues
. The residues of the resulting product
are at the intersection of row «6» and column «B».
Table 2 shows the application of (50).
The result is , which is subjected to error correction.
- 3.
Using the informational residues of the output byte, let us calculate new control residues according to (40). We obtain
- 4.
Using two adders modulo two, we calculate the error syndrome according to (41). We obtain
- 5.
The residues of the output byte are fed to the corrective adders modulo two. Since the error syndrome is , the CC does not contain errors.
Let us suppose there was an error while reading data in the second residue, and its depth is equal to
. Then the distorted residue, according to (25), will take the following form:
Then, the distorted CC has the following form:
Using the informational residues of the output byte, let us calculate the new control residues according to (40). We obtain
Using two adders modulo two, we calculate the error syndrome according to (41). We obtain
Since
and
, the error occurred in the second residue. Then the error vector is equal to
. According to (42), we have the following:
The error is corrected.
Figure 5a shows CCs at the output of the forward converter from positional code to RCPR. These CCs are passed to the input of the nonlinear SubBytes transformer. The output of the SubBytes transformer produces the result shown in
Figure 5b. At the same time, the redundant RCPR CCs are obtained from the output of this transformer.
Figure 5c shows the state at the output of the ShiftRows transformer.
Figure 6 shows the state at the output of the MixColumns linear transformer and the execution of the AddRoundKey transformation with the key represented in RCPR according to (49).
In this case, only the informational residues are added. The result of performing the AddRoundKey transformation is 16 bytes of the cipher text represented in RCPR. CCs are then subjected to the inverse conversion from RCPR to positional code. This operation is performed based on the Chinese Remainder Theorem (CRT) according to (21).
and
are orthogonal bases for RCPR with two informational modules
and
. In this case, the range of allowed combinations is
. Let us perform the inverse conversion for the zero byte
. Then, according to (21), we have
The decryption process in AES with RCPR is shown in
Figure 7 and
Figure 8. The cipher text is first converted from positional code to RCPR. Then the InvAddRoundKey transformation is performed with RCPR, which is shown in
Figure 7. The obtained result is passed to the input of InvMixColumns transformer.
The byte residues obtained after executing the InvMixColumns transformation with RCPR are shown in
Figure 8a. The results of InvShiftRows transformation with RCPR are shown in
Figure 8b. The result of the InvSubBytes transformation is the plaintext that is obtained using the CRT-based conversion. The result is shown in
Figure 8c.
Let us conduct a comparative analysis of the cybersecurity of VANET using various methods to increase the reliability of AES encryption systems. In this analysis, only the method presented in [
84] and the duplication method are considered. ECCs are not considered in the comparative analysis, since most of these codes are not arithmetic and cannot be used for calculations performed in AES encryption algorithm. These codes are widely used to improve noise immunity of the data transmission system (cyclic codes, BCH codes, Reed-Solomon codes). Also, TMR method was not considered in the comparative analysis. It is known that TMR method makes it possible to effectively correct single calculation errors that are caused by a failure or malfunction. However, this method has a disadvantage. In order to implement it, it is necessary to use three encryptors/decryptors that work in parallel. At the same time, in order to implement the developed method, it is necessary to double the number of tables for SubBytes and MixColumns, as well as introduce 2 additional shift registers modulo the control module and 8 adders modulo two.
The results of the evaluation of the redundant RCPR were obtained by iterating over all possible code combinations containing single, double and triple errors. The error syndrome was calculated according to (24) for each such combination. Then equal syndromes were selected. Obtaining such syndromes, EDCU will not be able to correct the distorted residues.
Figure 9a shows the capabilities of the developed method using the correction algorithm (22)–(24) and the method [
84] for detecting errors caused by failures that occur during the operation of AES encryption system. The analysis of
Figure 9a shows that the method [
84] makes it possible to detect 100% of single and 75% of double errors. A single error is a distortion of one digit of the code combination caused by the first failure of the equipment. If a second failure or failure occurs, a double error occurs. The developed method provides detection of 100% of single and double errors, as well as 75% of triple errors.
Since the method [
84] does not allow for error correction, a comparative analysis of the developed method will be carried out by AES encryption system using the duplication method. An analysis of
Figure 9b shows that the duplication method makes it possible to fend off 100% of single errors. If a second failure occurs, AES encryption system, which uses the duplication method, fails and cannot ensure cybersecurity during data exchange. The developed method makes it possible to effectively deal with the flow of failures that occur during the operation of AES encryption system. It fends off 100% of single errors caused by the first failure, as well as 100% of errors when the second failure occurs, as well as 75% of errors when the third failure occurs.
To assess the impact of the developed method on the overall delay of AES encryption, a prototyped model of a fault-tolerant encryptor based on Artix-7 FPGA (xc7a12ticsg325-1L) was implemented. Comparisons were made with a prototyped encryptor model using the classical AES encryption algorithm. Computer-aided design Xilinx Vivado-HLS 2018 was used in order to study the built models. The hardware costs for the implementation of these models are presented in
Table 3.
A comparative analysis was conducted on a single round of encryption. The following were selected as the initial data:
The plaintext that consists of 128 bits.
The plaintext in the form of bytes represented in a hexadecimal system: 30 28 00 54 5B D0 87, 08, 7B 87 09 1E 86 0A.
The key that consists of 128 bits.
The key in the form of bytes represented in a hexadecimal system: 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F.
As a result of the conducted research, the following data were obtained. When implementing the classical encryptor, the time spent on one round of encryption was 330 ns. When using the developed error correction method for RCPR, it took 426 ns to perform one round of encryption. Thus, the time spent on encryption was increased by 96 ns. It means that the delay in performing one round of encryption due to the application of the developed error correction method for RCPR was increased by 1.29 times.
Summarizing the results obtained, the following conclusion can be drawn. The novelty of the developed method lies in the fact that it allows us to correct errors using only one control module of the fourth degree. In [
84], the authors only managed to detect an error in operation of AES encryptor, but not to correct it. In addition, the developed method provides lower hardware costs compared to the projection method [
67] and its modification [
68], the interval-index characteristic calculation method [
69] and MRS method [
70,
71]. Thus, it is obvious that the application of the developed method using the correction algorithm (22)–(24) makes it possible to ensure a constant level of cybersecurity even with two consecutive failures in AES encryption system.