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Article

Low-Power FPGA Implementation of Convolution Neural Network Accelerator for Pulse Waveform Classification

by 1,2,3, 1,2,3,*, 1,3, 1,3, 1,2,3 and 1,2,3
1
Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China
2
School of Electronics, Electrical and Communication Engineering, University of Chinese Academy of Sciences, Beijing 100049, China
3
Beijing Key Laboratory for Next Generation RF Communication Chip Technology, Beijing 100029, China
*
Author to whom correspondence should be addressed.
Algorithms 2020, 13(9), 213; https://doi.org/10.3390/a13090213
Received: 6 July 2020 / Revised: 27 August 2020 / Accepted: 29 August 2020 / Published: 31 August 2020
(This article belongs to the Special Issue Algorithms in Bioinformatics)
In pulse waveform classification, the convolution neural network (CNN) shows excellent performance. However, due to its numerous parameters and intensive computation, it is challenging to deploy a CNN model to low-power devices. To solve this problem, we implement a CNN accelerator based on a field-programmable gate array (FPGA), which can accurately and quickly infer the waveform category. By designing the structure of CNN, we significantly reduce its parameters on the premise of high accuracy. Then the CNN is realized on FPGA and optimized by a variety of memory access optimization methods. Experimental results show that our customized CNN has high accuracy and fewer parameters, and the accelerator costs only 0.714 W under a working frequency of 100 MHz, which proves that our proposed solution is feasible. Furthermore, the accelerator classifies the pulse waveform in real time, which could help doctors make the diagnosis. View Full-Text
Keywords: convolution neural network (CNN); traditional Chinese medicine (TCM); pulse waveform classification; field-programmable gate array (FPGA) convolution neural network (CNN); traditional Chinese medicine (TCM); pulse waveform classification; field-programmable gate array (FPGA)
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MDPI and ACS Style

Chen, C.; Li, Z.; Zhang, Y.; Zhang, S.; Hou, J.; Zhang, H. Low-Power FPGA Implementation of Convolution Neural Network Accelerator for Pulse Waveform Classification. Algorithms 2020, 13, 213. https://doi.org/10.3390/a13090213

AMA Style

Chen C, Li Z, Zhang Y, Zhang S, Hou J, Zhang H. Low-Power FPGA Implementation of Convolution Neural Network Accelerator for Pulse Waveform Classification. Algorithms. 2020; 13(9):213. https://doi.org/10.3390/a13090213

Chicago/Turabian Style

Chen, Chuanglu, Zhiqiang Li, Yitao Zhang, Shaolong Zhang, Jiena Hou, and Haiying Zhang. 2020. "Low-Power FPGA Implementation of Convolution Neural Network Accelerator for Pulse Waveform Classification" Algorithms 13, no. 9: 213. https://doi.org/10.3390/a13090213

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