Chen, C.; Li, Z.; Zhang, Y.; Zhang, S.; Hou, J.; Zhang, H.
Low-Power FPGA Implementation of Convolution Neural Network Accelerator for Pulse Waveform Classification. Algorithms 2020, 13, 213.
https://doi.org/10.3390/a13090213
AMA Style
Chen C, Li Z, Zhang Y, Zhang S, Hou J, Zhang H.
Low-Power FPGA Implementation of Convolution Neural Network Accelerator for Pulse Waveform Classification. Algorithms. 2020; 13(9):213.
https://doi.org/10.3390/a13090213
Chicago/Turabian Style
Chen, Chuanglu, Zhiqiang Li, Yitao Zhang, Shaolong Zhang, Jiena Hou, and Haiying Zhang.
2020. "Low-Power FPGA Implementation of Convolution Neural Network Accelerator for Pulse Waveform Classification" Algorithms 13, no. 9: 213.
https://doi.org/10.3390/a13090213
APA Style
Chen, C., Li, Z., Zhang, Y., Zhang, S., Hou, J., & Zhang, H.
(2020). Low-Power FPGA Implementation of Convolution Neural Network Accelerator for Pulse Waveform Classification. Algorithms, 13(9), 213.
https://doi.org/10.3390/a13090213