Next Article in Journal
Defacement Detection with Passive Adversaries
Next Article in Special Issue
A Survey of Convolutional Neural Networks on Edge with Reconfigurable Computing
Previous Article in Journal
Variational Calculus Approach to Optimal Interception Task of a Ballistic Missile in 1D and 2D Cases
Previous Article in Special Issue
A New Method of Applying Data Engine Technology to Realize Neural Network Control
Open AccessFeature PaperArticle

Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using OpenCL

1
Department of Electronics and Information Systems, Ghent University, 9052 Ghent, Belgium
2
Department of Telecommunications and Information Processing, imec-IPI-Ghent University, 9000 Ghent, Belgium
*
Author to whom correspondence should be addressed.
Algorithms 2019, 12(8), 149; https://doi.org/10.3390/a12080149
Received: 27 June 2019 / Revised: 23 July 2019 / Accepted: 25 July 2019 / Published: 27 July 2019
(This article belongs to the Special Issue High Performance Reconfigurable Computing)
Intel recently introduced the Heterogeneous Architecture Research Platform, HARP. In this platform, the Central Processing Unit and a Field-Programmable Gate Array are connected through a high-bandwidth, low-latency interconnect and both share DRAM memory. For this platform, Open Computing Language (OpenCL), a High-Level Synthesis (HLS) language, is made available. By making use of HLS, a faster design cycle can be achieved compared to programming in a traditional hardware description language. This, however, comes at the cost of having less control over the hardware implementation. We will investigate how OpenCL can be applied to implement a real-time guided image filter on the HARP platform. In the first phase, the performance-critical parameters of the OpenCL programming model are defined using several specialized benchmarks. In a second phase, the guided image filter algorithm is implemented using the insights gained in the first phase. Both a floating-point and a fixed-point implementation were developed for this algorithm, based on a sliding window implementation. This resulted in a maximum floating-point performance of 135 GFLOPS, a maximum fixed-point performance of 430 GOPS and a throughput of HD color images at 74 frames per second. View Full-Text
Keywords: field-programmable gate arrays; OpenCL; high-performance computing; guided image filter field-programmable gate arrays; OpenCL; high-performance computing; guided image filter
Show Figures

Figure 1

MDPI and ACS Style

Faict, T.; D’Hollander, E.H.; Goossens, B. Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using OpenCL. Algorithms 2019, 12, 149. https://doi.org/10.3390/a12080149

AMA Style

Faict T, D’Hollander EH, Goossens B. Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using OpenCL. Algorithms. 2019; 12(8):149. https://doi.org/10.3390/a12080149

Chicago/Turabian Style

Faict, Thomas; D’Hollander, Erik H.; Goossens, Bart. 2019. "Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using OpenCL" Algorithms 12, no. 8: 149. https://doi.org/10.3390/a12080149

Find Other Styles
Note that from the first issue of 2016, MDPI journals use article numbers instead of page numbers. See further details here.

Article Access Map by Country/Region

1
Search more from Scilit
 
Search
Back to TopTop