OFF-State Leakage Suppression in Vertical Electron–Hole Bilayer TFET Using Dual-Metal Left-Gate and N⁺-Pocket

Abstract

In this paper, an In_0.53Ga_0.47As electron–hole bilayer tunnel field-effect transistor (EHBTFET) with a dual-metal left-gate and an N⁺-pocket (DGNP-EHBTFET) is proposed and systematically studied by means of numerical simulation. Unlike traditional transverse EHBTFETs, the proposed DGNP-EHBTFET can improve device performance without sacrificing the chip density, and can simplify the manufacturing process. The introduction of the dual-metal left-gate and the N⁺-pocket can shift the point-tunneling junction and adjust the energy band and the electric field in it, aiming to substantially degrade the OFF-state current (I_OFF) and maintain good ON-state performance. Moreover, the line tunneling governed by the tunneling-gate and the right-gate can further regulate and control I_OFF. By optimizing various parameters related to the N⁺-pocket and the gate electrodes, DGNP-EHBTFET’s I_OFF is reduced by at least four orders of magnitude, it has a 75.1% decreased average subthreshold swing compared with other EHBTFETs, and it can maintain a high ON-state current. This design greatly promotes the application potential of EHBTFETs.

1. Introduction

As the feature size enters the nanoscale and continues to shrink, the increasing static power consumption in metal-oxide-semiconductor field-effect transistors (MOSFETs) places restrictions on the development of integrated circuits. To continue Moore’s law, the static power consumption of devices must be further reduced. Limited by the injection mechanism of thermal emission for MOSFETs, an effective method to solve this problem is to develop steep subthreshold swing (SS) devices. One of the mainstream switching devices with steep SS, the tunneling field-effect transistor (TFET) [1,2,3], has the potential to achieve a low operating voltage by overcoming the thermally limited SS of 60 mV/decade by utilizing tunneling as a switching mechanism, and has attracted extensive attention due to its low-power-consumption feature. Si-based TFETs can take advantage of the existing semiconductor design and manufacturing infrastructure, and has thus become the research mainstream of TFETs. However, a low ON-state current (I_ON) caused by the inherent material properties of silicon restricts the practical commercial use of TFETs. Therefore, various TFETs with novel materials or structures have emerged to improve I_ON, such as nanowire TFETs [4,5,6], heterojunction TFETs [6,7,8,9,10], dopingless and junctionless TFETs [4,9,11,12,13,14,15], line-tunneling (LT) TFETs [15,16,17,18,19,20,21,22,23], two-dimensional material TFETs [24,25,26], etc. Among them, an electron–hole bilayer TFET (EHBTFET) [15,18,19,20,21,22,23] based on LT can boost I_ON due to having a larger tunneling region, and has been developed in recent years.

To conserve the total momentum in tunneling, III-V direct band gap materials do not have to involve phonons, which is more beneficial to the improvement of TFET performance than an indirect band gap semiconductor material such as silicon. By analyzing TFETs related to III-V materials in previous publications [9,11,14], it is confirmed that InGaAs is one of the candidate materials suitable for the design of N-type TFETs. In particular, In_0.53Ga_0.47As has a low effective electron mass, a narrow band gap, ultra-high electron mobility, and lattice matching with InP substrate, which has been widely used in the low-power-consumption applications [27,28]. Similarly, it can be employed as the bulk material of EHBTFETs to further improve I_ON [29,30]. Nevertheless, the band-to-band tunneling leakage in the OFF-state caused by point tunneling (PT) in In_0.53Ga_0.47As-based EHBTFETs can result in a higher OFF-state current (I_OFF) compared with Si-based ones, which will increase SS so as to increase the static power consumption of devices. To circumvent this issue, Alper et al. [31] have proposed a novel EHBTFET where counterdoping is carried out in the underlap regions. However, to maintain the same I_ON, the gate voltage (V_gs) needs to be increased to 2.6 V, which is unfavorable for low-power-consumption applications. To obtain low I_OFF, another technique [32] can be employed, that is, the high-K dielectric pocket is inserted into the underlap regions near the source and the drain regions, but it is only applicable to EHBTFETs with a transverse structure. The I_ON of transverse EHBTFETs directly depends on the gate overlap area, which will restrict the reduction in the lateral size of the device. In addition, the manufacturing process of transverse EHBTFETs is complicated, which will cause a reduction in the product yield rate in fabrication.

In this paper, an In_0.53Ga_0.47As EHBTFET with a dual-metal left-gate and an N⁺-pocket (DGNP-EHBTFET) is proposed to effectively solve the aforementioned problem. The proposed DGNP-EHBTFET has a vertical structure, which can improve I_ON by enlarging the gate overlap region in the vertical direction without sacrificing the chip density. Meanwhile, the realization of the asymmetric double-gate structure in DGNP-EHBTFET does not need the transfer substrate technique used in transverse EHBTFETs, thereby simplifying the manufacturing process. The introduction of the dual-metal left-gate can not only make the PT junction deviate from the gate overlap region, but also adjust the electric field profiles at the tunneling junction, both of which are conducive to reducing I_OFF. The N⁺-pocket inserted into the gate underlap region near the drain can regulate and control the tunneling energy range and the tunneling distance of PT, which is beneficial to further decreasing I_OFF but can maintain a good I_ON. Moreover, I_OFF is also affected by LT that is governed by the work-function of the tunneling-gate and the right-gate. Until now, since there are relatively few studies on the OFF-state leakage suppression of vertical EHBTFETs, it is necessary for the device mechanism of the proposed novel structure to be revealed.

This paper is organized as follows. Section 2 introduces the device structures, the related physical parameters and models, and the manufacturing process. The operating mechanism, the direct current (DC) characteristics for the three EHBTFETs, as well as the effects of the N⁺-pocket and the work-function of the gate electrodes on DGNP-EHBTFET are thoroughly investigated in Section 3. Finally, Section 4 briefly summarizes the present studies.

2. Devices Structure and Simulation Methods

To better reveal the device mechanism of the proposed DGNP-EHBTFET, two other EHBTFETs are introduced in this paper: (1) an In_0.53Ga_0.47As EHBTFET with a dual-metal left-gate (DG-EHBTFET) and (2) an In_0.53Ga_0.47As EHBTFET with an N⁺-pocket (NP-EHBTFET). Cross-sectional views of these three vertical-structure EHBTFETs and a 3D schematic of DGNP-EHBTFET are shown in Figure 1, and the corresponding structural parameters are listed in

Table 1. Device structure parameters used in simulations.

Parameters	Value
Bulk material width (W)	6 nm
N+-pocket width (Wp)	2 nm
N+-pocket length (Lp)	50 nm
Drain length (LD)	50 nm
Source length (LS)	50 nm
Tunneling-gate length (LTG)	50 nm
Control-gate length (LCG)	50 nm
Right-gate length (LRG)	100 nm
HfO2 length (LHfO2)	150 nm
SiO2 length (LSiO2)	100 nm
Dielectric width near gate (Wox)	2 nm
Tunneling-gate work-function (ΦTG)	4.5 eV
Control-gate work-function (ΦCG)	5.0 eV
Right-gate work-function (ΦRG)	5.5 eV

.

For these three EHBTFETs, the structural parts are the same except for the left-gate and the channel region connected to the drain region. The left-gates of DG-EHBTFET and DGNP-EHBTFET are composed of a tunneling-gate (TG) and a control-gate (CG) tied directly, while that of NP-EHBTFET is only TG, and the N⁺-pocket connected with the drain region only exists in NP-EHBTFET and DGNP-EHBTFET. Based on the charge plasma concept [33,34], chromium with a work-function of 4.5 eV [35] is employed as TG to form an electron layer in the left-side channel near TG (i.e., the “N” region in Figure 1), and rhenium formed at a specified pressure and temperature (work-function = 5.5 eV) [36] can be picked as the grounded right-gate (RG) to create a hole layer in the right-side channel near RG (i.e., “P” region in Figure 1), so as to provide conditions for LT parallel to the gate electric field. To enhance electron tunneling and effectively suppress gate leakage and the ambipolar current, a HfO₂/SiO₂ heterogate dielectric is adopted in the proposed EHBTFET, which is widely used in TFETs [9,11,14]. Moreover, P-type doping with a concentration of 1 × 10¹⁹ cm⁻³ is carried out in the source region, while N-type doping with a concentration of 1 × 10¹⁹ cm⁻³ and 2 × 10¹⁹ cm⁻³ is performed in the drain region and the N⁺-pocket, respectively. Except for the source, the drain, and the N⁺-pocket regions, the other parts of the channel are intrinsic. In simulations, some key material parameters for In_0.53Ga_0.47As—the band gap, heavy-hole effective mass, light-hole effective mass, and electron effective mass—are 0.751 eV, 0.457 m₀, 0.052 m₀, and 0.042 m₀, respectively [30,37].

The Silvaco Atlas 2D numerical simulation platform is used for all device simulations. To more accurately model the tunneling process, the non-local band-to-band (BTBT) tunneling model is adopted, which considers the spatial variation in the energy bands. The Lombardi mobility model with a remote coulomb scattering term is employed to account for the mobility degradation that occurs inside the inversion layers. Considering that the introduction of the HfO₂ dielectric will generate a large number of traps at the HfO₂/InGaAs interface, we adopt the trap-assisted tunneling model in simulations, and a single donor trap level is assumed near the valence band with an interface trap density of 1 × 10¹³ cm⁻² eV⁻¹. The limitation of this approach is that it cannot reflect the effect of the midlevel position of traps, which may over- or under-estimate SS and I_OFF. In light of the quantum confinement effect in a thin channel layer, we adopt the density gradient model. Additionally, the Shockley–Read–Hall and Auger recombination models, drift-diffusion current transport model, bandgap-narrowing models, Fermi–Dirac carrier statistics, and Schenk oxide-tunneling model are included in the simulations. For these three EHBTFETs, corresponding physical quantities used for revealing some physical mechanisms can be extracted along cutlines A–A’, B–B’, and C–C’ (see dotted lines in Figure 1c), respectively. During data processing, I_OFF and I_ON are extracted from the transfer characteristic curves in the OFF-state (V_gs = 0 V and V_ds = 0.5 V) and ON-state (V_gs = 1 V and V_ds = 0.5 V), respectively.

The proposed DGNP-EHBTFET can be manufactured by state-of-the-art process technology. A brief process flow for obtaining DGNP-EHBTFET is as follows. In stage (1), the In_0.53Ga_0.47As epitaxial layer is grown vertically on InP substrate using the molecular-beam epitaxy technique. P⁺-source, N⁺-pocket, and N⁺-drain are formed via ion implantation. Then, the epitaxial layer is etched using reactive ion etching or inductively coupled plasma etching in stage (2). To obtain the required N⁺-pocket and channel width, the key process focuses on the accurate design of the mask pattern. In stage (3), HfO₂ can be deposited using the atomic layer deposition technique, followed by the etching of dielectrics and metal electrode deposition in stage (4). Finally, SiO₂ deposition is carried out in stage (5). Moreover, to reduce the interface trap in real operation, good quality of the HfO₂/InGaAs interface should be possessed, which can be realized through adoption of the Al₂O₃/HfO₂ stack and the assurance of a good manufacturing process [38,39].

3. Results and Discussion

3.1. Operating Mechanism of Three EHBTFETs

The operating mechanisms of NP-EHBTFET, DG-EHBTFET, and DGNP-EHBTFET can be interpreted using the non-local e-BTBT tunneling rate. For a clear explanation, we simulate the non-local e-BTBT tunneling rates for these three EHBTFETs from the perspective of vertical tunneling and lateral tunneling, respectively, with the results are shown in Figure 2 and Figure 3. Figure 2 shows the vertical non-local e-BTBT tunneling rate in the OFF-state. It is observed that vertical tunneling (see black arrows) appears above the gate overlap region between TG and RG for NP-EHBTFET (see black dotted circles ➀ and ➁). It is because of the existence of N⁺-pocket that the energy band of this region bends downward, so as to provide conditions for vertical tunneling. As shown in Figure 2b, the CG in DG-EHBTFET can induce holes in its right-side region, which forms a PN junction between this region and the drain region, and eventually results in vertical tunneling in black dotted circles ➂ and ➃. Figure 2c shows that the vertical tunneling of DGNP-EHBTFET mainly occurs in black dotted circles ➄ and ➅, and its non-local e-BTBT tunneling rate is lower than that of NP-EHBTFET and DG-EHBTFET. Thus, it can be seen that the simultaneous introduction of the CG and N⁺-pocket in DGNP-EHBTFET contributes to the suppression of vertical tunneling in the OFF-state. This is mainly due to their regulation of electron and hole concentrations in the gate underlap region near the drain. Since there is no lateral tunneling in these EHBTFETs in the OFF-state, it is concluded that vertical tunneling dominates in this state.

It is observed from Figure 3 that the distribution ranges of vertical tunneling for these three EHBTFETs (see green dotted circles in Figure 3a–c) are basically the same in the ON-state, which is due to the fact that V_gs applied to TG turns on electron tunneling in the left side of the source and the gate overlap region near RG. As shown in Figure 3d–f, since the TG and RG are the same for these three EHBTFETs, an identical electron–hole bilayer can be induced in the gate overlap region. In the ON-state, electrons tunnel from the valence band of the hole layer into the conduction band of the electron layer under the action of V_gs. Therefore, lateral tunneling (see white arrows in Figure 3d–f) also exists in these three EHBTFETs. Through comparison, we can see that the region available for vertical tunneling is only a few nanometers wide, so can be named PT, while that for lateral tunneling covers the entire gate overlap region (50 nm in length), so can be named LT. Combining the non-local e-BTBT tunneling rate of these two types of tunneling, it follows that LT dominates in the ON-state but PT does in the OFF-state.

3.2. Comparison of DC Performance among Three EHBTFETs

To compare DC performance, the transfer characteristics of DG-EHBTFET, NP-EHBTFET, and DGNP-EHBTFET are calculated and plotted in Figure 4. It is found from the figure that the I_OFF of the proposed DGNP-EHBTFET is 3.54 × 10⁻¹⁵ A/μm, which is about four and nine orders of magnitude lower than that of DG-EHBTFET and NP-EHBTFET (9.9 × 10⁻¹¹ A/μm and 1.97 × 10⁻⁶ A/μm), respectively. The I_ON of DGNP-EHBTFET is close to 1.92 × 10⁻⁵ A/μm, almost the same magnitude as that of NP-EHBTFET but higher than that of DG-EHBTFET. Therefore, the maximum I_ON/I_OFF can be obtained by DGNP-EHBTFET, and its value is 5.42 × 10⁹.

The tunneling current depends on the tunneling probability (P_tun), which can be expressed as Equation (1) [14]

$$\begin{array}{ll}{P}_{\mathrm{tun}}\propto \exp \left(-\frac{4\lambda \sqrt{2m*}{E}_{\mathrm{g}}^{3/2}}{3\left|e\right|ħ(E_{\mathrm{g}}+\Delta \phi )}\right)& =\exp \left(-\frac{4\sqrt{2m*}{E}_{\mathrm{g}}^{3/2}}{3\left|e\right|ħE}\right)\\ & =\exp \left(-\frac{4\sqrt{2m*}{E}_{\mathrm{g}}^{3/2}}{3\left|e\right|ħ(E_{\mathrm{g}}+\Delta \phi )}\sqrt{\frac{{\epsilon }_{\mathrm{sem}}}{{\epsilon }_{\mathrm{die}}}{t}_{\mathrm{sem}}{t}_{\mathrm{die}}}\right)\end{array}$$

(1)

where Δφ is the energy range used for carrier tunneling, E is the electric field, m* is the effective carrier mass, λ is the tunneling distance, E_g is the band gap, and ε_die, ε_sem, t_die, and t_sem are the permittivity and the thickness of the dielectric and the bulk material, respectively. Since P_tun is closely related to Δφ and E, we can interpret the difference between I_OFF and I_ON for these three EHBTFETs based on them.

Figure 5 shows the energy band and the electric field profiles extracted along cutlines A–A’, B–B’, and C–C, respectively, in the OFF- and ON-states. To explain the physical mechanism more clearly, six regions (i.e., regions I to VI) are defined in the figures of this paper. This is because two kinds of tunneling mechanisms (PT and LT) exist in these three EHBTFETs, which occur in different regions based on different devices and states (see Figure 2 and Figure 3). As shown in Figure 5a, in the OFF-state, PT in NP-EHBTFET occurs in regions I and III, while that in DG- and DGNP-EHBTFETs occurs in regions II and IV. This is because the alignment of the conduction band and the valence band in these regions makes the energy range Δφ (named Δφ₁ to Δφ₆ in regions I to VI, respectively) that is available for carrier tunneling exist in regions I and III of NP-EHBTFET and regions II and IV of the other two EHBTFETs, respectively. Actually, the position of Δφ in DG-EHBTFET and DGNP-EHBTFET is different from that in NP-EHBTFET because the introduction of the control-gate CG lifts the energy band near it so as to shift the tunneling junction to the right. Moreover, for DGNP-EHBTFET, the simultaneous introduction of the CG and the N⁺-pocket can optimize its energy band profiles in four regions, which makes it have the narrowest Δφ. For further analysis, the electric field profiles in the OFF-state are calculated and plotted in Figure 5b. Since tunneling cannot occur in the regions without Δφ, we only compare E at the tunneling junctions of the four regions (see dotted circles in Figure 5b). It is observed that E at the tunneling junction of regions I and II is basically the same, but is very different in regions III and IV, so it can be inferred that the difference in P_tun mainly depends on E in regions III and IV. Obviously, DGNP-EHBTFET possesses the lowest E of the tunneling junction. The lower the E and the narrower the Δφ, the lower the P_tun of DGNP-EHBTFET that can be obtained, according to Equation (1). Furthermore, in the OFF-state, the energy band and the electric field profiles based on LT are also calculated, as shown in Figure 5c. It is found that the identical Es exist in the region V for these three EHBTFETs, which can be explained by Equation (2), expressed as

$$E=\frac{E_{\mathrm{g}}+\Delta \phi }{\lambda }=\frac{E_{\mathrm{g}}+\Delta \phi }{\sqrt{\frac{{\epsilon }_{\mathrm{sem}}}{{\epsilon }_{\mathrm{die}}}{t}_{\mathrm{sem}}{t}_{\mathrm{die}}}}$$

(2)

Since the gate overlap region for these three EHBTFETs has the same dielectric and bulk materials, the same t_die, t_sem, ε_die, ε_sem, and E_g are possessed in this region. Moreover, Figure 5c shows that there is no Δφ available for LT. According to Equation (2), the same E should exist in region V. Although there is E in region V, Δφ is absent; thus, no LT appears. It is thus clear that PT is dominant in the OFF-state, eventually resulting in DGNP-EHBTFET with the lowest I_OFF.

To investigate I_ON, the energy band profiles in the ON-state are calculated and shown in Figure 5d. It is seen that PT occurs in regions III and VI simultaneously because the applied V_gs bends down the energy bands in both regions. Due to the existence of CG, the energy bands of DG-EHBTFET are lifted obviously in regions I and III. The elevated energy band in region I hinders the tunneling electrons drifting to the drain, while that in region III reduces Δφ₃ and increases λ₃ so as to directly weaken the carrier tunneling, both of which lead to a reduction in the I_ON of DG-EHBTFET. Since the introduction of the N⁺-pocket can lower the energy bands in regions I and III, a high I_ON can be maintained in DGNP-EHBTFET like in NP-EHBTFET. In the ON-state, the existence of Δφ (see Δφ₅ in Figure 5e) enhances the E of LT, which is consistent with the result in Equation (2). However, unlike E in the OFF-state, E in regions A and B (see dotted circles in Figure 5e) in the ON-state further increases. This is because PT also affects the E of LT in the gate overlap region. It is observed from Figure 5d that the raised energy band in region I of DG-EHBTFET causes a large number of tunneling electrons from region VI to concentrate in the gate overlap region near TG, eventually resulting in the highest E in its region A. However, the existence of the N⁺-pocket bends the energy band downward in region III for NP-EHBTFET and DGNP-EHBTFET, which is more conducive to the accumulation of holes in the gate overlap region near RG, leading to a higher presence of E in region B (i.e., tunneling junction) of these two EHBTFETs. The higher the E, the higher the I_ON that can be obtained. Therefore, the I_ON of three EHBTFETs results in the aforementioned results.

The average subthreshold swing (SS_avg) is obtained using Equation (3) [9,14]

SS_avg = (V_th − V_OFF)/(log I_Vth − log I_VOFF),

(3)

where the subthreshold voltage (V_th) represents V_gs at which the drain current (I_ds) equals 0.1 μA/μm (i.e., I_Vth), V_OFF is V_gs at which I_ds begins to increase with V_gs, and I_VOFF is the corresponding I_ds when V_gs = V_OFF. It is found from Figure 4 that neither the V_th nor SS_avg of NP-EHBTFET can be extracted because NP-EHBTFET has been turned on in the OFF-state. Thus, only the values of SS_avg and V_th for DG-EHBTFET and DGNP-EHBTFET are compared here. The V_th and SS_avg of DGNP-EHBTFET are 0.17 V and 22.8 mV/decade, respectively, which are reduced by 57.5% and 75.1%, respectively, compared with DG-EHBTFET. Moreover, DGNP-EHBTFET exhibits V_OFF and I_VOFF values approaching 0 V and 3.54 × 10⁻¹⁵ A/μm, respectively, lower than those of DG-EHBTFET. In particular, its I_VOFF is four orders of magnitude lower than that of DG-EHBTFET, which is because PT, known from the previous analysis, is dominant in the OFF-state. For these two EHBTFETs, LT begins to operate when V_gs is applied to the left-gate, and its influence on I_ds starts to exceed PT when V_gs > 0.06 V (see I_ds distortion in the purple circles in Figure 4). Since the introduction of the N⁺-pocket can enhance the built-in electric field in the electron–hole bilayer so as to boost the P_tun of LT, I_Vth can be achieved under lower V_th for DGNP-EHBTFET, which is consistent with the results in Figure 4. As a result, a smaller difference between V_th and V_OFF and a greater one between I_Vth and I_VOFF exists in DGNP-EHBTFET, leading to a lower SS_avg in it. Point SS at each I_ds is expressed as dV_gs/d(logI_ds). To clearly exhibit the change in SS, point SS values are extracted from the transfer characteristic curves and plotted in Figure 5f. Note that the point SS values of NP-EHBTFET cannot be extracted, and the reason is the same as for SS_avg extraction. It is observed from the figure that the proposed DGNP-EHBTFET has steeper point SS when V_gs < V_th, and its minimum point SS is as low as 1.1 mV/decade. Based on above analyses, DGNP-EHBTFET possesses better DC performance.

3.3. Effect of N⁺-Pocket on DGNP-EHBTFET

Figure 6a shows the transfer characteristics of DGNP-EHBTFET with the N⁺-pocket having a different N-type doping concentration (N⁺D). It is found from the figure that I_OFF decreases first, and then, increases with the increase in N⁺D, and achieves the minimum value at N⁺D = 2 × 10¹⁹ cm⁻³. To interpret the variation in I_OFF, the energy band profiles in the OFF-state are calculated and shown in Figure 6b. It is observed from Δφ that PT appears in regions II and IV when N⁺D ≤ 2 × 10¹⁹ cm⁻³ while the same occurs in region III when N⁺D > 2 × 10¹⁹ cm⁻³. With the increase in N⁺D, both Δφ₂ and Δφ₄ decrease but Δφ₃ increases. Though P_tun can be reduced by narrowing Δφ to obtain a lower I_OFF, λ (named λ₁ to λ₆ in regions I to VI, respectively) should also be taken into account according to Equation (1). Unlike λ in region III, those in regions II and IV increase with N⁺D, and their lengths are greater. Hence, one can see that the maximum λ and the minimum Δφ simultaneously exist when N⁺D = 2 × 10¹⁹ cm⁻³, thereby resulting in the minimum P_tun based on Equation (1), eventually obtaining the minimum I_OFF. In fact, the change in the trend of I_OFF is dependent on the position of the PT junction (see black dotted circles in Figure 6b). Since CG can induce holes in the top gate underlap region, PN junctions available for tunneling (i.e., the PT junction in regions II and IV) can be created between this region and the drain region. With there is an increase in N⁺D, the increasing electrons in the top gate underlap region bend the energy band downward so as to reduce the aligned energy range for tunneling, eventually degrading I_OFF. When N⁺D > 2 × 10¹⁹ cm⁻³, the PT junction shifts to region III because a new PN junction is formed by electron accumulation in the top gate underlap region and hole accumulation in the gate overlap region near RG. With the further increase in N⁺D, more electrons gather in the top gate underlap region, which enlarges Δφ so as to promote the electron tunneling. Therefore, I_OFF exhibits an increasing trend. Moreover, further investigation reveals that there is basically no impact of the variation in N⁺D on LT in the OFF-state. With the increase in N⁺D, I_ON values exhibit a similar trend of linear increase and are in the same order of magnitude, which is because the electric field at the LT junction is slightly adjusted with the change in N⁺D on the basis of the same electron–hole bilayer. It can also be found from Figure 6a that the lower the V_gs, the greater the influence of N⁺D on I_ds. This is because at low V_gs, LT mainly depends on the built-in electric field in the electron–hole bilayer, which can be enhanced with an increase in N⁺D. A stronger built-in electric field will cause a higher P_tun of LT so as to turn on DGNP-EHBTFET more easily. Therefore, with the increase in N⁺D, V_th takes on a linear decreasing trend, except that it cannot be extracted when N⁺D = 5 × 10¹⁹ cm⁻³. I_ON/I_OFF exhibits the opposite trend to I_OFF, and approaches the maximum value of 5.42 × 10⁹ at N⁺D = 2 × 10¹⁹ cm⁻³. Benefiting from the minimum I_VOFF and the low V_th, the minimum SS_avg is reached when N⁺D = 2 × 10¹⁹ cm⁻³. As a result, the optimal device performance can be obtained at N⁺D = 2 × 10¹⁹ cm⁻³.

Next, the influence of the width of the N⁺-pocket (W_p) on the DC performance is studied. Figure 7a shows the transfer characteristic curves of DGNP-EHBTFET at W_p = 1~4 nm, from which various DC parameters such as I_OFF, V_th, SS_avg, etc., can be extracted. By compromising these extracted parameters, it follows that DGNP-EHBTFET possesses the optimal DC performance at W_p = 2 nm. Meanwhile, it is found that Figure 7a and Figure 6a have the same change trend in different cases, which is because W_p and N⁺D have identical mechanisms of influence on DGNP-EHBTFET. For example, it is observed from Figure 7b that PT occurs in regions II and IV when W_p ≤ 2 nm, while it occurs in region III when W_p > 2 nm. Similarly, DGNP-EHBTFET is of the maximum λ and the minimum Δφ at W_p = 2 nm, which makes it have the minimum I_OFF under this condition. As shown in Figure 7c, the energy bands in regions I and III gradually bend downward with the increase in W_p, which promotes the drift of tunneling electrons in region VI and the tunneling of electrons in region III, respectively. However, a slight influence of W_p on LT is dominant in the ON-state; thus, I_ON increases with W_p but has the same order of magnitude.

3.4. Effect of Gate Work-Function on DGNP-EHBTFET

Here, we investigate the effect of the work-functions of the right-gate RG, the tunneling-gate TG, and the control-gate CG (i.e., Φ_RG, Φ_TG, and Φ_CG, respectively) on DGNP-EHBTFET, respectively.

Table 2. Extracted parameters from transfer characteristic curves at Φ_RG = 5.0~5.8 eV.

ΦRG (eV)	IOFF (A/μm)	ION (A/μm)	ION/IOFF	Vth (V)	SSavg (mV/dec)
5.0	1.50 × 10−19	1.87 × 10−8	1.25 × 1011	N/A	N/A
5.2	1.15 × 10−18	1.20 × 10−6	1.04 × 1012	0.52	30.7
5.4	2.59 × 10−17	5.79 × 10−6	2.24 × 1011	0.32	33.4
5.5	3.54 × 10−15	1.92 × 10−5	5.42 × 109	0.17	22.8
5.6	2.58 × 10−9	2.87 × 10−5	1.11 × 104	0.14	88.1
5.8	5.16 × 10−9	4.30 × 10−5	8.33 × 103	0.11	85.4

shows the extracted parameters at Φ_RG = 5.0~5.8 eV. It is found that I_OFF maintains a relatively low value at Φ_RG ≤ 5.5 eV, but boosts sharply by six orders of magnitude with the further increase in Φ_RG, which can be seen in the energy band profiles. As shown in Figure 8a, PT occurs in regions II and IV is exactly the same under different Φ_RG levels. Moreover, because the hole concentration near RG increases with Φ_RG so as to lift the energy bands in region III, PT can also take place in this region when Φ_RG > 5.5 eV. Since narrow Δφ and wide λ exist in these tunneling regions, the effect of Φ_RG on PT is insignificant in the OFF-state. Furthermore, it is observed from Figure 8b that LT is opened in region V when Φ_RG > 5.5 eV. According to the changing trend of I_OFF, it can be concluded that when Φ_RG > 5.5 eV, the rapid increase in I_OFF is mainly caused by LT. Figure 8c,d show the energy band profiles in the ON-state regarding PT and LT, respectively. It is seen that with the decrease in Φ_RG, Δφ reduces but λ increases in regions III, V, and VI, particularly when Φ_RG = 5.0 eV, and there is no tunneling in region III. Therefore, I_ON shows a monotonic decreasing trend with the reduction in Φ_RG and achieves the minimum value at Φ_RG = 5.0 eV. Both SS_avg and V_th cannot be extracted at Φ_RG = 5.0 eV as DGNP-EHBTFET is still turned off, even when V_gs = 1.0 V. Note that parameters that cannot be extracted in this paper are all represented by N/A. Moreover, with the increase in Φ_RG, I_ON/I_OFF represents a trend of increasing first, and then, decreasing, and V_th exhibits the opposite trend to I_ON. By comparing these parameters, we assume that DGNP-EHBTFET can maintain better device performance when Φ_RG = 5.5 eV.

Table 3. Extracted parameters from transfer characteristic curves at Φ_TG = 3.5~5.5 eV.

ΦTG (eV)	IOFF (A/μm)	ION (A/μm)	ION/IOFF	Vth (V)	SSavg (mV/dec)
3.5	1.64 × 10−7	2.19 × 10−5	1.34 × 102	N/A	N/A
4.0	7.87 × 10−8	2.11 × 10−5	2.68 × 102	0.02	192.3
4.4	7.90 × 10−9	1.99 × 10−5	2.52 × 103	0.12	108.9
4.5	3.54 × 10−15	1.92 × 10−5	5.42 × 109	0.17	22.8
4.6	8.51 × 10−15	1.81 × 10−5	2.13 × 109	0.24	33.9
5.0	1.03 × 10−13	9.93 × 10−6	9.64 × 107	0.48	80.2
5.5	6.86 × 10−13	3.43 × 10−6	5.00 × 106	0.51	98.8

lists the parameters extracted from the transfer characteristic curves at different Φ_TG levels. It is found that with the increase in Φ_TG, I_OFF decreases first, and then, increases, and obtains the minimum value when Φ_TG = 4.5 eV. To explain in detail, the energy band profiles of LT and PT are calculated. As shown in Figure 9a, when Φ_TG < 4.5 eV, the accumulation of a large number of electrons near TG opens LT in the OFF-state; thus, the I_OFF values are much higher than that in other cases. In addition, with the increase in Φ_TG, Δφ₅ decreases and λ₅ increases, resulting in a gradual reduction in I_OFF. When Φ_TG ≥ 4.5 eV, I_OFF is dependent on PT, which makes it have a substantial reduction. Since Φ_TG just affects the carrier concentration of the gate overlap region (i.e., region V), only the energy bands in this region and the regions connected to it will be adjusted with the change in Φ_TG. It is observed from Figure 9b that the energy bands in region III lift with the increase in Φ_TG, and a new PT appears in this region when Φ_TG > 4.6 eV; therefore, I_OFF begins to increase obviously. It is found from Figure 9c that when Φ_TG < 5.5 eV, LT is dominant in the ON-state, and I_ON shows a slowly decreasing trend with increasing Φ_TG based on the variation in Δφ₅ and λ₅. It is worth noting that only PT exists when Φ_TG = 5.5 eV, and it appears in regions I and III (not shown). As a result, the minimum I_ON is obtained at this Φ_TG. Furthermore, the optimal values of I_ON/I_OFF and SS_avg can be obtained at Φ_TG = 4.5 eV. Comprehensive analysis shows that Φ_TG = 4.5 eV is the best choice for DGNP-EHBTFET.

Further, the influence of Φ_CG on DGNP-EHBTFET is examined, and parameters related to DC performance are extracted and listed in

Table 4. Extracted parameters from transfer characteristic curves at Φ_CG = 3.5~5.5 eV.

ΦCG (eV)	IOFF (A/μm)	ION (A/μm)	ION/IOFF	Vth (V)	SSavg (mV/dec)
3.5	1.47 × 10−5	4.57 × 10−5	3.11 × 100	N/A	N/A
4.0	3.43 × 10−6	3.79 × 10−5	1.10 × 101	N/A	N/A
4.5	9.13 × 10−8	2.90 × 10−5	3.18 × 102	0.02	506
4.9	4.39 × 10−12	2.13 × 10−5	4.85 × 106	0.14	32.1
5.0	3.54 × 10−15	1.92 × 10−5	5.42 × 109	0.17	22.8
5.1	4.96 × 10−15	1.68 × 10−5	3.39 × 109	0.23	31.5
5.5	7.04 × 10−10	6.37 × 10−6	9.05 × 103	0.52	105

. As shown in Figure 10a, since the variation in Φ_CG can adjust the energy band profiles in regions I to IV, the region where PT appears varies with Φ_CG. Because tunneling only exists in the regions with Δφ, we only compare E at the tunneling junction to explain the changing trend of I_OFF. As shown in Figure 10b, when Φ_CG < 4.5 eV, high E exists simultaneously at the tunneling junction of regions I and III, which results in a high I_OFF and turns on DGNP-EHBTFET in the OFF-state. When Φ_CG > 4.5 eV, E at the tunneling junction of regions II and IV increases with Φ_CG, and there is also high E at the tunneling junction of region III at Φ_CG = 4.9 eV. As a result, I_OFF decreases first, and then, increases, and achieves the minimum I_OFF at Φ_CG = 5.0 eV. It is observed from Figure 10c that PT in region VI is insensitive to the change in Φ_CG, but the energy band in region I elevates with the increase in Φ_CG; especially when Φ_CG > 4.5 eV it begins to hinder the drift of the tunneling electrons, eventually degrading device performance in the ON-state. Moreover, with the increase in Φ_CG, E in the tunneling junction of region III gradually weakens, which reduces the P_tun of PT. As shown in Figure 10d, the varying trend of E at the LT junction of region V is the same as that in region III, thereby lowering the P_tun of LT with increasing Φ_CG. Therefore, I_ON decreases with the increase in Φ_CG, which is consistent with the results in Table 4. Furthermore, by comparison of the extracted parameters in Table 4, it follows that DGNP-EHBTFET can obtain optimal device performance only when Φ_CG = 5.0 eV.

4. Conclusions

In conclusion, an In_0.53Ga_0.47As electron–hole bilayer TFET with a dual-metal left-gate and an N⁺-pocket is proposed and investigated in detail using the Silvaco Atlas 2D numerical simulation platform. The numerical simulations demonstrate that the simultaneous introduction of the control-gate and the N⁺-pocket for the proposed DGNP-EHBTFET can optimize the energy band profiles in the tunneling regions so as to substantially degrade the OFF-state current and maintain good ON-state performance. Further, the impact of the N⁺-pocket on DGNP-EHBTFET is investigated, and the results show that both N⁺D and W_p focus on the adjustment of the tunneling energy range and the tunneling distance of PT, thereby mainly affecting I_OFF. By compromise of the extracted various parameters, the optimal DC performance can be obtained when N⁺D = 2 × 10¹⁹ cm⁻³ and W_p = 2 nm. Considering the change in Φ_RG and Φ_TG, it is observed that both can control LT and PT through the regulation of the carrier concentration in the overlap region, and comprehensive analysis illustrates that only when Φ_RG = 5.5 eV and Φ_TG = 4.5 eV can good device performance be maintained. Furthermore, the investigation shows that the variation in Φ_CG can not only change the electric field of the tunneling junction, but it can also regulate and control the drift of tunneling electrons. The results show that Φ_CG = 5.0 eV is the best choice for better DC performance. This paper focuses on revealing the OFF-state leakage suppression mechanism and optimizing the device parameters, without considering the static and dynamic behavior of the proposed DGNP-EHBTFET. In view of their importance, we will put emphasis on this aspect in our next work.