OFF-State Leakage Suppression in Vertical Electron–Hole Bilayer TFET Using Dual-Metal Left-Gate and N+-Pocket

In this paper, an In0.53Ga0.47As electron–hole bilayer tunnel field-effect transistor (EHBTFET) with a dual-metal left-gate and an N+-pocket (DGNP-EHBTFET) is proposed and systematically studied by means of numerical simulation. Unlike traditional transverse EHBTFETs, the proposed DGNP-EHBTFET can improve device performance without sacrificing the chip density, and can simplify the manufacturing process. The introduction of the dual-metal left-gate and the N+-pocket can shift the point-tunneling junction and adjust the energy band and the electric field in it, aiming to substantially degrade the OFF-state current (IOFF) and maintain good ON-state performance. Moreover, the line tunneling governed by the tunneling-gate and the right-gate can further regulate and control IOFF. By optimizing various parameters related to the N+-pocket and the gate electrodes, DGNP-EHBTFET’s IOFF is reduced by at least four orders of magnitude, it has a 75.1% decreased average subthreshold swing compared with other EHBTFETs, and it can maintain a high ON-state current. This design greatly promotes the application potential of EHBTFETs.


Introduction
As the feature size enters the nanoscale and continues to shrink, the increasing static power consumption in metal-oxide-semiconductor field-effect transistors (MOSFETs) places restrictions on the development of integrated circuits. To continue Moore's law, the static power consumption of devices must be further reduced. Limited by the injection mechanism of thermal emission for MOSFETs, an effective method to solve this problem is to develop steep subthreshold swing (SS) devices. One of the mainstream switching devices with steep SS, the tunneling field-effect transistor (TFET) [1][2][3], has the potential to achieve a low operating voltage by overcoming the thermally limited SS of 60 mV/decade by utilizing tunneling as a switching mechanism, and has attracted extensive attention due to its low-power-consumption feature. Si-based TFETs can take advantage of the existing semiconductor design and manufacturing infrastructure, and has thus become the research mainstream of TFETs. However, a low ON-state current (I ON ) caused by the inherent material properties of silicon restricts the practical commercial use of TFETs. Therefore, various TFETs with novel materials or structures have emerged to improve I ON , such as nanowire TFETs [4][5][6], heterojunction TFETs [6][7][8][9][10], dopingless and junctionless TFETs [4,9,[11][12][13][14][15], line-tunneling (LT) TFETs [15][16][17][18][19][20][21][22][23], two-dimensional material TFETs [24][25][26], etc. Among them, an electron-hole bilayer TFET (EHBTFET) [15,[18][19][20][21][22][23] based on LT can boost I ON due to having a larger tunneling region, and has been developed in recent years.
To conserve the total momentum in tunneling, III-V direct band gap materials do not have to involve phonons, which is more beneficial to the improvement of TFET performance than an indirect band gap semiconductor material such as silicon. By analyzing TFETs

Devices Structure and Simulation Methods
To better reveal the device mechanism of the proposed DGNP-EHBTFET, two other EHBTFETs are introduced in this paper: (1) an In 0.53 Ga 0.47 As EHBTFET with a dualmetal left-gate (DG-EHBTFET) and (2) an In 0.53 Ga 0.47 As EHBTFET with an N + -pocket (NP-EHBTFET). Cross-sectional views of these three vertical-structure EHBTFETs and a 3D schematic of DGNP-EHBTFET are shown in Figure 1, and the corresponding structural parameters are listed in Table 1.
For these three EHBTFETs, the structural parts are the same except for the left-gate and the channel region connected to the drain region. The left-gates of DG-EHBTFET and DGNP-EHBTFET are composed of a tunneling-gate (TG) and a control-gate (CG) tied directly, while that of NP-EHBTFET is only TG, and the N + -pocket connected with the drain region only exists in NP-EHBTFET and DGNP-EHBTFET. Based on the charge plasma concept [33,34], chromium with a work-function of 4.5 eV [35] is employed as TG to form an electron layer in the left-side channel near TG (i.e., the "N" region in Figure 1), and (d) A 3D schematic of DGNP-EHBTFET. Cutlines A-A' and B-B' are located at 0.5 nm on the right side of the left-gate dielectric and the left side of the right-gate dielectric, respectively, and cutline C-C' is located in the middle of the tunneling-gate.

Parameters
Value Bulk material width (W) 6   The Silvaco Atlas 2D numerical simulation platform is used for all device simulations. To more accurately model the tunneling process, the non-local band-to-band (BTBT) tunneling model is adopted, which considers the spatial variation in the energy bands. The Lombardi mobility model with a remote coulomb scattering term is employed to account for the mobility degradation that occurs inside the inversion layers. Considering that the introduction of the HfO 2 dielectric will generate a large number of traps at the HfO 2 /InGaAs interface, we adopt the trap-assisted tunneling model in simulations, and a single donor trap level is assumed near the valence band with an interface trap density of 1 × 10 13 cm −2 eV −1 . The limitation of this approach is that it cannot reflect the effect of the midlevel position of traps, which may overor under-estimate SS and I OFF . In light of the quantum confinement effect in a thin channel layer, we adopt the density gradient model. Additionally, the Shockley-Read-Hall and Auger recombination models, drift-diffusion current transport model, bandgap-narrowing models, Fermi-Dirac carrier statistics, and Schenk oxide-tunneling model are included in the simulations. For these three EHBTFETs, corresponding physical quantities used for revealing some physical mechanisms can be extracted along cutlines A-A', B-B', and C-C' (see dotted lines in Figure 1c), respectively. During data processing, I OFF and I ON are extracted from the transfer characteristic curves in the OFF-state (V gs = 0 V and V ds = 0.5 V) and ON-state (V gs = 1 V and V ds = 0.5 V), respectively. The proposed DGNP-EHBTFET can be manufactured by state-of-the-art process technology. A brief process flow for obtaining DGNP-EHBTFET is as follows. In stage (1), the In 0.53 Ga 0.47 As epitaxial layer is grown vertically on InP substrate using the molecular-beam epitaxy technique. P + -source, N + -pocket, and N + -drain are formed via ion implantation. Then, the epitaxial layer is etched using reactive ion etching or inductively coupled plasma etching in stage (2). To obtain the required N + -pocket and channel width, the key process focuses on the accurate design of the mask pattern. In stage (3), HfO 2 can be deposited using the atomic layer deposition technique, followed by the etching of dielectrics and metal electrode deposition in stage (4). Finally, SiO 2 deposition is carried out in stage (5). Moreover, to reduce the interface trap in real operation, good quality of the HfO 2 /InGaAs interface should be possessed, which can be realized through adoption of the Al 2 O 3 /HfO 2 stack and the assurance of a good manufacturing process [38,39].

Operating Mechanism of Three EHBTFETs
The operating mechanisms of NP-EHBTFET, DG-EHBTFET, and DGNP-EHBTFET can be interpreted using the non-local e-BTBT tunneling rate. For a clear explanation, we simulate the non-local e-BTBT tunneling rates for these three EHBTFETs from the perspective of vertical tunneling and lateral tunneling, respectively, with the results are shown in Figures 2 and 3. Figure 2 shows the vertical non-local e-BTBT tunneling rate in the OFF-state. It is observed that vertical tunneling (see black arrows) appears above the gate overlap region between TG and RG for NP-EHBTFET (see black dotted circles x and y). It is because of the existence of N + -pocket that the energy band of this region bends downward, so as to provide conditions for vertical tunneling. As shown in Figure 2b, the CG in DG-EHBTFET can induce holes in its right-side region, which forms a PN junction between this region and the drain region, and eventually results in vertical tunneling in black dotted circles z and {. Figure 2c shows that the vertical tunneling of DGNP-EHBTFET mainly occurs in black dotted circles | and }, and its non-local e-BTBT tunneling rate is lower than that of NP-EHBTFET and DG-EHBTFET. Thus, it can be seen that the simultaneous introduction of the CG and N + -pocket in DGNP-EHBTFET contributes to the suppression of vertical tunneling in the OFF-state. This is mainly due to their regulation of electron and hole concentrations in the gate underlap region near the drain. Since there is no lateral tunneling in these EHBTFETs in the OFF-state, it is concluded that vertical tunneling dominates in this state.

Operating Mechanism of Three EHBTFETs
The operating mechanisms of NP-EHBTFET, DG-EHBTFET, and DGNP-EHBTFET can be interpreted using the non-local e-BTBT tunneling rate. For a clear explanation, we simulate the non-local e-BTBT tunneling rates for these three EHBTFETs from the perspective of vertical tunneling and lateral tunneling, respectively, with the results are shown in Figures 2 and 3. Figure 2 shows the vertical non-local e-BTBT tunneling rate in the OFF-state. It is observed that vertical tunneling (see black arrows) appears above the gate overlap region between TG and RG for NP-EHBTFET (see black dotted circles ➀ and ➁). It is because of the existence of N + -pocket that the energy band of this region b-

Operating Mechanism of Three EHBTFETs
The operating mechanisms of NP-EHBTFET, DG-EHBTFET, and DGNP-EHBTFET can be interpreted using the non-local e-BTBT tunneling rate. For a clear explanation, we simulate the non-local e-BTBT tunneling rates for these three EHBTFETs from the perspective of vertical tunneling and lateral tunneling, respectively, with the results are shown in Figures 2 and 3. Figure 2 shows the vertical non-local e-BTBT tunneling rate in the OFF-state. It is observed that vertical tunneling (see black arrows) appears above the gate overlap region between TG and RG for NP-EHBTFET (see black dotted circles ➀ and ➁). It is because of the existence of N + -pocket that the energy band of this region b-   It is observed from Figure 3 that the distribution ranges of vertical tunneling for these three EHBTFETs (see green dotted circles in Figure 3a-c) are basically the same in the ON-state, which is due to the fact that V gs applied to TG turns on electron tunneling in the left side of the source and the gate overlap region near RG. As shown in Figure 3d-f, since the TG and RG are the same for these three EHBTFETs, an identical electron-hole bilayer can be induced in the gate overlap region. In the ON-state, electrons tunnel from the valence band of the hole layer into the conduction band of the electron layer under the action of V gs . Therefore, lateral tunneling (see white arrows in Figure 3d-f) also exists in these three EHBTFETs. Through comparison, we can see that the region available for vertical tunneling is only a few nanometers wide, so can be named PT, while that for lateral tunneling covers the entire gate overlap region (50 nm in length), so can be named LT.
Combining the non-local e-BTBT tunneling rate of these two types of tunneling, it follows that LT dominates in the ON-state but PT does in the OFF-state.

Comparison of DC Performance among Three EHBTFETs
To compare DC performance, the transfer characteristics of DG-EHBTFET, NP-EHBTFET, and DGNP-EHBTFET are calculated and plotted in Figure 4. It is found from the figure that the I OFF of the proposed DGNP-EHBTFET is 3.54 × 10 −15 A/µm, which is about four and nine orders of magnitude lower than that of DG-EHBTFET and NP-EHBTFET (9.9 × 10 −11 A/µm and 1.97 × 10 −6 A/µm), respectively. The I ON of DGNP-EHBTFET is close to 1.92 × 10 −5 A/µm, almost the same magnitude as that of NP-EHBTFET but higher than that of DG-EHBTFET. Therefore, the maximum I ON /I OFF can be obtained by DGNP-EHBTFET, and its value is 5.42 × 10 9 .
DGNP-EHBTFET mainly occurs in black dotted circles ➄ and ➅, and its non-local e-BTBT tunneling rate is lower than that of NP-EHBTFET and DG-EHBTFET. Thus, it can be seen that the simultaneous introduction of the CG and N + -pocket in DGNP-EHBTFET contributes to the suppression of vertical tunneling in the OFF-state. This is mainly due to their regulation of electron and hole concentrations in the gate underlap region near the drain. Since there is no lateral tunneling in these EHBTFETs in the OFF-state, it is concluded that vertical tunneling dominates in this state.
It is observed from Figure 3 that the distribution ranges of vertical tunneling for these three EHBTFETs (see green dotted circles in Figures 3a-c) are basically the same in the ON-state, which is due to the fact that Vgs applied to TG turns on electron tunneling in the left side of the source and the gate overlap region near RG. As shown in Figures 3d-f, since the TG and RG are the same for these three EHBTFETs, an identical electron-hole bilayer can be induced in the gate overlap region. In the ON-state, electrons tunnel from the valence band of the hole layer into the conduction band of the electron layer under the action of Vgs. Therefore, lateral tunneling (see white arrows in Figures 3d-f) also exists in these three EHBTFETs. Through comparison, we can see that the region available for vertical tunneling is only a few nanometers wide, so can be named PT, while that for lateral tunneling covers the entire gate overlap region (50 nm in length), so can be named LT.
Combining the non-local e-BTBT tunneling rate of these two types of tunneling, it follows that LT dominates in the ON-state but PT does in the OFF-state.

Comparison of DC Performance among Three EHBTFETs
To compare DC performance, the transfer characteristics of DG-EHBTFET, NP-EHBTFET, and DGNP-EHBTFET are calculated and plotted in Figure 4. It is found from the figure that the IOFF of the proposed DGNP-EHBTFET is 3.54 × 10 −15 A/μm, which is about four and nine orders of magnitude lower than that of DG-EHBTFET and NP-EHBT-FET (9.9 × 10 −11 A/μm and 1.97 × 10 −6 A/μm), respectively. The ION of DGNP-EHBTFET is close to 1.92 × 10 −5 A/μm, almost the same magnitude as that of NP-EHBTFET but higher than that of DG-EHBTFET. Therefore, the maximum ION/IOFF can be obtained by DGNP-EHBTFET, and its value is 5.42 × 10 9 . The tunneling current depends on the tunneling probability (P tun ), which can be expressed as Equation (1) where ∆ϕ is the energy range used for carrier tunneling, E is the electric field, m* is the effective carrier mass, λ is the tunneling distance, E g is the band gap, and ε die , ε sem , t die , and t sem are the permittivity and the thickness of the dielectric and the bulk material, respectively. Since P tun is closely related to ∆ϕ and E, we can interpret the difference between I OFF and I ON for these three EHBTFETs based on them. Figure 5 shows the energy band and the electric field profiles extracted along cutlines A-A', B-B', and C-C, respectively, in the OFF-and ON-states. To explain the physical mechanism more clearly, six regions (i.e., regions I to VI) are defined in the figures of this paper. This is because two kinds of tunneling mechanisms (PT and LT) exist in these three EHBTFETs, which occur in different regions based on different devices and states (see Figures 2 and 3). As shown in Figure 5a, in the OFF-state, PT in NP-EHBTFET occurs in regions I and III, while that in DG-and DGNP-EHBTFETs occurs in regions II and IV. This is because the alignment of the conduction band and the valence band in these regions makes the energy range ∆ϕ (named ∆ϕ 1 to ∆ϕ 6 in regions I to VI, respectively) that is available for carrier tunneling exist in regions I and III of NP-EHBTFET and regions II and IV of the other two EHBTFETs, respectively. Actually, the position of ∆ϕ in DG-EHBTFET and DGNP-EHBTFET is different from that in NP-EHBTFET because the introduction of the control-gate CG lifts the energy band near it so as to shift the tunneling junction to the right. Moreover, for DGNP-EHBTFET, the simultaneous introduction of the CG and the N + -pocket can optimize its energy band profiles in four regions, which makes it have the narrowest ∆ϕ. For further analysis, the electric field profiles in the OFF-state are calculated and plotted in Figure 5b. Since tunneling cannot occur in the regions without ∆ϕ, we only compare E at the tunneling junctions of the four regions (see dotted circles in Figure 5b). It is observed that E at the tunneling junction of regions I and II is basically the same, but is very different in regions III and IV, so it can be inferred that the difference in P tun mainly depends on E in regions III and IV. Obviously, DGNP-EHBTFET possesses the lowest E of the tunneling junction. The lower the E and the narrower the ∆ϕ, the lower the P tun of DGNP-EHBTFET that can be obtained, according to Equation (1). Furthermore, in the OFF-state, the energy band and the electric field profiles based on LT are also calculated, as shown in Figure 5c. It is found that the identical Es exist in the region V for these three EHBTFETs, which can be explained by Equation (2), expressed as To investigate ION, the energy band profiles in the ON-state are calculated and shown in Figure 5d. It is seen that PT occurs in regions III and VI simultaneously because the applied Vgs bends down the energy bands in both regions. Due to the existence of CG, the energy bands of DG-EHBTFET are lifted obviously in regions I and III. The elevated energy band in region I hinders the tunneling electrons drifting to the drain, while that in region III reduces Δφ3 and increases λ3 so as to directly weaken the carrier tunneling, both Since the gate overlap region for these three EHBTFETs has the same dielectric and bulk materials, the same t die , t sem , ε die , ε sem , and E g are possessed in this region. Moreover, Figure 5c shows that there is no ∆ϕ available for LT. According to Equation (2), the same E should exist in region V. Although there is E in region V, ∆ϕ is absent; thus, no LT appears. It is thus clear that PT is dominant in the OFF-state, eventually resulting in DGNP-EHBTFET with the lowest I OFF .
To investigate I ON , the energy band profiles in the ON-state are calculated and shown in Figure 5d. It is seen that PT occurs in regions III and VI simultaneously because the applied V gs bends down the energy bands in both regions. Due to the existence of CG, the energy bands of DG-EHBTFET are lifted obviously in regions I and III. The elevated energy band in region I hinders the tunneling electrons drifting to the drain, while that in region III reduces ∆ϕ 3 and increases λ 3 so as to directly weaken the carrier tunneling, both of which lead to a reduction in the I ON of DG-EHBTFET. Since the introduction of the N + -pocket can lower the energy bands in regions I and III, a high I ON can be maintained in DGNP-EHBTFET like in NP-EHBTFET. In the ON-state, the existence of ∆ϕ (see ∆ϕ 5 in Figure 5e) enhances the E of LT, which is consistent with the result in Equation (2). However, unlike E in the OFF-state, E in regions A and B (see dotted circles in Figure 5e) in the ON-state further increases. This is because PT also affects the E of LT in the gate overlap region. It is observed from Figure 5d that the raised energy band in region I of DG-EHBTFET causes a large number of tunneling electrons from region VI to concentrate in the gate overlap region near TG, eventually resulting in the highest E in its region A. However, the existence of the N + -pocket bends the energy band downward in region III for NP-EHBTFET and DGNP-EHBTFET, which is more conducive to the accumulation of holes in the gate overlap region near RG, leading to a higher presence of E in region B (i.e., tunneling junction) of these two EHBTFETs. The higher the E, the higher the I ON that can be obtained. Therefore, the I ON of three EHBTFETs results in the aforementioned results.
The average subthreshold swing (SS avg ) is obtained using Equation (3) [9,14] SS avg = (V th − V OFF )/(log I Vth − log I VOFF ), where the subthreshold voltage (V th ) represents V gs at which the drain current (I ds ) equals 0.1 µA/µm (i.e., I Vth ), V OFF is V gs at which I ds begins to increase with V gs , and I VOFF is the corresponding I ds when V gs = V OFF . It is found from Figure 4 that neither the V th nor SS avg of NP-EHBTFET can be extracted because NP-EHBTFET has been turned on in the OFF-state. Thus, only the values of SS avg and V th for DG-EHBTFET and DGNP-EHBTFET are compared here. The V th and SS avg of DGNP-EHBTFET are 0.17 V and 22.8 mV/decade, respectively, which are reduced by 57.5% and 75.1%, respectively, compared with DG-EHBTFET. Moreover, DGNP-EHBTFET exhibits V OFF and I VOFF values approaching 0 V and 3.54 × 10 −15 A/µm, respectively, lower than those of DG-EHBTFET. In particular, its I VOFF is four orders of magnitude lower than that of DG-EHBTFET, which is because PT, known from the previous analysis, is dominant in the OFF-state. For these two EHBTFETs, LT begins to operate when V gs is applied to the left-gate, and its influence on I ds starts to exceed PT when V gs > 0.06 V (see I ds distortion in the purple circles in Figure 4). Since the introduction of the N + -pocket can enhance the built-in electric field in the electron-hole bilayer so as to boost the P tun of LT, I Vth can be achieved under lower V th for DGNP-EHBTFET, which is consistent with the results in Figure 4. As a result, a smaller difference between V th and V OFF and a greater one between I Vth and I VOFF exists in DGNP-EHBTFET, leading to a lower SS avg in it. Point SS at each I ds is expressed as dV gs /d(logI ds ). To clearly exhibit the change in SS, point SS values are extracted from the transfer characteristic curves and plotted in Figure 5f. Note that the point SS values of NP-EHBTFET cannot be extracted, and the reason is the same as for SS avg extraction. It is observed from the figure that the proposed DGNP-EHBTFET has steeper point SS when V gs < V th , and its minimum point SS is as low as 1.1 mV/decade. Based on above analyses, DGNP-EHBTFET possesses better DC performance. Figure 6a shows the transfer characteristics of DGNP-EHBTFET with the N + -pocket having a different N-type doping concentration (N + D). It is found from the figure that I OFF decreases first, and then, increases with the increase in N + D, and achieves the minimum value at N + D = 2 × 10 19 cm −3 . To interpret the variation in I OFF , the energy band profiles in the OFF-state are calculated and shown in Figure 6b. It is observed from ∆ϕ that PT appears in regions II and IV when N + D ≤ 2 × 10 19 cm −3 while the same occurs in region III when N + D > 2 × 10 19 cm −3 . With the increase in N + D, both ∆ϕ 2 and ∆ϕ 4 decrease but ∆ϕ 3 increases. Though P tun can be reduced by narrowing ∆ϕ to obtain a lower I OFF , λ (named λ 1 to λ 6 in regions I to VI, respectively) should also be taken into account according to Equation (1). Unlike λ in region III, those in regions II and IV increase with N + D, and their lengths are greater. Hence, one can see that the maximum λ and the minimum ∆ϕ simultaneously exist when N + D = 2 × 10 19 cm −3 , thereby resulting in the minimum P tun based on Equation (1), eventually obtaining the minimum I OFF . In fact, the change in the trend of I OFF is dependent on the position of the PT junction (see black dotted circles in Figure 6b). Since CG can induce holes in the top gate underlap region, PN junctions available for tunneling (i.e., the PT junction in regions II and IV) can be created between this region and the drain region. With there is an increase in N + D, the increasing electrons in the top gate underlap region bend the energy band downward so as to reduce the aligned energy range for tunneling, eventually degrading I OFF . When N + D > 2 × 10 19 cm −3 , the PT junction shifts to region III because a new PN junction is formed by electron accumulation in the top gate underlap region and hole accumulation in the gate overlap region near RG. With the further increase in N + D, more electrons gather in the top gate underlap region, which enlarges ∆ϕ so as to promote the electron tunneling. Therefore, I OFF exhibits an increasing trend. Moreover, further investigation reveals that there is basically no impact of the variation in N + D on LT in the OFF-state. With the increase in N + D, I ON values exhibit a similar trend of linear increase and are in the same order of magnitude, which is because the electric field at the LT junction is slightly adjusted with the change in N + D on the basis of the same electron-hole bilayer. It can also be found from Figure 6a that the lower the V gs , the greater the influence of N + D on I ds . This is because at low V gs , LT mainly depends on the built-in electric field in the electron-hole bilayer, which can be enhanced with an increase in N + D. A stronger built-in electric field will cause a higher P tun of LT so as to turn on DGNP-EHBTFET more easily. Therefore, with the increase in N + D, V th takes on a linear decreasing trend, except that it cannot be extracted when N + D = 5 × 10 19 cm −3 . I ON /I OFF exhibits the opposite trend to I OFF , and approaches the maximum value of 5.42 × 10 9 at N + D = 2 × 10 19 cm −3 . Benefiting from the minimum I VOFF and the low V th , the minimum SS avg is reached when N + D = 2 × 10 19 cm −3 . As a result, the optimal device performance can be obtained at N + D = 2 × 10 19 cm −3 . decreasing trend, except that it cannot be extracted when N + D = 5 × 10 19 cm −3 . ION/IOFF exhibits the opposite trend to IOFF, and approaches the maximum value of 5.42 × 10 9 at N + D = 2 × 10 19 cm −3 . Benefiting from the minimum IVOFF and the low Vth, the minimum SSavg is reached when N + D = 2 × 10 19 cm −3 . As a result, the optimal device performance can be obtained at N + D = 2 × 10 19 cm −3 . Next, the influence of the width of the N + -pocket (Wp) on the DC performance is studied. Figure 7a shows the transfer characteristic curves of DGNP-EHBTFET at Wp = 1 ~ 4 nm, from which various DC parameters such as IOFF, Vth, SSavg, etc., can be extracted. By compromising these extracted parameters, it follows that DGNP-EHBTFET possesses the optimal DC performance at Wp = 2 nm. Meanwhile, it is found that Figure 7a and   Next, the influence of the width of the N + -pocket (W p ) on the DC performance is studied. Figure 7a shows the transfer characteristic curves of DGNP-EHBTFET at W p = 1~4 nm, from which various DC parameters such as I OFF , V th , SS avg , etc., can be extracted. By compromising these extracted parameters, it follows that DGNP-EHBTFET possesses the optimal DC performance at W p = 2 nm. Meanwhile, it is found that Figures 7a and 6a have the same change trend in different cases, which is because W p and N + D have identical mechanisms of influence on DGNP-EHBTFET. For example, it is observed from Figure 7b that PT occurs in regions II and IV when W p ≤ 2 nm, while it occurs in region III when W p > 2 nm. Similarly, DGNP-EHBTFET is of the maximum λ and the minimum ∆ϕ at W p = 2 nm, which makes it have the minimum I OFF under this condition. As shown in Figure 7c, the energy bands in regions I and III gradually bend downward with the increase in W p , which promotes the drift of tunneling electrons in region VI and the tunneling of electrons in region III, respectively. However, a slight influence of W p on LT is dominant in the ON-state; thus, I ON increases with W p but has the same order of magnitude. Next, the influence of the width of the N + -pocket (Wp) on the DC performance is studied. Figure 7a shows the transfer characteristic curves of DGNP-EHBTFET at Wp = 1 ~ 4 nm, from which various DC parameters such as IOFF, Vth, SSavg, etc., can be extracted. By compromising these extracted parameters, it follows that DGNP-EHBTFET possesses the optimal DC performance at Wp = 2 nm. Meanwhile, it is found that Figure 7a and Figure  6a have the same change trend in different cases, which is because Wp and N + D have identical mechanisms of influence on DGNP-EHBTFET. For example, it is observed from Figure 7b that PT occurs in regions II and IV when Wp ≤ 2 nm, while it occurs in region III when Wp > 2 nm. Similarly, DGNP-EHBTFET is of the maximum λ and the minimum Δφ at Wp = 2 nm, which makes it have the minimum IOFF under this condition. As shown in Figure 7c, the energy bands in regions I and III gradually bend downward with the increase in Wp, which promotes the drift of tunneling electrons in region VI and the tunneling of electrons in region III, respectively. However, a slight influence of Wp on LT is dominant in the ON-state; thus, ION increases with Wp but has the same order of magnitude.

Effect of Gate Work-Function on DGNP-EHBTFET
Here, we investigate the effect of the work-functions of the right-gate RG, the tunneling-gate TG, and the control-gate CG (i.e., ΦRG, ΦTG, and ΦCG, respectively) on DGNP-

Effect of Gate Work-Function on DGNP-EHBTFET
Here, we investigate the effect of the work-functions of the right-gate RG, the tunnelinggate TG, and the control-gate CG (i.e., Φ RG , Φ TG , and Φ CG , respectively) on DGNP-EHBTFET, respectively. Table 2 shows the extracted parameters at Φ RG = 5.0~5.8 eV. It is found that I OFF maintains a relatively low value at Φ RG ≤ 5.5 eV, but boosts sharply by six orders of magnitude with the further increase in Φ RG , which can be seen in the energy band profiles. As shown in Figure 8a, PT occurs in regions II and IV is exactly the same under different Φ RG levels. Moreover, because the hole concentration near RG increases with Φ RG so as to lift the energy bands in region III, PT can also take place in this region when Φ RG > 5.5 eV. Since narrow ∆ϕ and wide λ exist in these tunneling regions, the effect of Φ RG on PT is insignificant in the OFF-state. Furthermore, it is observed from Figure 8b that LT is opened in region V when Φ RG > 5.5 eV. According to the changing trend of I OFF , it can be concluded that when Φ RG > 5.5 eV, the rapid increase in I OFF is mainly caused by LT. Figure 8c,d show the energy band profiles in the ON-state regarding PT and LT, respectively. It is seen that with the decrease in Φ RG , ∆ϕ reduces but λ increases in regions III, V, and VI, particularly when Φ RG = 5.0 eV, and there is no tunneling in region III. Therefore, I ON shows a monotonic decreasing trend with the reduction in Φ RG and achieves the minimum value at Φ RG = 5.0 eV. Both SS avg and V th cannot be extracted at Φ RG = 5.0 eV as DGNP-EHBTFET is still turned off, even when V gs = 1.0 V. Note that parameters that cannot be extracted in this paper are all represented by N/A. Moreover, with the increase in Φ RG , I ON /I OFF represents a trend of increasing first, and then, decreasing, and V th exhibits the opposite trend to I ON . By comparing these parameters, we assume that DGNP-EHBTFET can maintain better device performance when Φ RG = 5.5 eV.
fore, ION shows a monotonic decreasing trend with the reduction in ΦRG and achieves the minimum value at ΦRG = 5.0 eV. Both SSavg and Vth cannot be extracted at ΦRG = 5.0 eV as DGNP-EHBTFET is still turned off, even when Vgs = 1.0 V. Note that parameters that cannot be extracted in this paper are all represented by N/A. Moreover, with the increase in ΦRG, ION/IOFF represents a trend of increasing first, and then, decreasing, and Vth exhibits the opposite trend to ION. By comparing these parameters, we assume that DGNP-EHBT-FET can maintain better device performance when ΦRG = 5.5 eV.     Table 3 lists the parameters extracted from the transfer characteristic curves at different Φ TG levels. It is found that with the increase in Φ TG , I OFF decreases first, and then, increases, and obtains the minimum value when Φ TG = 4.5 eV. To explain in detail, the energy band profiles of LT and PT are calculated. As shown in Figure 9a, when Φ TG < 4.5 eV, the accumulation of a large number of electrons near TG opens LT in the OFF-state; thus, the I OFF values are much higher than that in other cases. In addition, with the increase in Φ TG , ∆ϕ 5 decreases and λ 5 increases, resulting in a gradual reduction in I OFF . When Φ TG ≥ 4.5 eV, I OFF is dependent on PT, which makes it have a substantial reduction. Since Φ TG just affects the carrier concentration of the gate overlap region (i.e., region V), only the energy bands in this region and the regions connected to it will be adjusted with the change in Φ TG . It is observed from Figure 9b that the energy bands in region III lift with the increase in Φ TG , and a new PT appears in this region when Φ TG > 4.6 eV; therefore, I OFF begins to increase obviously. It is found from Figure 9c that when Φ TG < 5.5 eV, LT is dominant in the ON-state, and I ON shows a slowly decreasing trend with increasing Φ TG based on the variation in ∆ϕ 5 and λ 5 . It is worth noting that only PT exists when Φ TG = 5.5 eV, and it appears in regions I and III (not shown). As a result, the minimum I ON is obtained at this Φ TG . Furthermore, the optimal values of I ON /I OFF and SS avg can be obtained at Φ TG = 4.5 eV. Comprehensive analysis shows that Φ TG = 4.5 eV is the best choice for DGNP-EHBTFET.
just affects the carrier concentration of the gate overlap region (i.e., region V), only the energy bands in this region and the regions connected to it will be adjusted with the change in ΦTG. It is observed from Figure 9b that the energy bands in region III lift with the increase in ΦTG, and a new PT appears in this region when ΦTG > 4.6 eV; therefore, IOFF begins to increase obviously. It is found from Figure 9c that when ΦTG < 5.5 eV, LT is dominant in the ON-state, and ION shows a slowly decreasing trend with increasing ΦTG based on the variation in Δφ5 and λ5. It is worth noting that only PT exists when ΦTG = 5.5 eV, and it appears in regions I and III (not shown). As a result, the minimum ION is obtained at this ΦTG. Furthermore, the optimal values of ION/IOFF and SSavg can be obtained at ΦTG = 4.5 eV. Comprehensive analysis shows that ΦTG = 4.5 eV is the best choice for DGNP-EHBTFET.  Further, the influence of ΦCG on DGNP-EHBTFET is examined, and parameters related to DC performance are extracted and listed in Table 4. As shown in Figure 10a, since the variation in ΦCG can adjust the energy band profiles in regions I to IV, the region where PT appears varies with ΦCG. Because tunneling only exists in the regions with Δφ, we only  Further, the influence of Φ CG on DGNP-EHBTFET is examined, and parameters related to DC performance are extracted and listed in Table 4. As shown in Figure 10a, since the variation in Φ CG can adjust the energy band profiles in regions I to IV, the region where PT appears varies with Φ CG . Because tunneling only exists in the regions with ∆ϕ, we only compare E at the tunneling junction to explain the changing trend of I OFF . As shown in Figure 10b, when Φ CG < 4.5 eV, high E exists simultaneously at the tunneling junction of regions I and III, which results in a high I OFF and turns on DGNP-EHBTFET in the OFF-state. When Φ CG > 4.5 eV, E at the tunneling junction of regions II and IV increases with Φ CG , and there is also high E at the tunneling junction of region III at Φ CG = 4.9 eV. As a result, I OFF decreases first, and then, increases, and achieves the minimum I OFF at Φ CG = 5.0 eV. It is observed from Figure 10c that PT in region VI is insensitive to the change in Φ CG , but the energy band in region I elevates with the increase in Φ CG ; especially when Φ CG > 4.5 eV it begins to hinder the drift of the tunneling electrons, eventually degrading device performance in the ON-state. Moreover, with the increase in Φ CG , E in the tunneling junction of region III gradually weakens, which reduces the P tun of PT. As shown in Figure 10d, the varying trend of E at the LT junction of region V is the same as that in region III, thereby lowering the P tun of LT with increasing Φ CG . Therefore, I ON decreases with the increase in Φ CG , which is consistent with the results in Table 4. Furthermore, by comparison of the extracted parameters in Table 4, it follows that DGNP-EHBTFET can obtain optimal device performance only when Φ CG = 5.0 eV. performance in the ON-state. Moreover, with the increase in ΦCG, E in the tunneling junction of region III gradually weakens, which reduces the Ptun of PT. As shown in Figure  10d, the varying trend of E at the LT junction of region V is the same as that in region III, thereby lowering the Ptun of LT with increasing ΦCG. Therefore, ION decreases with the increase in ΦCG, which is consistent with the results in Table 4. Furthermore, by comparison of the extracted parameters in Table 4, it follows that DGNP-EHBTFET can obtain optimal device performance only when ΦCG = 5.0 eV.

Conclusions
In conclusion, an In 0.53 Ga 0.47 As electron-hole bilayer TFET with a dual-metal left-gate and an N + -pocket is proposed and investigated in detail using the Silvaco Atlas 2D numerical simulation platform. The numerical simulations demonstrate that the simultaneous introduction of the control-gate and the N + -pocket for the proposed DGNP-EHBTFET can optimize the energy band profiles in the tunneling regions so as to substantially degrade the OFF-state current and maintain good ON-state performance. Further, the impact of the N + -pocket on DGNP-EHBTFET is investigated, and the results show that both N + D and W p focus on the adjustment of the tunneling energy range and the tunneling distance of PT, thereby mainly affecting I OFF . By compromise of the extracted various parameters, the optimal DC performance can be obtained when N + D = 2 × 10 19 cm −3 and W p = 2 nm. Considering the change in Φ RG and Φ TG , it is observed that both can control LT and PT through the regulation of the carrier concentration in the overlap region, and comprehen-sive analysis illustrates that only when Φ RG = 5.5 eV and Φ TG = 4.5 eV can good device performance be maintained. Furthermore, the investigation shows that the variation in Φ CG can not only change the electric field of the tunneling junction, but it can also regulate and control the drift of tunneling electrons. The results show that Φ CG = 5.0 eV is the best choice for better DC performance. This paper focuses on revealing the OFF-state leakage suppression mechanism and optimizing the device parameters, without considering the static and dynamic behavior of the proposed DGNP-EHBTFET. In view of their importance, we will put emphasis on this aspect in our next work.