# Memristor-CMOS Hybrid Circuit for Temporal-Pooling of Sensory and Hippocampal Responses of Cortical Neurons

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Proposed Methods

_{0}, m

_{1}, m

_{2}, etc. The temporal/location SDR vectors are connected to the basal/distal dendrites of m

_{3}, m

_{4}, m

_{5}, etc. One thing to note in Figure 4a is that each neuron is allowed to have only a single proximal dendrite. However, for the basal/distal ones, the neuron can have multiple dendrites, as explained in Figure 2. The sensory SDR and temporal/location SDR are collectively received by the input-layer neurons. The column current of the sensory SDR “A” is delivered to C

_{0}, where the column current is converted to a voltage and then compared with the threshold. The detailed schematic of C

_{0}is shown in Figure 4b. Similarly, the column current of “B”’ is delivered to C

_{1}. The temporal/location SDR vectors of “#1”, “#3”, and “#2” generate the row currents which are delivered to C

_{2}, C

_{3}, and C

_{4}, respectively. A

_{0}, A

_{1}, and A

_{2}are the AND gates that combine the sensory information of “A”’ with the temporal/location SDRs of “#1”, “#3”, and “#2”, respectively. The outputs of A

_{0}, A

_{1}, and A

_{2}are represented with i

_{0}, i

_{1}, and i

_{2}, respectively. They enter the pulse-type set-reset latches of L

_{0}, L

_{1}, and L

_{2}, respectively. The pulse-type set-reset latch is shown in Figure 4c. L

_{0}can be set if the SDR “A” and SDR “#1” are recognized at the same time. L

_{1}is set for “A” and “#3”. L

_{2}is switched to the SET state for “A” and “#2”. Similarly, L

_{3}, L

_{4}, and L

_{5}can respond to the input SDR of “B#1”, “B#3”, and “B#2”, respectively. The set-reset latch in Figure 4c is reset by the delayed version of the “EOW_P” pulse from the delay line τ. Here, “EOW_P” means the pulse indicating the end of the word. “EOW_P” is generated when the word ends.

_{1}is activated. Similarly, when the sensory SDR of “B” and the location SDR of “#2” are recognized, Q

_{5}becomes high. When “EOW_P” is activated, the two latches of L

_{1}and L

_{5}keep Q

_{1}and Q

_{5}high, respectively, until the reset. Assuming that the dendritic synapses of the output neuron O

_{0}are already put in the predicted state with “A#3” and “B#2”, m

_{7}and m

_{9}are already programmed LRSs (Low Resistance States) as a result of crossbar training. Here, the solid and open circles represent LRS and HRS (High Resistance State), respectively. At end-of-word, if the row current of k

_{0}is larger than the output-layer neuron’s threshold, O

_{0}becomes high. Actually, we can think that the k

_{0}current represents the integration of temporal responses to the sensory/location SDRs of “A#3” and “B#2” because “A#3” and “B#2’ were already recognized at the previous time. Similarly, if “A#2” and “B#1” are recognized one by one, the row current k

_{1}becomes larger than the threshold and can activate O

_{1}.

_{3}/Nb-doped SrTiO

_{3}stacked layer [35]. Here, the LRS and HRS were measured as 10 kΩ and 1 MΩ, respectively. The black line in Figure 5a represents the behavioral model of memristors [35]. The measured data are represented with the red line. The behavioral model described by Verilog-A was used in the circuit simulation of the hybrid circuits of memristors and CMOS in this paper. Here, the circuit simulation was performed using CADENCE SPECTRE (Cadence Design Systems, Inc., San Jose, CA, USA) and SAMSUNG 0.13-µm circuit simulation parameters [36]. The mathematical equations of the Verilog-A model of memristors were explained in a previous publication in detail [35].

_{0}and IN

_{5}pulses are high, while the others are low in Figure 5b. By doing so, Q

_{1}becomes high. Second, if the spatial pooler generates the sensory SDR of letter “B” and the location SDR “#2”, Q

_{5}becomes high. At end-of-word, the pulse of “EOW_P” is enabled and the output neuron O

_{0}becomes active. Here, the output neuron is already put in the predicted state by the previous signals of Q

_{1}and Q

_{5}. After the output neuron O

_{0}fires a pulse, O

_{0}returns to low, as the typical integrate-and-fire neuron acts. To do so, the “EOW_P” pulse goes through the delay line τ and its delayed pulse resets the set-reset latches. The integrate-and-fire operation is realized very simply using the digital CMOS gates and the memristor crossbar, as shown in Figure 4a–c.

## 3. Results

_{DD}/2 scheme for programming memristors. One thing to note is that the memristor programming based on Hebbian learning does not need the complicated backpropagation calculation [21]. By doing so, the proposed memristor-CMOS hybrid circuit can be very suitable to online learning because the hardware complexity of Hebbian learning is much simpler than that of a backpropagation-based system.

## 4. Discussion

## 5. Conclusions

## Author Contributions

## Funding

## Acknowledgments

## Conflicts of Interest

## References

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**Figure 1.**(

**a**) The functional block diagram of Hierarchical Temporal Memory (HTM): The spatial pooler receives the sensory information from various sensory organs and forms the Sparse Distributed Representation (SDR) output representing the collective cortical neurons activated in response to the sensory information. The temporal memory learns the sequence of items that are represented by the SDR vectors by combining the sensory information with the temporal information. (

**b**) The cross-sectional view of the human brain: Here, the neocortex and hippocampus regions are shown for processing the “what” and “when/where” information, respectively.

**Figure 2.**(

**a**) The conceptual model of temporal memory architecture: The red and blue lines represent the proximal and basal/distal dendrites, respectively. (

**b**) The schematic of a pyramidal neuron with a single proximal dendrite and multiple basal/distal ones. The number of output axons can be multiple too. Here, we showed 4 axons to constitute one mini-column with 4 cells. The pyramidal neurons are known as the majority of neocortical neurons.

**Figure 3.**The conceptual schematic of a temporal-pooling memristor crossbar composed of input-layer and output-layer neurons: The input-layer neuron receives sensory SDR and temporal/location SDR from the spatial pooler and hippocampus model, respectively. The sensory and temporal/location SDR are generated from the spatial-pooling memristor crossbar that was developed in a previous work [21]. The output-layer neuron can perform a prediction by integrating the temporal information through multiple basal/distal dendrites.

**Figure 4.**(

**a**) The schematic of the proposed memristor-CMOS hybrid circuit for the temporal pooling of sequences such as words, sentences, etc: The input layer is composed of the memristor crossbars for sensory and temporal/location SDRs, the current-to-voltage converters, comparators, the AND gates, etc. The output layer is composed of the memristor crossbars, converters, comparators, latches, etc. (

**b**) The schematic of the current–voltage converter and comparator and (

**c**) the schematic of the pulse-type set-reset latch.

**Figure 5.**(

**a**) The current–voltage relationships of memristors for the measurement and Verilog-A model: The black line represents the Verilog-A model of memristors used in the circuit simulation in this paper [35]. The red line is for the measurement [35]. The details of the measurement and the Verilog-A model were explained well in a previous publication [35]. (

**b**) The waveforms of the proposed memristor-CMOS hybrid circuit for temporal pooling shown in Figure 4.

**Figure 6.**The operational steps of simple Hebbian learning of memristor crossbars: initialization, overlap computation, activation and deactivation by thresholding, and permanence updating and memristor programming. Here the memristor programming based on Hebbian learning does not need the complicated backpropagation calculation.

**Figure 7.**The first row shows the EMNIST handwritten letters of “c”, “o”, “m”, and “e”, respectively. The second row shows randomized images of EMIST handwritten letters. The third row are the SDRs that are obtained from the spatial-pooing memristor crossbar for the randomized images of “c”, “o”, “m”, and “e”. The fourth row shows 100 EMNIST input vectors. Each EMNIST vector is composed of 20 × 20 pixels. The fifth row shows 100 SDRs with 16 × 16 bits which are obtained from 100 EMNIST input vectors with 20 × 20 pixels. Among the 16 × 16 bits, only 2% of the bits become active to maintain the sparsity ratio around 2% by spatial-pooling for EMNIST vectors [21].

**Figure 9.**The recognition rate of words by varying the amount of noise added to location SDRs and sensory SDRs: The red circles represent the recognition rate for the noise added to the sensory SDRs. The black boxes are for the noise added to the location SDRs.

**Figure 10.**The recognition rate of words by increasing the percentage variation in memristance from 0% to 15%: The inset figure shows the statistical distribution of LRS and HRS for the memristance variation = 10%.

**Figure 11.**The prediction rate of sentences by increasing the number of words sensed for recognizing the sentences: Here, both the ordinal and out-of-order sequences can be recognized by the temporal-pooling memristor crossbar circuit proposed in this paper.

**Table 1.**A comparison of the memristor crossbar area, power consumption, and prediction of the ordinal and out-of-order sequences.

Scheme | The Previous Sequential Memristor Crossbar [40] | The Proposed Memristor-CMOS Hybrid Circuit of Temporal Pooling |
---|---|---|

The number of memristors (Memristor crossbar area) | 17556 | 17027 |

The amount of power consumption (LRS = 1 MΩ, HRS = 100 MΩ) | 151.5 µW | 5.24 µW |

Prediction of ordinal sequences | O | O |

Prediction of out-of-order sequences | X | O |

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**MDPI and ACS Style**

Nguyen, T.V.; Pham, K.V.; Min, K.-S.
Memristor-CMOS Hybrid Circuit for Temporal-Pooling of Sensory and Hippocampal Responses of Cortical Neurons. *Materials* **2019**, *12*, 875.
https://doi.org/10.3390/ma12060875

**AMA Style**

Nguyen TV, Pham KV, Min K-S.
Memristor-CMOS Hybrid Circuit for Temporal-Pooling of Sensory and Hippocampal Responses of Cortical Neurons. *Materials*. 2019; 12(6):875.
https://doi.org/10.3390/ma12060875

**Chicago/Turabian Style**

Nguyen, Tien Van, Khoa Van Pham, and Kyeong-Sik Min.
2019. "Memristor-CMOS Hybrid Circuit for Temporal-Pooling of Sensory and Hippocampal Responses of Cortical Neurons" *Materials* 12, no. 6: 875.
https://doi.org/10.3390/ma12060875