A Method for Optimizing Turn-Off Losses Design in Parallel MOSFETs Inverter with RC Snubber Circuits

Abstract

Voltage spikes are particularly severe in low-voltage high-current inverters due to the influence of parasitic inductance during the turn-off process. A resistor-capacitor (RC) snubber circuit is commonly connected in parallel with the switching device to suppress excessive voltage overshoot. However, the snubber circuit inevitably introduces additional power losses, making the selection of snubber parameters critical for achieving low-loss operation. In this paper, the voltage spike suppression mechanism of the RC snubber circuit is first analyzed. Then, a comprehensive turn-off loss model is established by considering the MOSFET turn-off loss, the RC snubber loss, and the loss associated with the DC-bus parasitic inductance. Based on the proposed model, the influence of the snubber capacitance on the total turn-off loss is investigated. The results show that an optimal capacitance value exists, with which the total switching loss can be minimized. Finally, both simulation and experimental results are presented to validate the proposed loss model and demonstrate the effectiveness of the optimized snubber capacitance in minimizing inverter turn-off losses.

1. Introduction

In the design of low-voltage, high-current inverters, paralleled MOSFETs are widely used to reduce conduction losses and improve power density [1,2,3]. However, the parasitic inductance of the power loop is difficult to further minimize because of the limitations imposed by device packaging, PCB layout, and busbar structure [4,5]. With increasing switching frequency, the large current slew rate (di/dt) during switching transitions interacts with the parasitic inductance, producing severe voltage spikes during MOSFET turn-off. These spikes reduce the device voltage margin, increase switching losses, and consequently degrade inverter efficiency [6,7,8].

To suppress excessive voltage spikes and reduce transient stress during switching transitions, a resistor–capacitor (RC) snubber circuit is commonly connected in parallel with the bridge arms as a common engineering solution [9,10,11]. The RC snubber circuits provide a low-impedance bypass path for absorbing the transient energy associated with bus parasitic inductance. Therefore, voltage overshoot can be effectively mitigated, and the voltage stress on the switching devices can be reduced [12].

Figure 1 shows a typical parallel MOSFETs switching circuit with an RC snubber circuit, which is used for the equivalent analysis of the MOSFET switching process in the inverter [8]. In this circuit, M1, M3 and M5 are the upper-arm MOSFETs, whilst M2, M4 and M6 are the lower-arm MOSFETs. C_ds, C_gd and C_gs represent the parasitic capacitances of the MOSFETs; C_s and R_s denote the snubber capacitance and resistance of the bridge leg, respectively. L_dc is the bus parasitic inductance; L_load and R_load are the load inductance and resistance; and C_dc is the direct current (DC) bus support capacitance. The generation mechanism of turn-off voltage spikes and the suppression effect of the RC snubber circuit are analyzed in Section 2.

Although RC snubber circuits perform excellently in suppressing voltage spikes, the snubber capacitor is repeatedly charged and discharged during each switching cycle. As a result, part of the transient energy associated with high-frequency oscillation is transferred to the snubber network and dissipated through the snubber resistor, leading to additional switching loss [13,14]. Therefore, the selection of RC parameters involves a trade-off between voltage spike suppression and power dissipation. In particular, the snubber capacitance directly determines the amount of energy absorbed by the snubber circuit for a given voltage variation, while the snubber resistance mainly affects the damping characteristics and discharge process. Accordingly, the capacitance selection plays a dominant role in snubber loss optimization, with the resistance designed to ensure proper energy dissipation and transient damping [15,16].

For system-level loss optimization in low-voltage, high-current inverters, an accurate definition of the loss boundary is essential. Existing studies on RC snubber parameter design mainly focus on the switching energy of MOSFETs or the power loss of the snubber circuit itself [17]. However, under low-voltage and high-current operating conditions, the transient energy associated with the DC-bus parasitic inductance during turn-off also contributes significantly to the total turn-off loss. For system-level loss optimization in low-voltage, high-current inverters, an accurate boundary definition and comprehensive modeling are key to optimizing the design in terms of switching loss. Existing studies on RC snubber parameter design mainly focus on the switching energy of MOSFETs or the power loss of the snubber circuit itself [17]. However, under low-voltage and high-current operating conditions, the transient energy associated with the DC-bus parasitic inductance during turn-off also contributes significantly to the total turn-off loss. This part of the loss is usually not separately considered in snubber parameter optimization.

To address this issue, this paper proposes a total turn-off loss optimization method for a paralleled MOSFET circuit with an RC snubber. A comprehensive loss model is established by incorporating the MOSFET turn-off loss, RC snubber loss, and DC-bus parasitic inductance loss. Based on this model, the influence of the snubber capacitance on the total turn-off loss is clarified, and an optimal capacitance value can be obtained to minimize the inverter turn-off loss.

The rest of this paper is organized as follows. Section 2 analyzes the generation mechanism of turn-off voltage spikes and the suppression effect of RC snubber circuits in parallel MOSFET configurations. Section 3 establishes a comprehensive total turn-off loss model incorporating MOSFET turn-off loss, RC snubber loss, and bus parasitic inductance loss, followed by a simulation validation. Section 4 presents the experimental verification to demonstrate the effectiveness of the proposed loss optimization method. Finally, Section 5 concludes the paper.

2. RC Snubber Circuits in Parallel MOSFET Configuration

2.1. Simplified Analytical Model Development

It is assumed that the three paralleled MOSFETs turn off synchronously. Therefore, for the analysis of the turn-off voltage spike and turn-off losses, the circuit shown in Figure 1 can be further simplified. The corresponding simplified switching circuit is shown in Figure 2.

The circuit simplification mainly focuses on the equivalent representation of the parasitic capacitances of the paralleled MOSFETs. Since the gate-drain capacitance C_gd and drain-source capacitance C_ds are closely related to the turn-off transient, their equivalent values can be expressed as follows:

$$C_{\mathit{gd},n} ={ C}_{\mathit{gd},1} + C_{\mathit{gd},3} +{ C}_{\mathit{gd},5}$$

(1)

$$C_{\mathit{ds},n}=C_{\mathit{ds},1}+{ C}_{\mathit{ds},3}+{ C}_{\mathit{ds},5}$$

(2)

The two parasitic capacitances mentioned above form the MOSFET output capacitance C_oss, as expressed in Equation (3). To simplify the subsequent analysis and calculation, the output capacitance C_oss and the snubber capacitance C_s are further combined into an equivalent capacitance C_eq, as given in Equation (4):

$$C_{\mathit{oss}} ={ C}_{\mathit{gd},n} + C_{\mathit{ds},n}$$

(3)

$$C_{\mathit{eq}}=C_{\mathit{oss}}+{ C}_s$$

(4)

2.2. Analysis of Turn-Off Voltage Spikes

First, during the turn-off transient, the equivalent capacitance C_eq and the bus parasitic inductance L_dc form a resonant network. The relationship between the resonant period and these parameters is given by

$$T_0\propto \sqrt{L_{\mathit{dc}}{C}_{\mathit{eq}}}$$

(5)

As the MOSFET begins to turn off, the channel current I_d commutates to the resonant network formed by C_eq and L_dc over the turn-off duration t_off. The magnitude of the resulting voltage spike, ΔV₁, depends primarily on the ratio of t_off to the resonant period T₀. When $t_{\mathit{off}} \ll \sqrt{L_{\mathit{dc}}{C}_{\mathit{eq}}}$, the energy stored in L_dc cannot dissipate immediately and is entirely converted into electric field energy within C_eq, satisfying

$${\displaystyle \frac{1}{2}}{L}_{\mathit{dc}}{I}_d^2={\displaystyle \frac{1}{2}}{C}_{\mathit{eq}}{\left(∆V_1\right)}^2$$

(6)

Consequently, the resonance-induced voltage spike ΔV₁ can be expressed as

$$∆V_1=I_d\sqrt{{\displaystyle \frac{L_{\mathit{dc}}}{C_{\mathit{eq}}}}}$$

(7)

Additionally, voltage spikes during the MOSFET turn-off transient may be driven by the induced electromotive force (EMF) across the bus parasitic inductance L_dc due to rapid current variations. Assuming a linear decay of the channel current, the rate of change is given by

$$\left|{\displaystyle \frac{\mathit{di}}{\mathit{dt}}}\right|\approx {\displaystyle \frac{I_d}{t_{\mathit{off}}}}$$

(8)

Thus, the EMF-induced voltage spike ΔV₂ is formulated as

$$∆V_2=L_{\mathit{dc}}{\displaystyle \frac{I_d}{t_{\mathit{off}}}}$$

(9)

Under practical operating conditions, the total turn-off voltage spike is a non-linear superposition of these two mechanisms. Analyzed concurrently via an inverse-square relationship, the total voltage spike can be mathematically represented by

$${\displaystyle \frac{1}{∆V^2}}={\displaystyle \frac{1}{∆V_1^2}}+{\displaystyle \frac{1}{∆V_2^2}}={\displaystyle \frac{C_{\mathit{eq}}}{I_d^2{L}_{\mathit{dc}}}}+{\displaystyle \frac{t_{\mathit{off}}^2}{I_d^2{L}_{\mathit{dc}}^2}}={\displaystyle \frac{L_{\mathit{dc}}{C}_{\mathit{eq}}+t_{\mathit{off}}^2}{I_d^2{L}_{\mathit{dc}}^2}}$$

(10)

Simplifying this expression yields

$$∆V={\displaystyle \frac{L_{\mathit{dc}}{I}_{\mathit{dc}}}{\sqrt{t_{\mathit{off}}^2 +L_{\mathit{dc}}{C}_{\mathit{eq}}}}}$$

(11)

Ultimately, the peak drain-to-source voltage spike, V_ds,peak, during the turn-off transient is determined by

$$V_{\mathit{ds},\mathit{peak}}={ V}_{\mathit{dc}}+∆V$$

(12)

where V_dc denotes the nominal DC bus voltage.

As illustrated in Figure 3, the impact of turn-off time and snubber capacitance on the turn-off voltage spike is plotted according to Equation (12). In the extreme scenario of an ultra-short switching time without a snubber capacitor, the transient voltage spike can reach approximately 230 V, despite a nominal bus voltage V_dc of only 56 V. Although power devices are typically selected with voltage ratings well exceeding the bus voltage, spikes of this magnitude will inevitably lead to catastrophic device failure. Therefore, the integration of an RC snubber circuit is essential in this system.

As indicated in Figure 3, shorter turn-off times t_off and smaller snubber capacitances C_s exacerbate the voltage spike generated during MOSFET turn-off. While the spike can be mitigated by extending the turn-off time, this approach prolongs the switching transient and significantly increases turn-off losses. Consequently, artificially increasing the MOSFET turn-off time is rarely adopted in practical applications. Instead, increasing the snubber capacitance effectively suppresses the voltage spike. Although the introduced capacitive path inevitably contributes to switching losses, the capacitance parameters can be optimized. This ensures the voltage spike remains within the safe operating area while concurrently minimizing the overall switching losses of the circuit.

3. Total Turn-Off Loss Modeling of Paralleled MOSFET Circuits with an RC Snubber

3.1. Comprehensive Turn-Off Loss Modeling with MOSFET, RC Snubber, and Bus Inductance Effects

The total switching loss, which accounts for the switching losses of the MOSFET, the RC snubber circuit, and the bus parasitic inductance, is expressed in Equation (13):

$$P_{\mathit{sw}} = \left[E_{\mathit{off}} + C_s{V}_{\mathit{dc}}^2 + {\displaystyle \frac{1}{2}}{L}_{\mathit{dc}}{I}_L^2{\displaystyle \frac{C_{\mathit{oss}}}{C_{\mathit{eq}}}}\right] \times f_{\mathit{sw}}$$

(13)

In Equation (13), the second and third terms denote the losses in the RC snubber circuit and the parasitic inductance, respectively, where f_sw represents the switching frequency. The MOSFET turn-off loss after integrating the RC snubber circuit is defined by Equation (14):

$$E_{\mathit{off} }= {\displaystyle \frac{I_L^2{t}_{\mathit{off}}^2}{24C_{\mathit{eq}}}}$$

(14)

By rearranging Equation (13), the loss component associated with the snubber capacitor C_s can be isolated as a function of C_s:

$$f\left(C_s\right) ={ C}_s{V}_{\mathit{dc} }^2+ {\displaystyle \frac{1}{C_s+C_{\mathit{oss}}}}\left({\displaystyle \frac{I_L^2{t}_{\mathit{off}}^2}{24}} + {\displaystyle \frac{1}{2}}{L}_{\mathit{dc}}{I}_L^2{C}_{\mathit{oss}}\right)$$

(15)

Minimizing the total loss is equivalent to finding the global minimum of the function presented in Equation (15). By setting the derivative of Equation (15) with respect to C_s to zero, the optimal snubber capacitance that minimizes the total switching loss can be determined:

$$\mathit{f}\prime \left(C_s\right) = 0$$

(16)

Thus, the calculated snubber capacitance that theoretically minimizes these losses is formulated in Equation (17):

$$C_{s,\mathit{opt}} = \sqrt{{\displaystyle \frac{I_L^2{t}_{\mathit{off}}^2}{24V_{dc}^2}} + {\displaystyle \frac{L_s{I}_L^2{C}_{\mathit{oss}}}{2V_{dc}^2}}}-C_{\mathit{oss}}$$

(17)

The system parameters—nominal bus voltage V_dc = 56 V, total channel current I_d = 180 A, turn-off time t_off = 70 ns, MOSFET output capacitance C_oss = 6000 pF, and bus parasitic inductance L_dc = 15 nH—are substituted into Equation (17). In particular, the value of L_dc is derived from experimental measurements. The measured waveforms and the calculation formula are presented in detail in Section 4.1. The source of the L_dc value used in the simulation process is also consistent with this. The theoretical relationship between the snubber capacitance C_s and the total switching loss P_sw is plotted in Figure 4.

As observed in Figure 4, a U-shaped relationship exists between the total turn-off loss and the snubber capacitance. Specifically, P_sw initially decreases as C_s increases, reaching a minimum at the optimal capacitance value. Beyond this optimal point, P_sw increases proportionally with further additions to C_s. Based on Equation (17), the theoretical optimal capacitance is calculated to be 23.2 nF.

It is worth noting that while the snubber is an RC-network, the derivation in this paper focuses on the optimization of the capacitance C_s. As previously indicated in the Introduction, C_s determines the absolute amount of transient energy absorbed by the snubber network during each switching cycle, thereby dominating the total loss minimization. The snubber resistance R_s, on the other hand, mainly governs the damping characteristics and the energy dissipation rate rather than the total absorbed energy. In this study, Rs is selected as 1 Ω based on two critical considerations. First, from the perspective of the series RC cut-off frequency ($f_c = 1/(2\mathsf{\pi }{R}_s{C}_s)$), pairing R_s = 1 Ω with an optimal C_s of around 25 nF yields a cut-off frequency of approximately 6 MHz. This ensures that the snubber provides a highly effective, low-impedance bypass path for the high-frequency voltage spikes, while blocking the lower fundamental switching frequencies. Second, regarding overall power dissipation and voltage clamping, an excessively large Rs would produce a significant instantaneous resistive voltage drop during the turn-off transient, exacerbating the peak voltage stress on the MOSFET. Conversely, an overly small Rs would fail to provide sufficient damping, leading to prolonged LC resonant oscillations. The selection of 1 Ω strikes an optimal balance, ensuring rapid thermal dissipation of the trapped energy while strictly maintaining the voltage spike within the safe operating area.

3.2. Simulation Validation

The turn-off losses of the parallel-MOSFETs circuit equipped with an RC snubber were simulated using LTspice. The schematic of the simulated circuit is presented in Figure 5. All simulation parameters align with the theoretical calculations previously discussed. Additionally, the MOSFET drain inductance L_d was set to 2 nH, the source inductance L_s to 8 nH, the DC bus support capacitance C_dc to 30 μF, and the snubber resistance R_s to 1 Ω. A parametric sweep was performed on the snubber capacitance C_s, ranging from 10 nF to 150 nF with a step size of 10 nF.

To ensure high fidelity in the simulation, the SPICE model for IPP030N10N3 was acquired directly from the official Infineon Technologies database. The diodes in the gate drive loop, utilized to accelerate the gate discharge process during turn-off, employ standard fast-switching diode models from the built-in LTSpice library (1N4148). The accuracy of the semiconductor SPICE model parameters profoundly influences the simulation performance and the reliability of the loss estimation. The specific values of drain inductance and source inductance were taken from the device’s datasheet to ensure accuracy.

Figure 6 illustrates the transient behaviors of the MOSFET channel current I_d and the drain-source voltage V_ds during the turn-off transient under varying snubber capacitance C_s. The results indicate that I_d remains largely unaffected by C_s, whereas the peak V_ds at the turn-off instant is notably attenuated as C_s increases. Consequently, the intrinsic turn-off loss of the MOSFET decreases with a larger C_s, as depicted in Figure 7.

Figure 8 and Figure 9 present the transient losses attributed to the bus parasitic inductance L_dc and the RC snubber circuit, respectively, during the turn-off transient. The parasitic inductance loss inversely correlates with the snubber capacitance, whereas the energy dissipation within the RC snubber circuit scales proportionally with C_s. These simulated trends are in robust agreement with the analytical loss model derived in Equation (13).

Table 1. Turn-off losses simulation results.

Cs (nF)	MOSFET Turn-Off Loss (W)	Remaining Turn-Off Loss (W)	Psw (W)	Cs (nF)	MOSFET Turn-Off Loss (W)	Remaining Turn-Off Loss (W)	Psw (W)
10	3.64	1.19	4.82	90	2.16	2.59	4.75
20	2.70	1.29	3.99	100	2.17	2.86	5.03
30	2.34	1.36	3.70	110	2.17	3.13	5.3
40	2.24	1.46	3.71	120	2.17	3.40	5.57
50	2.19	1.64	3.82	130	2.17	3.66	5.83
60	2.17	1.84	4.01	140	2.18	3.92	6.10
70	2.16	2.07	4.23	150	2.18	4.19	6.37
80	2.16	2.33	4.48

summarizes the simulated MOSFET turn-off losses and the remaining turn-off losses (defined as the sum of the parasitic inductance losses and the RC snubber circuit losses). Based on these data, the relationship between C_s and the total switching loss P_sw is plotted in Figure 10. While the intrinsic MOSFET turn-off losses decrease monotonically with an increasing C_s, the remaining turn-off losses exhibit an upward trend.

Consequently, the total turn-off loss curve maintains a characteristic U-shape, reaching an absolute minimum total switching loss at C_s = 30 nF. This optimal value deviates slightly from the theoretically calculated 23.2 nF, primarily because the theoretical model does not incorporate the impact of the MOSFET’s intrinsic parasitic inductances (L_d and L_s). Nevertheless, the overall trend closely mirrors the theoretical predictions, effectively validating the proposed analytical model.

4. Experimental Verification

4.1. Experimental Platform

The experimental verification was conducted using the setup illustrated in Figure 11. The bus capacitance was configured to 30 μF, with a load inductance of 25 nH and an equivalent series resistance of 1 mΩ. The device under test was constructed utilizing six identical MOSFETs (Infineon IPP030N10N3, Munich, Germany) from the same production batch, arranged as previously depicted in Figure 1. An microcontroller (STMicroelectronics STM32F407VGT6, Geneva, Switzerland)served as the core of the control circuit, generating the requisite drive signals for the double-pulse test.

4.2. Measurement of Busbar Parasitic Inductance

During the MOSFET turn-off transient, the channel current I_d decreases rapidly. According to the fundamental inductive voltage relationship ΔV = L*di/dt, the busbar parasitic inductance L_dc induces a significant voltage overshoot. The drain-source voltage V_ds and channel current I_d waveforms at the turn-off instant were captured via the double-pulse test. By determining the rate of current change (di/dt) and the peak voltage overshoot ΔV (the portion exceeding the nominal DC bus voltage), the dynamic inductance under actual operating conditions can be evaluated. This measurement implicitly accounts for high-frequency skin and proximity effects. The busbar parasitic inductance is formulated as

$$L_{\mathit{dc}}=\left(V_{\mathit{ds},\mathit{peak}}-V_{\mathit{dc}}\right)/\left(\mathit{di}/\mathit{dt}\right)$$

(18)

Figure 12 presents the experimental waveforms used for this measurement. These waveforms directly reveal the severe effect of the busbar parasitic inductance on the MOSFET dynamic operation. As observed, the high rate of current decline ($\mathit{d}\mathit{i}/\mathit{d}\mathit{t}$) in the channel current I_d (green trace) interacts with the busbar parasitic inductance to induce a strong back-electromotive force. This manifests as a severe voltage spike in the drain-source voltage V_ds (purple trace), peaking at 94 V. Given a nominal bus voltage V_dc of 56 V, the busbar parasitic inductance for this experimental setup was calculated to be 15 nH, according to Equation (18).

4.3. The Effectiveness of RC Snubber Circuits in Suppressing Voltage Spikes

To evaluate the efficacy of the snubber capacitor C_s in suppressing voltage spikes, turn-off transient voltages were measured across varying capacitance values. The parameter C_s was swept from 10 nF to 100 nF in increments of 10 nF. This specific range was established based on prior theoretical calculations and simulation analyses, both of which indicated that the optimal snubber capacitance would fall well below 100 nF for this system. Consequently, values exceeding 100 nF were omitted to streamline the experiment without compromising the validity of the conclusions.

Figure 13 displays the turn-off voltage waveforms for the tested snubber capacitance values. As C_s increases, the peak voltage spike is progressively attenuated. The quantitative relationship between the peak drain-source voltage spike V_ds,peak and the snubber capacitance C_s is further detailed in Figure 14. At the same time, the simulation results shown in Figure 6b have been plotted alongside the experimental data in Figure 14. It can be observed that the experimental and simulation results exhibit consistent trends, indicating that the simulated circuit accurately represents the actual conditions. The values from the simulation are consistently higher than those from the experiments. This is because not all parasitic parameters were taken into consideration during the simulation, resulting in higher voltage spikes in the simulation.

4.4. Measurement of Total Turn-Off Losses

Concurrently with the variation in C_s, the intrinsic MOSFETs turn-off losses and the energy dissipated in the remaining circuit were quantified. Figure 15 depicts the transient I_d and V_ds waveforms for the parallel MOSFETs configuration during the turn-off transient. By comparing these measured results with the simulated waveforms presented earlier in Figure 6, a highly consistent dynamic trend is observed. Specifically, in both the simulation and physical experiment, as the snubber capacitance C_s increases, the peak drain-source voltage V_ds is significantly attenuated, whereas the trajectory of the channel current I_d remains largely unaffected. This strong qualitative agreement effectively verifies the accuracy of the established simulation model in capturing the transient switching dynamics.

The intrinsic turn-off loss is derived by integrating the product of these waveforms over the turn-off duration. A similar integration methodology was applied to determine the losses in the remaining circuit components.

Table 2. Experimental results of turn-off losses.

Cs (nF)	MOSFET Turn-Off Loss (W)	Remaining Turn-Off Loss (W)	Psw (W)	Cs (nF)	MOSFET Turn-Off Loss (W)	Remaining Turn-Off Loss (W)	Psw (W)
10	3.37	1.15	4.52	60	2.16	1.81	3.97
20	2.49	1.27	3.76	70	1.98	1.97	3.94
30	2.23	1.40	3.63	80	2.04	2.17	4.21
40	2.20	1.49	3.69	90	2.12	2.41	4.53
50	2.17	1.68	3.85	100	2.08	2.75	4.83

summarizes the calculated overall turn-off losses under varying C_s values.

Based on the experimental data in Table 2, the relationship between C_s and the total turn-off loss P_sw is plotted in Figure 16. Consistent with both theoretical predictions and simulation results, the intrinsic MOSFET turn-off losses decrease monotonically with an increase in snubber capacitance, whereas the remaining circuit losses exhibit an upward trend. Consequently, the total turn-off loss curve maintains a characteristic U-shape, identifying a minimum total turn-off loss at C_s = 30 nF.

Table 3. Results of turn-off losses under the optimal Cs through different verification methods.

Verification Method	Cs,opt (nF)	Psw,opt (W)
Theoretical calculation	23.2	3.25
Simulation	30	3.70
Experiment	30	3.63

shows the optimal snubber capacitance C_s,opt obtained by the three methods and the corresponding switching losses P_sw,opt. Although the absolute loss values obtained experimentally exhibit minor deviations from the theoretical and simulated figures—primarily due to unmodeled parasitic elements in the physical setup—the overall trend robustly demonstrates that the optimal snubber capacitance derived from the proposed comprehensive loss model effectively minimizes the total turn-off loss under the specified operating conditions.

5. Conclusions

This paper presents a total turn-off loss optimization method for RC-snubber-based parallel MOSFETs in low-voltage, high-current inverters. A comprehensive loss model is established by considering the MOSFET turn-off loss, RC snubber loss, and bus parasitic inductance loss. Based on this model, the influence of the snubber capacitance on the total turn-off loss is clarified. Theoretical analysis, the simulation, and the experimental results show that the total turn-off loss first decreases and then increases with the snubber capacitance, indicating the existence of an optimal capacitance value. Under the tested condition with a bus parasitic inductance of 15 nH, the minimum turn-off energy is achieved when the snubber capacitance is approximately 30 nF. The proposed model provides an effective basis for snubber capacitance selection and low-loss inverter design.

Furthermore, in practical implementations, printed circuit board (PCB) layouts introduce additional parasitic parameters, such as trace inductances and stray capacitances, which can further influence the high-frequency switching transients and amplify voltage spikes. While the current study primarily focuses on the dominant busbar parasitic inductance, meticulously extracting and taking into account the fine PCB parasitic parameters is crucial for highly accurate loss estimation. Future work will focus on integrating comprehensive PCB parasitic parameter models into the loss optimization framework to further enhance the reliability and efficiency of high-power-density inverter designs.