A Computationally Efficient Model Predictive Control for Star-Connected Cascaded Static Synchronous Compensator Under Unbalanced Conditions

Abstract

The conventional model predictive control (MPC) experiences a tremendous number of switching state evaluations per control cycle when applied to multilevel converters, which makes it computationally impractical. To address this issue, this article proposes a computationally efficient MPC (EMPC) for the cascaded H-bridge (CHB) static synchronous compensator (STATCOM), which is enabled by the sorting of the H-bridge submodules upon their dc capacitor voltages, such that the candidate switching states are restricted to the scope in which the lower-voltage submodules are charged and the higher-voltage submodules are discharged. And therefore, the exponentially increasing switching states in the CHB-STATCOM can be dramatically reduced while the computational efficiency is greatly improved. In addition, prior to control implementation, a generic discrete-time prediction model with the incorporation of a zero-sequence component is established to merge the balanced and unbalanced scenarios into one framework, so as to address the issues related to either grid and/or load unbalances in the CHB-STATCOM for distribution grids. Both simulation and hardware-in-loop experimental studies are provided to verify the effectiveness of the EMPC strategy.

1. Introduction

During the past few decades, owing to the tremendous advancement of digital microprocessors, the proliferation of model predictive control (MPC) has been an emerging trend in the control of power converters and motor drives both from academia and industry [1,2,3,4]. The MPC approaches have been proposed and implemented for almost all power electronic applications [5]. Due to their distinctive advantages, such as fast dynamic response, the capability to incorporate multiple control objectives, straightforward implementation, and no need for modulator, MPC is much more powerful to tackle the challenge of the control of the cascaded H-bridge (CHB) static synchronous compensator (STATCOM) for distribution grids, compared with traditional linear hierarchical cascade control using phase-shifted carrier pulse-width modulation [6,7,8,9]. To ensure the proper functionality of a power converter, the MPC has to complete a control iteration in the order of tens to hundreds of microseconds. However, when employing MPC to CHB-STATCOMs, the modular multilevel structure brings about massive computational burden, and system modeling encounters great challenges when operating under unbalanced scenarios, which restricts the application of MPC.

To mitigate the computational burden of model predictive control (MPC) in multilevel converters, e.g., CHB-STATCOM, the existing literature has focused on four primary optimization dimensions. (1) First, from the perspective of hardware acceleration, field-programmable gate arrays (FPGAs) with parallel data processing capabilities have been utilized to accelerate the execution of optimization algorithms [10]. (2) Second, the optimal voltage level method [4,5], also referred to as optimal voltage level MPC (OVL-MPC) [5,11,12], represents the most widely adopted approach. It leverages redundant switching states corresponding to each output voltage level to balance capacitor voltages or suppress switching losses, notably reducing the number of iterations per cell in a CHB converter from $4^N$ to $2N+1$ (where N denotes the number of cascaded submodules) [5]. (3) Third, the nearest level selection (NLS) method for cascaded multilevel converters reduces the evaluated voltage levels by selecting two adjacent levels within consecutive sampling periods, which minimizes both the computational overhead and the output voltage change rate ($dv/dt$), making it suitable for applications with relaxed dynamic response requirements. As presented in [13], the optimal voltage level MPC proposed for the CHB converter can dramatically reduce the calculation burden from an exponential to a polynomial level. An adjacent voltage-level MPC is proposed in [14], which uses two adjacent voltage levels over two consecutive sampling cycles to further reduce the voltage level evaluations, but as mentioned in the article, its dynamic response is compromised while reducing the calculation burden, and is thus only suitable for the applications that do not require very fast dynamic response. (4) Fourth, simplified inverse MPC strategies have been proposed to streamline the optimization process [15]. This approach transforms the cost function into an equivalent optimization problem, whereby the equivalent output voltage references are inversely calculated within the system predictive model based on future current references, thereby drastically compressing the controller’s computational effort by requiring only a single evaluation per sampling period. Although this computational reduction is less pronounced in long-prediction-horizon scenarios [16,17]—rendering it primarily suitable for short-prediction-horizon MPC (SPH-MPC)—it has achieved significant efficiency enhancements in CHB converters [18].

In addition, submodule DC-side capacitor voltage sorting methods restrict the control set range by selecting appropriate switching states to selectively charge or discharge low- and high-voltage submodules, thus achieving simultaneous capacitor voltage balancing and current tracking with a drastically reduced computational load. As reported in [19], a group-sorting MPC method is proposed for MMCs, which classifies the half-bridge submodules into a variety of groups to restrict the finite control set scope. The evaluation is conducted within this restrained scope, and thus, the calculation burden is significantly reduced. In [20], a priority sorting MPC approach is presented for MMCs, which significantly improves the calculation efficiency.

In recent years, research on MPC strategies for multilevel converters has primarily centered on addressing steady-state tracking errors and processor computational overhead. However, beyond the aforementioned works, comprehensive research regarding MPC strategies specifically tailored for CHB-STATCOMs under unbalanced conditions can rarely be found in the published literature thus far. Some of the existing articles only focus on the computational efficiency improvement but without considering grid and/or load unbalances [21,22]. Therefore, an MPC strategy is proposed for the CHB-STATCOM with considerations of unbalanced conditions in [23]. This article proposes a computationally efficient model predictive control (EMPC), which presents more experimental results and further advances the idea proposed in [23] in detail. It develops a generic discrete-time model of the CHB-STATCOM for distribution grids by mathematically analyzing the power interaction of the system, which uses a proper calculated zero-sequence voltage to regulate the active power among the three phase legs of the CHB-STATCOM. Then, the bubble sorting algorithm is adopted to arrange the H-bridge submodules in low-to-high order based on their dc capacitor voltages, such that the optimal switching states that have the best current tracking performance can be chosen among the ones that charge the lower-voltage capacitors and discharge higher-voltage capacitors, and thus, the execution efficiency can be significantly enhanced. Finally, both simulation and hardware-in-the-loop (HIL) experimental studies are presented to validate the effectiveness of the proposed EMPC strategy.

2. Computationally Efficient Model Predictive Control

2.1. Generic Prediction Model

The first step of great significance is to develop a discrete-time prediction model for the CHB-STATCOM, which should be a valid model for both balanced and unbalanced scenarios. Figure 1 illustrates a typical architecture of a CHB-STATCOM with star-connection for distribution grids, where $i_{sj}$ are grid currents, $u_{sab}$, $u_{sbc}$, and $u_{sca}$ are line-to-line voltages, $i_{load\_j}$ are load currents, $i_{STAT\_j}$ are STATCOM output currents, C and L are dc capacitance and interfacing inductance, respectively, $u_{dc\_j\_n}$ are H-bridge dc capacitor voltages in three phase legs, and $u_j$ are converter ac terminal voltages, where $j\in \{a,b,c\}$ and $n\in \{1,2,\dots ,N\}$.

Since the balanced scenario can be considered as a specific case of the unbalanced scenario, a generic mathematical model can be developed by transforming the load- and grid-side as a lumped equivalent power source, as demonstrated in Figure 2. The line-to-line voltages can be expressed as

$$\left\{\begin{array}{c}{u}_{sab}=u_a-L{\displaystyle \frac{d{i}_{STAT\_a}}{dt}}-\left(u_b-L{\displaystyle \frac{d{i}_{STAT\_b}}{dt}}\right)\hfill \\ u_{sbc}=u_b-L{\displaystyle \frac{d{i}_{STAT\_b}}{dt}}-\left(u_c-L{\displaystyle \frac{d{i}_{STAT\_c}}{dt}}\right)\hfill \\ u_{sca}=u_c-L{\displaystyle \frac{d{i}_{STAT\_c}}{dt}}-\left(u_a-L{\displaystyle \frac{d{i}_{STAT\_a}}{dt}}\right)\hfill \end{array}.\right.$$

(1)

It should be noted that, in a real-world scenario, the resistance of the inductor should be included in the model. However, since the value of the resistance only constitutes a tiny portion of the interfacing impedance, its impact is very minor. Therefore, we neglected the resistance in the above model.

Due to the star-connection, the following relationship can be obtained,

$$u_0={\displaystyle \frac{1}{3}}\left(u_a+u_b+u_c\right),$$

(2)

$$i_{STAT\_a}+i_{STAT\_b}+i_{STAT\_c}=0,$$

(3)

where $u_0$ is the common-mode voltage, or namely, the zero-sequence voltage of the STATCOM. Combining (2) and (3) with (1) yields

$$\left\{\begin{array}{c}{\displaystyle \frac{1}{3}}\left(u_{sab}-u_{sca}\right)=u_a-u_0-L{\displaystyle \frac{d{i}_{STAT\_a}}{dt}}\hfill \\ {\displaystyle \frac{1}{3}}\left(u_{sab}-u_{sbc}\right)=u_b-u_0-L{\displaystyle \frac{d{i}_{STAT\_b}}{dt}}\hfill \\ {\displaystyle \frac{1}{3}}\left(u_{sbc}-u_{sca}\right)=u_c-u_0-L{\displaystyle \frac{d{i}_{STAT\_c}}{dt}}\hfill \end{array}.\right.$$

(4)

Define $u_{sj\_p}$, $u_{sj\_n}$, and $u_{s0}$ as the positive- negative-, and zero-sequence voltage of the equivalent power source; then,

$$\left\{\begin{array}{c}{\displaystyle \frac{1}{3}}\left(u_{sab}-u_{sca}\right)=u_{sa\_p}+u_{sa\_n}=u_{sa}-u_{s0}\hfill \\ {\displaystyle \frac{1}{3}}\left(u_{sab}-u_{sbc}\right)=u_{sb\_p}+u_{sb\_n}=u_{sb}-u_{s0}\hfill \\ {\displaystyle \frac{1}{3}}\left(u_{sbc}-u_{sca}\right)=u_{sc\_p}+u_{sc\_n}=u_{sc}-u_{s0}\hfill \end{array},\right.$$

(5)

where $u_{s0}=u_0$. Thus, by substituting (5) into (4), the system mathematical model can be given by

$$u_{sj}=u_j-L{\displaystyle \frac{d{i}_{STAT\_j}}{dt}},$$

(6)

where $u_{sj}=u_{sj\_p}+u_{sj\_n}+u_0$, and $j\in a,b,c$.

In this mathematical model, the three-phase system is independently decoupled, and the zero-sequence voltage serves as an extra degree of freedom to regulate internal active power among three phase legs, such that the dc capacitor voltages are balanced when negative current compensation is required. It is noteworthy that, if the negative current to be compensated is too large, the demanded zero-sequence voltage may exceed the maximum output voltage amplitude of the converter; the discussion of this limitation can be found in [24].

2.2. Zero-Sequence Voltage Derivation

According to the analysis in [23,24], the amount of power regulation for the three-phase STATCOM system can be obtained. Then, defining the zero-sequence voltage as $u_0=U_{0}sin(\omega t+{\varphi }_0)=Asin\left(\omega t\right)+Bcos\left(\omega t\right)$, where A and B can be given by

$$\left\{\begin{array}{c}A={\displaystyle \frac{\left[\begin{array}{c}2\Delta p_a-U_p{I}_{n}cos({\phi }_n-{\theta }_p)-U_n{I}_{p}cos({\phi }_p-{\theta }_n)-B(I_{p}sin{\phi }_p+I_{n}sin{\phi }_n)\hfill \end{array}\right]}{{\displaystyle I_{p}cos{\phi }_p+I_{n}cos{\phi }_n}}}\hfill \\ B={\displaystyle \frac{\left\{\begin{array}{c}2\Delta p_a\left[I_{p}cos({\phi }_p-\frac{2}{3}\pi )+I_{n}cos({\phi }_n+\frac{2}{3}\pi )\right]-2\Delta p_b(I_{p}cos{\phi }_p+I_{n}cos{\phi }_n)\hfill \\ +U_p{I}_n{I}_{p}sin\left(\frac{2}{3}\pi \right)sin({\phi }_n-{\phi }_p-{\theta }_p)+U_n{I}_n{I}_{p}sin\left(\frac{2}{3}\pi \right)sin({\phi }_n+{\phi }_p+{\theta }_n)\hfill \\ +U_p{I_n}^{2}sin\left(\frac{2}{3}\pi \right)sin(2{\phi }_n-{\theta }_p)-U_n{I_p}^{2}sin\left(\frac{2}{3}\pi \right)sin(2{\phi }_p-{\theta }_n)\hfill \end{array}\right\}}{{\displaystyle sin\left(\frac{2}{3}\pi \right)({I_p}^2-{I_n}^2)}}}\hfill \end{array},\right.$$

(7)

where $\Delta p_j$ is the interactive active power among three phase legs, $U_p$, $U_n$, ${\theta }_p$ and ${\theta }_n$ are positive- and negative-sequence voltage amplitude and initial phase, $U_0$ and ${\phi }_0$ are the zero-sequence component amplitude and phase of converter output voltage, and $I_p$, $I_n$, ${\phi }_p$, and ${\phi }_n$ are the positive- and negative-sequence current amplitude and initial phase of the converter output current, respectively. In this way, the sum of the three-phase active power remains the same. And consequently, the zero-sequence voltage for regulating the active power among phase legs can be obtained from the above equations.

Figure 3 illustrates the phasor diagram of the unbalanced CHB-STATCOM system. As can be seen, the phase leg current vector $i_{STAT\_j}$ of the STATCOM is perpendicular to the equivalent power source voltage $u_{sa}$, which is also equal to the converter voltage plus the inductor voltage: $j\omega L·i_{STAT\_j}$ that is in phase with the equivalent power source voltage usa, such that the active power that flows through the STATCOM equals to zero, and the dc capacitor voltage can be stabilized accordingly. In addition to the relationship between the converter current and the equivalent power source voltage, Figure 3 also shows that the equivalent power source voltage usa is the summation of the positive-, and negative- and zero-sequence voltage, i.e., $u_{sj\_p}$, $u_{sj\_n}$, and $u_0$. As can be seen, the original power source voltage ${u_{sj}}^{\ast }$ is converted to $u_{sj}$, while the neutral point has been shifted after the zero-sequence voltage $u_0$ is injected. However, the line-to-line voltages stay unchanged.

2.3. Implementation of the EMPC

Figure 4 illustrates the control diagram of the proposed EMPC, where flag is a two-dimension array, which represents the capacitor voltage sorting index, $u_{dc\_avg}$ is the average value of all the $3N$ dc voltages, $u_{dc\_ref}$ is the dc capacitor voltage reference, “$PLL$” block is the phase-lock-loop, which locks the positive-sequence phase of the equivalent power source, $u_{dc\_phase\_avg}$ is the average value of the dc voltages per phase, and $u_{dc\_a\_sum}$ and $u_{dc\_b\_sum}$ are the sum of the dc voltages in phase A and B, respectively. The amplitude and phase of the positive- and negative-sequence components of the equivalent power source voltage and STATCOM current are calculated by the method of symmetric components. The desired zero-sequence voltage can be obtained by (7). The reference calculation is aimed at obtaining the active power required for overall dc voltage regulation, fundamental reactive current, and negative current from the load.

As depicted in Figure 4, the dc capacitor voltage balancing is achieved by three layers of control: firstly, the total active power of three-phase system is regulated by the reference current calculation; secondly, the total active power in each phase leg is regulated by inserting a control objective in the cost function and the interactive active power among each phase leg is regulated by zero-sequence voltage; thirdly, the dc capacitor voltage balancing within each phase leg is guaranteed by the sorting process. The implementation process of the EMPC is elaborated in the following paragraphs.

Basically, there are two essential control objectives for a CHB STATCOM, i.e., the dc capacitor voltage regulation and reference current tracking, that need to be considered regarding the optimality. Assuming that the dc capacitors voltages are well-regulated all the time, the current tracking is only determined by the output voltage vector, i.e., the output voltage level, of the CHB converter, which produces a particular current slope that has a certain impact on the current tracking [25]. The current control objective of the MPC is to find the optimal voltage vector that has optimal impact on the current tracking. However, each output voltage level can be contributed to by numerous redundant switching states, especially when a large number of the H-bridges are cascaded together in one phase leg.

The concept of the EMPC strategy can dramatically reduce the number of the switching states that should be evaluated within each sampling period by only considering the ones that can balance the dc capacitor voltages of the H-bridges, i.e., the switching functions that allow charging of the higher-voltage dc capacitors or discharging of the lower-voltage dc capacitors. The selection of the available switching states should be deliberately arranged so that the range of choice is not too small to track current reference and not too large to reduce the evaluation burden either.

The limitation of the proposed EMPC only works as a refinement process to select the optimal switching state, i.e., the one that is able to balance the dc capacitor voltages, among all the redundant switching states that belong to the optimal voltage vector. Therefore, the optimality of reference current tracking can always be safeguarded while the dc voltage balancing can also be guaranteed.

Figure 5a demonstrates the switching states selection process of the proposed EMPC strategy, i.e., the dual symmetric distribution method. Firstly, the H-bridge submodules are sorted according to their dc capacitor voltages in ascending order. Defining the switching function of the nth H-bridge in phase j as $S_{j\_n}$ ($S_{j\_n}\in \{-1,0,1\}$), the switching states to be evaluated can be described as follows: (1) when $i_{STAT\_j}<0$, $flag=[p,q]$ is used to represent the switching state flag, where p is the index of the H-bridges from the lower- to higher-voltage direction that are switched to charge the dc capacitors, $S_{j\_n}=1$, and while q is the index of the H-bridges form the higher- to lower-voltage direction that are switched to discharge the dc capacitors, $S_{j\_n}=-1$; (2) when $i_{STAT\_j}>0$, $flag=[p,q]$ represents the switching state flag, where p is the index of the H-bridges from the lower- to higher-voltage direction that are switched to charge the dc capacitors, $S_{j\_n}=-1$, and while q is the index of the H-bridges from the higher- to lower-voltage direction that are switched to discharge the dc capacitors, $S_{j\_n}=1$. Figure 5b shows all the possible flag combinations. In this way, the possible switching state to be evaluated in one phase per sampling cycle can be reduced from $4N$ to ${\displaystyle \frac{(N+2)(N+1)}{2}}$. Figure 6 exhibits the switching state comparison between the proposed EMPC and conventional MPC (CMPC), which reveals that the switching state evaluation quantity of the CMPC is tremendously larger than that of the proposed EMPC and is therefore too hard to implement.

The next step is the calculation of the cost function, which can be classified into two categories:

(1) when $i_{STAT\_j}<0$, the switching function of submodules in phase j can be given by

$$S_{j\_n^{\ast }}=\left\{\begin{array}{c}1,p\ne 0\&n^{\ast }=1,\cdots ,p\hfill \\ 0,p+q\ne N\&n^{\ast }=p+1,\cdots ,N-q\hfill \\ -1,q\ne 0\&n^{\ast }=N-q+1,\cdots ,N\hfill \end{array},\right.$$

(8)

where ${S_{j\_n}}^{\ast }$ and $n^{\ast }$ stand for the switching function of phase j and the submodule index after ascendingly sorted. Then the ac terminal voltage of the STATCOM can be given by

$$u_j\left(k\right)={\displaystyle \sum _{n^{\ast }=1}^N}{S}_{j\_n^{\ast }}{u}_{dc\_j\_n^{\ast }}\left(k\right).$$

(9)

The predicted H-bridge capacitor voltage can be given by

$${u_{dc\_j\_n^{\ast }}}^p(k+1)=u_{dc\_j\_n^{\ast }}\left(k\right)-S_{j\_n^{\ast }}{\displaystyle \frac{i_{STAT\_j}\left(k\right)}{C}}{T}_s.$$

(10)

By applying the forward Euler method to the mathematical model in (6), the discrete-time model can be given by

$$L{\displaystyle \frac{i_{STAT\_j}(k+1)-i_{STAT\_j}\left(k\right)}{T_s}}=u_j\left(k\right)-u_{sj}\left(k\right),$$

(11)

where $T_s$ is the sampling period; then the predicted output current of the STATCOM can be given by

$${i_{STAT\_j}}^p(k+1)={\displaystyle \frac{T_s}{L}}\left[u_j\left(k\right)-u_{sj}\left(k\right)\right]+i_{STAT\_j}\left(k\right).$$

(12)

The predicted total dc-side energy can be given by

$${w_j}^p(k+1)={\displaystyle \sum _{n^{\ast }=1}^N}{\displaystyle \frac{1}{2}}C{\left[{u_{dc\_j\_n^{\ast }}}^p(k+1)\right]}^2.$$

(13)

(2) When $i_{STAT\_j}>0$, the switching function of submodules in phase j can be given by

$$S_{j\_n^{\ast }}=\left\{\begin{array}{c}-1,p\ne 0\&n^{\ast }=1,\cdots ,p\hfill \\ 0,p+q\ne N\&n^{\ast }=p+1,\cdots ,N-q\hfill \\ 1,q\ne 0\&n^{\ast }=N-q+1,\cdots ,N\hfill \end{array}.\right.$$

(14)

The derivation of the other variables is the same as the condition when current is negative.

Consequently, the cost function using the $l_2$ norm [26] can be given by

$$J=\lambda {\displaystyle \sum _{n^{\ast }=1}^N}{∥{u_{dc\_j\_n^{\ast }}}^p-u_{dc\_ref}∥}_2^2+{∥{i_{STAT\_j}}^p(k+1)-i_{ref\_j}(k+1)∥}_2^2,$$

(15)

where $\lambda$ is the weighting factor of the cost function, the design guidance of which can be found in [3], and $u_{dc\_ref}$ is the dc capacitor voltage reference. Figure 7 demonstrates the flow chart of the proposed EMPC strategy, where $J_{min}$ represents the minimum cost function. At the beginning of each sampling period, the minimum cost function value is initialized, and the sorted dc-link capacitor voltages of the N CHB cells, the measured STATCOM current, the equivalent grid voltage, and the reference current are loaded. Subsequently, two nested loops are executed to traverse all feasible voltage-level candidates represented by the variables p and q. Depending on the direction of the STATCOM current, the corresponding H-bridge switching functions are determined according to (16) and (22). Based on the obtained switching states, the predicted STATCOM output current and dc-side energy are calculated using (20) and (21), respectively. The cost function defined in (23) is then evaluated for each candidate. If the calculated cost is smaller than the current minimum value, the minimum cost and the associated switching-state flag are updated. After all combinations of p and q have been examined, the switching-state flag corresponding to the minimum cost function value is selected and output as the optimal module state for the next control interval.

3. Simulation Studies

To verify the proposed EMPC strategy, a 10 kV, 6 MVA star-connected CHB-STATCOM is developed in MATLAB (R2021b) Simulink, the connection of which is the same as that in Figure 1; the key system parameters are listed in

Table 1. System parameters.

Description	Variable	Simulation	Experiment
Interfacing inductance	L	6 mH	6 mH
DC capacitance	C	9000 µF	3000 µF
DC voltage reference	$u_{dc\_ref}$	1000 V	300 V
Cascade number	N	12	2
Grid voltage	–	10 kV	380 V
Active power capacity	–	6 MW	30 kW
Reactive power capacity	–	6 MVAR	30 kVAR
Sampling frequency	$f_s$	10 kHz	10 kHz
Dead time	$T_d$	–	1 µs
Fundamental frequency	f	50 Hz	50 Hz

, and the rated capacities of the reactive and active power of the load are set to 6 MVAR and 6 MW, respectively.

In Figure 8a, load and grid unbalance appear at 0.3 s and 0.4 s, respectively. Note that the unbalance in the simulation is achieved only through the voltage and current amplitude deviation. As can be seen, the dc capacitor voltages are well-regulated during the unbalance scenario, but with a slightly larger fluctuation. The grid-side current is in phase with the equivalent power source voltage, and is also balanced, which indicates that the reactive and negative-sequence currents have been completely compensated by the STATCOM, the zero-sequence voltage emerges when the current unbalance occurs and the amplitude of which becomes larger when grid unbalance occurs. As can be seen, the STATCOM output currents are also unbalanced, which is in accordance with the aforementioned analysis.

In Figure 8b, the reactive current drops to half at 0.4 s and restores at 0.44 s. As can be seen, the dc capacitor voltages are also well-regulated to their reference when reactive power drops suddenly and the fast-dynamic response of the MPC is still kept active, that the regulation time is as short as approximately 350 µs.

It should be noted that the harmonic performance of MPC follows the patterns demonstrated in [3], which does not reveal a fixed switching frequency pattern. However, by applying an extra degree of control over the switching frequency with another weighting factor, MPC can also have a fixed switching frequency [3].

4. Experimental Studies

To experimentally validate the proposed EMPC strategy, an HIL experimental test rig is established (see Figure 9), which consists of a Typhoon HIL 602+ (Manufactured by Typhoon HIL, Waltham, MA, USA) and a dSapce MicroLabBox (Manufactured by dSPACE GmbH, Paderborn, Germany). Since the adopted simulator can only synchronously simulate maximum 6 H-bridges in real-time, i.e., 24 power switches in total, a downscaled 380 V–30 kVA star-connected CHB-STATCOM model is developed in the Typhoon HIL 602+; the key system parameters are also listed in Table 1. The objective of the HIL experiments is to validate the correctness and real-time feasibility of the proposed control algorithm. The proposed MPC strategy is formulated in a modular manner and operates based on the same prediction and optimization principles regardless of the number of cascaded cells. Increasing the number of cells mainly affects the dimensionality of the optimization problem and the associated computational burden, rather than altering the control mechanism itself. Therefore, a two-cell HIL setup is sufficient to experimentally verify the implementation, execution sequence, and dynamic behavior of the proposed control strategy. HIL platforms for high-voltage/high-cell-count CHB systems are often constrained by available real-time simulator resources and I/O channels; due to the resource limitations of our lab, the simulator is only able to operate a two-cell three-phase CHB system, but it is indeed enough to verify the control mechanism.

In the experiment, the amplitudes of the load current and grid voltage of phase A are set to 80% of the rated value to emulate the unbalances. Figure 10 demonstrates the steady-state waveforms of the proposed EMPC and the CMPC. As can be seen, the dc capacitor voltages are all well-regulated to their reference, with a slight voltage fluctuation caused by reactive power. The dc voltage fluctuation of the CMPC is slightly larger than that of the proposed EMPC. In addition, the output currents under both control approaches are almost the same, which indicates that, although the proposed EMPC strategy has a restriction on the selection of switching states, the performance is not significantly affected.

The transient-state performances of the EMPC strategy and the CMPC are exhibited in Figure 11, where the load reactive current drops to half for 60 ms. As shown, the dc capacitor voltages can still be stabilized during the transients under both control methods; the output current tracks the reference current very closely with a regulation time of only 260 µs for the proposed EMPC and 280 µs for the CMPC. It can be therefore be concluded that the dynamic performance of the proposed EMPC is still comparable to the CMPC.

Figure 12 shows the impact of the weighting factor when using the EMPC. The weighting factor $\lambda$ is initially set to 0.1, then changed to 0.01 for 200 ms and changed to 2 for 100 ms, and then restored to 0.1 again. As can be seen, when $\lambda =0.1$, the dc voltage balancing experiences the best performance. When $\lambda =0.01$, the dc voltages begin to drift away from their reference. When $\lambda =2$, the dc voltages are well-balanced and the dc voltage fluctuation is smaller compared to the situation when $\lambda =0.1$. However, it can be observed that the converter terminal voltage reveals significant distortion when $\lambda =2$.

Figure 13 exhibits the impact of the interfacing inductance mismatch when using the EMPC. The inductance is firstly set to its accurate value of 6 mH; then it changes to 4 mH (−33% mismatch), 9 mH (50% mismatch), and 18 mH (200% mismatch) in turn with each of the value lasting for 100 ms. As can be seen, when −33% of mismatch occurs, the dc voltages become unstable. When 50% and 200% of mismatch occur, the system can still be stable, but the current ripple of the 200% scenario is slightly larger. Therefore, it can be concluded that the EMPC is not very sensitive to parameter mismatch, and it is more sensitive to inductance decrease than to inductance increase. According to the phasor diagram in Figure 3, a smaller inductance means that the voltage amplitude across the inductor is smaller, and therefore, the ac terminal voltage across the CHB-STATCOM becomes larger, which makes the modulation index of the CHB converter larger, and thus in turn, makes the dc capacitor voltage balancing more difficult. On the other hand, when the inductance is larger, the ac terminal voltage across the CHB-STATCOM becomes smaller, and the dc capacitor voltage balancing becomes easier.

Figure 14 demonstrates the dc voltage balancing effect of the zero-sequence voltage injection. As can be seen, during the time period when the zero-sequence voltage is set to 0 for 500 ms, the dc voltages start to drift away, while, as soon as the zero-sequence voltage is restored, the dc voltages begin to converge together. This clearly shows the effectiveness of the generic prediction model for dc voltage balancing. Figure 15 depicts the turnaround time comparison between the proposed EMPC and the CMPC, which is measured in the dSpace real-time mode. As can be seen, the turnaround times of the proposed EMPC and the CMPC applied to the 380 V–30 kVA-2 module CHB STATCOM are 26 µs and 31 µs, respectively, while for the 10 kV–12 MVA-12 module CHB STATCOM, they are 52 µs and 5,033,164 µs, respectively. Thus, the proposed EMPC strategy for 12-module CHB STATCOM can be completely executed within a 100 µs time-frame, i.e., a 10 kHz sampling frequency, which enables approximately 90 k times execution time reduction compared with the CMPC. It should be noted that the sorting process is considered in the turnaround time.

5. Conclusions

In this article, an EMPC strategy for CHB-STATCOM with star-connection is presented, which significantly reduces the computational burden and simultaneously achieves dc capacitor voltage balancing under an unbalanced scenario. A generic discrete-time prediction model of an equivalent power source model is developed, which incorporates the zero-sequence voltage by mathematically analyzing the power interaction of the system. In addition, the bubble sorting algorithm is employed to arrange the H-bridge submodules in low to high order based on their dc capacitor voltages to restrict the scope of the candidate switching states, such that the execution efficiency is significantly improved. Finally, both simulation and experimental studies are presented to validate the feasibility and effectiveness of the proposed EMPC strategy for CHB-STATCOM with star-connection.