Coordinated AC Fault Ride-Through Strategy for Wind Farms Integration via MMC-HVDC Using DC-Side Energy Storage

Abstract

In the context of the new power system, modular multilevel converter high-voltage direct current (MMC-HVDC) has become a key technical solution for the large-scale grid integration of wind power. However, when a fault occurs in the AC grid at the system receiving end, the high-voltage direct current (HVDC) system faces challenges such as wind power redundancy, DC overvoltage, and equipment overcurrent. To address this, this paper proposes an energy storage-coordinated fault ride-through (FRT) control strategy suitable for different fault scenarios. The strategy optimizes the allocation of energy storage capacity according to the state of charge (SOC) of the energy storage units (ESUs), preventing individual ESUs from prematurely shutting down and reducing energy dissipation. Finally, a comparison with a conventional DC dissipation resistor scheme on the PSCAD/EMTDC platform demonstrates that the proposed strategy provides smoother power regulation characteristics and smaller DC voltage fluctuations, thereby enhancing the economic efficiency and reliability of system operation.

1. Introduction

Driven by the global energy transition and carbon neutrality goals, the development and transformation of the six key elements in the new power system—power generation, grids, loads, energy storage, carbon emissions, and meteorological conditions—are facing unprecedented challenges and opportunities [1]. AC fault ride-through (AC-FRT) in wind power grid-connected systems has become a current research hotspot. When a fault occurs in the AC grid on the load side, the active power output from the grid-side modular multilevel converter (GSMMC) rapidly decreases, obstructing the wind power transmission path. This causes a large amount of power to accumulate on the DC side, leading to a rise in voltage and threatening system safety. Therefore, eliminating redundant power on the DC side is key to achieving fault ride-through (FRT). Existing methods can be broadly categorized into two types:

(1)

Using additional energy-dissipating resistors. This method directly converts excess power into heat by installing energy-dissipating devices on the DC or AC side. Specific approaches include centralized [2], distributed [3], and hybrid [4,5,6] configurations. Among these, the distributed approach places resistors within submodules and regulates power through switching control, but faces challenges related to heat dissipation. For onshore systems, thyristor-controlled AC dissipation resistors can also be installed at the point of common coupling (PCC) to limit the impact of faults [7,8]. However, this method inherently involves energy loss and can result in significant energy waste, particularly during severe grid voltage sags.

(2)

Wind farm (WF) load shedding. This method reduces the output of wind turbines (WTs) at the source to eliminate excess power. There are three primary methods for transmitting load shedding signals: communication-based, voltage-reduction, and frequency-increase methods [9]. While the frequency-increase method overcomes the reliability issues caused by communication delays, it suffers from some dynamic response lag [10]; therefore, there is a greater body of literature on the voltage-reduction method. For example, by analytically deriving the output power during under-voltage control, rapid matching control between the voltage reduction of the WF-side modular multilevel converter (WFMMC) and the load shedding of WTs can be achieved [11]; alternatively, a linear relationship between the DC voltage and the PCC voltage can be established, and instability caused by deep voltage reduction can be avoided through adaptive voltage adjustment [12,13,14]. However, excessively low-voltage strategies may cause motor overcurrent, which could compromise control performance or even lead to secondary issues.

In addition to the methods described above, some studies have utilized an energy storage system (ESS) to absorb excess power during faults, thereby preventing DC overvoltage. Specific approaches include: first, using passive components inherent to the system, such as capacitors and inductors, for short-term energy storage and release [15,16,17,18]; and second, installing dedicated energy storage devices within WTs or on the DC side [19,20,21]. The former approach typically requires integration with energy-dissipating devices or modifications to control strategies, resulting in a limited capacity to handle high-power surges or in complex engineering implementation; the latter has not fully leveraged the flexibility of wind-storage coordination in existing research. Current studies on FRT assisted by energy storage primarily focus on connecting energy storage as an independent unit to the DC bus of the converter station [22,23,24]. While such direct-connection schemes offer straightforward control, they fail to fully exploit the coordination potential between energy storage and WTs. Although coordinated MMC-wind farm power reduction without energy buffering has been investigated to mitigate DC overvoltage [25], few studies address distributed energy storage unit (ESU) participation with state of charge (SOC)-aware power allocation under AC faults at the receiving end, which is the focus of this paper. By distributing ESUs on the DC side of each WT, this paper proposes a coordinated control strategy that leverages these advantages: first, it enables deep coordinated control with the WT converter; second, it facilitates optimized power allocation and health management based on the SOC; and third, the distributed architecture enhances system reliability. Therefore, the proposed wind-storage hybrid system demonstrates significant potential for enhancing FRT performance.

Therefore, the main research question addressed in this paper is how to coordinate distributed ESUs and WT converters on the DC side to manage DC overvoltage during receiving-end AC faults without dissipative resistors. To answer this, the key contributions and novelty of this work lie in three aspects. First, regarding the distributed ESU architecture, unlike centralized ESS at the converter station, ESUs are distributed on the DC side of each WT, enabling deep coordination with local converters and enhancing system redundancy. Second, a coordinated control strategy is proposed that dynamically adjusts power absorption based on real-time voltage deviations, ensuring continuous operation without switching to dissipative devices. Third, for SOC-aware power allocation, an explicit SOC-based allocation logic is introduced to balance energy among distributed ESUs, preventing over-charge of high-SOC units and fully utilizing low-SOC units.

2. Materials and Methods

2.1. Topology of Wind Power Grid-Connection Systems via MMC-HVDC

Figure 1 shows the system architecture of a wind power grid-connection system based on modular multilevel converter high-voltage direct current (MMC-HVDC) technology. The high-voltage direct current (HVDC) section of this system employs a symmetrical bipolar connection, and its converter consists of half-bridge submodules.

At the control level, the GSMMC implements constant DC voltage and constant reactive power control, while the WFMMC employs a constant AC voltage and constant frequency control mode, designed to provide WTs with a grid-connected environment featuring stable voltage and frequency. The WF consists of multiple sets of permanent magnet synchronous generators (PMSG), which are stepped up and fed into the WFMMC. ESUs are integrated in parallel at the DC bus of each WT via bidirectional DC/DC converters. Additionally, overhead lines, which offer superior economic efficiency, are selected for the transmission lines connecting the two converter stations. Direct current circuit breakers (DCCB) and current-limiting reactors (L_dc) are connected in series at both ends of the overhead lines.

The digital control system operates with a sampling frequency of 10 kHz and a control period of 100 μs. All PI controllers employ output saturation limits and anti-windup mechanisms based on back-calculation to prevent integrator windup during fault transients. During Low Voltage Ride-Through (LVRT), the current reference is limited to 1.1 p.u. to protect the power devices. Synchronization is achieved using a Decoupled Double Synchronous Reference Frame PLL (DDSRF-PLL) to ensure accurate phase locking under asymmetric AC faults [26]. Low-pass filters (LPF) with a cutoff frequency of 50 Hz are used in the voltage and power control loops to suppress switching harmonics.

The ESS is modeled as a lithium-ion battery pack using a first-order resistor–capacitor (RC) equivalent circuit. The SOC is updated via Coulomb counting [27]. The SOC operational limits are set to 0.2–0.9 to ensure battery safety. The ESU is interfaced to the WT’s DC bus via a bidirectional buck-boost DC/DC converter. The converter control adopts a double-loop structure, consisting of an outer voltage loop and an inner current loop. For the purpose of system-level coordination analysis, the converter is assumed to operate with a constant efficiency of 95%, and detailed loss modeling is not explicitly included. The initial SOC values for the simulation cases are set to 0.60 and 0.40 for WG1 and WG2, respectively.

2.2. AC Fault Ride-Through Control Strategy Considering Energy Storage

The minimum capacity requirement of each ESU is determined according to the worst-case fault duration of 625 ms, in compliance with grid code requirements for WF’s FRT [19]. Since the fault duration is relatively short, thermal accumulation within the ESU is considered negligible, and no additional thermal sizing constraints are imposed for the FRT operation analyzed in this study.

When an AC fault occurs in the equivalent system at the receiving end, as shown in Figure 1, the active power delivered by the GSMMC to the receiving-end grid gradually decreases as the AC voltage drops. Due to the AC-DC isolation characteristics of the HVDC system, the WF is unable to detect the AC fault at the receiving end and will continue to supply power to the WFMMC as it did before the fault. The resulting excess power is primarily absorbed by the capacitors of the system submodules, causing the DC voltage to rise continuously. If the excess power persists, the DC voltage will exceed the normal operating threshold, leading to DC overvoltage in the system and threatening its safe and stable operation.

The coordination between WTs and ESUs is centrally managed by the WFMMC, which monitors the DC voltage and PCC voltage to generate global power references. These references are assumed to be ideally available to each ESU for the purpose of system-level coordination analysis. Detailed modeling of the communication network, including latency and failure modes, is beyond the scope of this study.

2.2.1. Analysis of Power-Dissipating Resistor Strategies

To limit overvoltage on the DC side, current engineering practices often involve connecting energy-dissipating resistors in parallel on the DC side of a GSMMC. The principle behind this approach is to dissipate excess power during a fault by switching the resistors on and off. While existing literature predominantly focuses on centralized structures, the energy-dissipating resistor devices currently in engineering applications are mostly distributed structures, consisting of a series of submodules connected in series [28].

Due to its unified switching control and single power path, the centralized structure provides a standard reference model free of internal coordination discrepancies. This facilitates a clearer attribution of system performance differences to the characteristics of the proposed control strategy itself when analyzing simulation results. To facilitate comparative analysis, this simulation study adopts a centralized energy-dissipating resistor as the baseline reference scheme. Figure 2 illustrates its installation location, basic structure, and control principle.

The resistance value of a dissipation resistor is typically configured based on the rated capacity of the converter station, and the calculation formula is as follows:

$$R_{\mathrm{ch}}={\displaystyle \frac{U_{\mathrm{dc}}^2}{S_{\mathrm{N}}}}$$

(1)

In the equation, R_ch is the resistance of the dissipation resistor; U_dc is the unipolar DC voltage of the HVDC system; S_N is the rated capacity of the converter station.

The energy absorbed by the dissipation resistor during the fault is:

$$E_{\mathrm{R}}={\displaystyle {\int }_{t_0}^t\frac{U_{\mathrm{dc}}^2}{R_{\mathrm{ch}}}}\mathrm{d}t$$

(2)

In the equation, E_R represents the energy dissipated by the energy-dissipating resistor during the fault.

The power-dissipating resistor employs a switching control strategy based on a DC voltage hysteresis comparator. When the DC voltage exceeds 1.05 p.u., the hysteresis comparator outputs a high level, driving the switching transistor to turn on and engage the resistor to dissipate excess power; when the voltage falls below 0.95 p.u., it outputs a low level, turning off the switching transistor to disconnect the resistor. Through this switching action, the DC voltage is limited to the range of 0.95–1.05 p.u., thereby eliminating the threat of DC overvoltage to system stability and ensuring the system successfully completes the AC-FRT.

To ensure clarity, the power sign convention defines charging (power flowing into the ESU) as positive (p > 0) and discharging (power flowing out) as negative (p < 0). During fault conditions, the operational mode maintains the ESUs in charging mode to absorb redundant power, thereby stabilizing the DC voltage.

Since the energy storage is integrated into the WT’s DC bus, the WT and energy storage are closely coupled. The WT’s grid-side voltage source converter (GSVSC), the wind-turbine voltage source converter (WTVSC), and the energy storage DC/DC converter can operate in coordination. Specifically, the system operates in a mode where the WT’s GSVSC controls the DC voltage and the energy storage operates at constant power. Based on this, this section proposes the corresponding energy storage constant-power control strategy.

2.2.2. Coordinated Control Strategy Based on Wind-Storage DC-Side Coordination

Figure 3 shows the overall control architecture of control strategy based on wind-storage DC-side coordination, the constant-power control strategy.

The specific implementation of the buck control and the voltage-active power control (u_w-P control) at the PCC in Control Strategy 1 is shown in Figure 4.

Assume that a fault occurs in the AC system at time t₀, causing the DC voltage to begin rising. During the time interval t₀–t₁, while the DC voltage has not yet exceeded the threshold U_dc,th, the d-axis voltage reference of the WFMMC remains set to u_wd,ref = 1, as in normal operation.

When the DC voltage rises to the threshold U_dc,th at time t₁, the WFMMC initiates the buck control strategy, and its voltage reference value u_wd,ref is calculated according to the following equation:

$$u_{\mathrm{wd},\mathrm{ref}}=u_{\mathrm{wd},\mathrm{nom}}-K_{\mathrm{v}}(U_{\mathrm{dc}}-U_{\mathrm{dc},\mathrm{th}})$$

(3)

In the equation, u_wd,nom is the d-axis component of the rated voltage on the WT side; U_dc,th is the DC voltage threshold; K_v is the step-down ratio coefficient.

In particular, the formula for calculating the voltage reduction ratio is:

$$K_v={\displaystyle \frac{u_{\mathrm{wd},\mathrm{nom}}-u_{\mathrm{wd},\min }}{U_{\mathrm{dc},\max }-U_{\mathrm{dc},\mathrm{th}}}}$$

(4)

In the equation, u_wd,min is the minimum voltage on the d-axis of the wind field; U_dc,max is the maximum DC voltage.

At time t₁, the voltage u_w at the WF’s PCC begins to drop due to the initiation of voltage-reduction control. During the time interval t₁–t₂, while the voltage at the PCC has not yet fallen below the threshold u_w,th, the ESU power reference value remains at P_ESU,ref = 0; When the voltage at the PCC falls below the threshold u_w,th at time t₂, the ESU begins to absorb power, and the total power reference value that the ESS should absorb is calculated according to Equation (5):

$$P_{\mathrm{ESS},\mathrm{ref}}=n\left[K_{\mathrm{P}}(u_{\mathrm{w},\mathrm{th}}-u_{\mathrm{w}})\right]$$

(5)

In the equation, P_ESS,ref is the reference value for the total power that the ESS should absorb; u_w is the voltage at the PCC; u_w,th is the voltage threshold at the PCC; K_P is the energy storage power ratio coefficient; n is the number of WTs, i.e., the number of ESUs.

In particular, the formula for calculating the energy storage power ratio coefficient K_P is:

$$K_{\mathrm{P}}={\displaystyle \frac{P_{\mathrm{ESU},\mathrm{nom}}}{u_{\mathrm{w},\mathrm{th}}-u_{\mathrm{w},\min }}}$$

(6)

In the equation, u_w,min is the minimum voltage limit at the PCC.

Considering the differences in SOC among the ESUs within each WT, simply distributing the redundant power equally may result in ESUs with higher SOC reaching their capacity limits quickly, while ESUs with lower SOC still have significant unused storage capacity. Therefore, a scheme is proposed to allocate the total power absorbed by the ESS according to the SOC of each ESU. First, the initial power reference value allocated to each ESU is calculated using the following equation:

$${P^{\prime }}_{\mathrm{ESU},\mathrm{ref}i}={\displaystyle \frac{\frac{1}{S_{\mathrm{SOC},i}}}{{\displaystyle \sum _{i=1}^n\frac{1}{S_{\mathrm{SOC},i}}}}}{P}_{\mathrm{ESS},\mathrm{ref}}$$

(7)

In the equation, ${P^{\prime }}_{\mathrm{ESU},\mathrm{ref}i}$ is the initial power reference value for the i-th ESU; S_SOC,i denotes the real-time SOC of the i-th ESU.

To prevent overcharging and fully utilize the capacity of all ESUs, the total absorption power is allocated inversely proportional to the SOC of each unit. As defined in Equation (7), the weighting factor for each ESU is ${\displaystyle \frac{1}{S_{\mathrm{SOC},i}}}$, which inherently assigns a larger power share to low-SOC ESUs (with more available headroom) and a smaller share to high-SOC ESUs (with less headroom). This inverse-SOC allocation strategy maximizes total energy absorption while minimizing the risk of any individual ESU prematurely hitting the upper SOC limit and shutting down.

To further ensure physical feasibility, the allocated power is subject to a hard ceiling that limits the absorbed energy to the remaining SOC headroom within the 625 ms fault duration.

If the initial allocated power of the i-th ESU exceeds its rated power, its power reference value is set equal to its rated power, P_ESU,nom, and the power reference values for all other ESUs (excluding the i-th ESU) are adjusted as follows:

Define the set of non-saturated ESUs as:

$${\Omega }_{\mathrm{ns}}=\left\{i|P_{\mathrm{ESS},\mathrm{refi}}\le P_{\mathrm{ESU},\mathrm{nom}}\right\}$$

(8)

Then, the corrected power reference is:

$$P_{\mathrm{ESU},\mathrm{ref}i}^{\mathrm{new}}=\left\{\begin{array}{l}{P}_{\mathrm{ESU},\mathrm{nom}}, i\in {\Omega }_{\mathrm{sat}}\\ {\displaystyle \frac{\frac{1}{S_{\mathrm{SOC},i}}}{{\displaystyle \sum _{k\in {\Omega }_{\mathrm{ns}}}\frac{1}{S_{\mathrm{SOC},k}}}}}\left(P_{\mathrm{ESS},\mathrm{ref}}-{\displaystyle \sum _{l\in {\Omega }_{\mathrm{sat}}}{P}_{\mathrm{ESU},\mathrm{nom}}}\right), i\in {\Omega }_{\mathrm{ns}}\end{array}\right.$$

(9)

In the equation, $P_{\mathrm{ESU},\mathrm{ref}i}^{\mathrm{new}}$ is the corrected energy storage power reference value; ${\Omega }_{\mathrm{ns}}$ is the set of ESUs whose initial power reference does not exceed the rated power, and ${\Omega }_{\mathrm{sat}}$ is the saturated ESUs; The index k iterates over all non-saturated ESUs to compute the normalization factor for power allocation and the index l iterates over all saturated ESUs to calculate the total power already allocated at their rated capacity.

In the equation, $P_{\mathrm{ESU},\mathrm{ref}i}^{\mathrm{new}}$ is the corrected energy storage power reference value; m is the number of ESUs whose initial power reference values exceed the rated power.

After each ESU absorbs power according to Equation (9), the DC voltage stops rising and stabilizes within the limit U_dc,max. When the fault ends at time t₃, the input power to the GSMMC increases; as the DC voltage decreases, the PCC voltage recovers, and the energy storage absorption power decreases accordingly. When the PCC voltage rises to the threshold, the energy storage power reference value drops to zero, once the DC voltage falls to the threshold, the voltage-reduction control is deactivated, the PCC voltage returns to the rated value, and the system reverts to its pre-fault steady-state, thereby completing FRT.

The parameter values for the proposed coordinated control strategy are shown in

Table 1. Parameter values in the control strategy.

Parameters	Udc,nom	Udc,th	Udc,max	uw,nom	uw,th	uw,min	PESU,nom
Values/p.u.	1.0	1.05	1.1	1.0	0.95	0.5	1.0

. Throughout the control process, u_wq,ref is set to 0; therefore, it can be assumed that the values of u_w and u_wd are identical.

The DC voltage threshold U_dc,th = 1.05 is selected in accordance with GB/T 19963.2-2024 [29] and is consistent with international grid-code requirements (e.g., E.ON Netz Grid Code and IEC 61400-related provisions), which mandate corrective action when the DC voltage exceeds 105% of the nominal value. The PCC voltage threshold u_w,th = 0.95 is aligned with standard LVRT requirements for Type-IV wind turbines to ensure coordination with grid support functions. The control logic is designed to be robust against minor threshold deviations. Since the voltage reduction and energy storage activation are governed by proportional relationships rather than rigid setpoints [25], reasonable variations in the thresholds are expected to have a limited impact on the peak DC voltage and the overall ride-through performance.

To ensure stable mode switching between Strategy 1 and Strategy 2, a bumpless transfer mechanism is implemented. A voltage hysteresis deadband of ±0.05 p.u. is applied to the PCC voltage to avoid chattering during threshold crossing. During switching, reference ramping is enforced on the active power command and DC voltage reference, with a maximum ramp rate of 0.1 p.u./ms to prevent current overshoot. Additionally, as shown in Figure 3 and Figure 5, a first-order LPF with a cutoff frequency of 50 Hz is applied to the PCC voltage measurement to suppress high-frequency noise and ensure reliable mode detection. This filter is critical for accurate voltage-sag detection and prevents false triggering of mode switches during transient disturbances.

2.2.3. Overall Control Logic and Energy Storage Parameter Design

The specific control sequence and logic for the proposed coordinated control strategy are shown in Figure 5a,b.

As can be seen from the above control strategy, the excess power during a fault is primarily absorbed by the ESS, with only a small portion stored by the capacitors in the DC system submodules. It is evident that the ESS’s ability to absorb excess power directly affects the effectiveness of AC-FRT; therefore, it is necessary to clarify the rated power and rated capacity of the ESU. Considering the most severe fault scenario where the WF is operating at full capacity, the WFMMC transmits virtually no active power to the AC system. In this case, if the energy storage capacity of the submodule capacitors is disregarded, all system excess power is absorbed by the ESU; therefore, the ESU’s rated power, P_ESU,nom, should equal the WT’s rated power, P_WT,nom.

According to the grid connection guidelines for WFs: when the voltage at the WF’s PCC drops to 20% of the nominal voltage, the WTs within the WF must ensure continuous operation without disconnection. From this, the required FRT duration T_FRT is specified as 625 ms in this study.

From this, it can be determined that the minimum required capacity of the ESU is:

$$E_{\mathrm{ESU},\mathrm{nom}}={\displaystyle \frac{1}{{\eta }_{\mathrm{dc}}\left(S_{\mathrm{SOC},\max }-S_{\mathrm{SOC},\min }\right)}}{\displaystyle {\int }_{t_2}^{t_2+T_{\mathrm{FRT}}}{P}_{\mathrm{ESU},\mathrm{nom}}\mathrm{d}t}$$

(10)

In the equation, E_ESU,nom is the rated capacity of the ESU; t₂ is the time at which the ESU begins to absorb excess power; ${\eta }_{\mathrm{dc}}$ is the DC/DC converter efficiency; $S_{\mathrm{SOC},\max }$ and $S_{\mathrm{SOC},\min }$ denote the allowable SOC upper and lower limits; T_FRT is the required FRT duration.

The effective available capacity is reduced by the SOC reserve margin, lithium-ion battery degradation and current limits are implicitly considered through conservative capacity sizing.

Although the present study prioritizes active power regulation for clarity, the proposed voltage-triggered coordination is conceptually compatible with grid-code-mandated reactive current injection, provided the 1.1 p.u. converter current limit is shared between active and reactive components. However, detailed validation of specific grid-code compliance under reactive-priority modes is outside the scope of this work.

3. Results and Discussion

In this section, a wind power grid-connected system via MMC-HVDC, as shown in Figure 1, is constructed on the PSCAD/EMTDC simulation platform, and the validity of the schemes proposed in the preceding sections is verified. At t = 5 s, a three-phase short-circuit fault and a single-phase short-to-ground (SLG) fault occur at the locations shown in Figure 1 in the AC power distribution network, causing the voltage to drop to 0.2 times and 0.6 times the rated value, respectively. Both faults last for 625 ms.

The system simulation parameters are shown in

Table 2. System simulation parameters.

Parameters	Values
Rated AC-side voltage/kV	220
Rated DC-side voltage/kV	±400
Single-pole converter transformer ratio/(kV/kV)	220/210
Rated capacity of single-pole converter station/MVA	400
Number of submodules/unit	200
Submodule capacitance/μF	10,000
Arm reactor inductance/mH	29
Overhead line length/km	200
The rated power PMSG/MW	5
Number of PMSGs shown in figures/unit	2*
ESU rated capacity/kWh	2.5
SOC operating limits	0.2–0.9
DC/DC efficiency	0.95
DC bus voltage/kV	1
Max charge/discharge current/kA	1.2

* The WF consists of 80 PMSG units, each rated at 5 MW, giving a total rated capacity of 400 MW. All PMSG units participate in the simulation. For clarity and readability, only the results of two representative units (WG1 and WG2) are shown in the figures.

and

Table 3. System control parameters.

Converter	Inner Loop Proportional/Integral Parameters	Outer Loop Proportional/Integral Parameters
GSMMC	1.8/0.2	2.5/25
WFMMC	0.3/0.5	2.5/30
WTVSC	1.0/0.5	2.0/10
GSVSC	1.5/1.0	1.5/50

. The WF delivering its rated active power of 400 MW. The initial SOC values of the ESUs are set to 0.60 and 0.40 for WG1 and WG2, respectively, representing relatively high and moderate SOC levels.

The PI controller parameters listed in Table 3 were obtained through a systematic trial-and-error tuning procedure based on the linearized small-signal model of the MMC-HVDC system. The tuning process prioritized closed-loop stability, sufficient phase margin, and adequate damping of low-frequency oscillations. The bandwidth of each control loop was selected to ensure fast dynamic response without exciting the resonant modes of the MMC arm circuits. Robustness against parameter variations and fault transients was verified through extensive time-domain simulations under various operating conditions, confirming that the selected gains provide stable and reliable performance for the proposed control strategies. A detailed small-signal-based PI tuning methodology for MMC systems can be found in [30], as the parameter tuning of converters is not the primary research focus of this paper and is therefore not elaborated upon in detail.

3.1. Simulation and Verification of Power-Dissipating Resistors

Figure 6 shows the system simulation waveforms for the energy-dissipating resistor scheme. As shown in Figure 6a,b, at t = 5 s, the AC voltage at the load end drops to 0.2 p.u., while the voltage at the PCC of the WF remains essentially stable. At this point, as shown in Figure 6d, the WF continues to output approximately 400 MW of active power, while the active power input to the GSMMC drops sharply to around 110 MW, causing the positive and negative DC voltages to gradually rise.

As shown in Figure 6c,e, when the DC voltage rises to 1.05 p.u., the trigger pulse for the energy-dissipating resistor goes high, the switching transistor turns on, the resistor is engaged to dissipate power, and the DC voltage subsequently drops. When the voltage drops to 0.95 p.u., the trigger pulse goes low, the switching transistor turns off, the resistor is disengaged, and the DC voltage rises again. Through the repeated switching of the dissipation resistor, the DC voltage is limited to the range of 0.95–1.05 p.u.

Throughout the entire fault period, as shown in Figure 6f, the approximately 110 MJ of energy absorbed by the dissipation resistor is ultimately dissipated as thermal energy. When the fault is cleared at t = 5.625 s, the GSMMC’s transmission capability is restored, the DC voltage stabilizes at the rated value, and the dissipation resistor is deactivated.

The resistor hysteresis band is set to 0.95–1.05 p.u. to represent a typical industrial configuration. It is important to note that both the braking resistor scheme and the proposed strategies are evaluated under the same DC voltage threshold constraint of 1.1 p.u. While the resistor strictly limits the voltage within a narrow band to ensure rigidity, the proposed strategies allow the DC voltage to approach the 1.1 p.u. limit to avoid energy dissipation. This comparison under equal constraints demonstrates that our strategies achieve effective overvoltage suppression without the energy waste associated with resistive braking.

3.2. Simulation Validation of the Proposed Control Strategy

Figure 7 shows the system simulation waveforms under Control Strategy 1. As shown in Figure 7a,b, an AC fault occurs at t = 5 s. Before the control strategy is activated, the power fed into the AC system by the GSMMC drops sharply to approximately 110 MW, while the WF continues to supply approximately 400 MW of active power to the WFMMC. As shown in Figure 7c, the AC voltage on the WF side drops to approximately 0.6 p.u. As shown in Figure 7d, the DC voltage begins to rise due to the presence of unbalanced power. When the DC voltage rises to 1.05 p.u., the WFMMC reduces the PCC voltage according to Equation (3).

As shown in Figure 7e, the actual PCC voltage tracks the reference value well. When the PCC voltage falls below 0.95 p.u., the ESS begins to absorb active power according to the power reference values specified in Equations (5)–(9). The power reference values and actual values absorbed by the ESS are shown in Figure 7f. As can be seen from the figure, the energy storage within WG1 is assigned approximately 2.7 MW of power due to its higher SOC, while the energy storage within WG2 is assigned approximately 4 MW of power due to its lower SOC. After the ESS absorbs power, the system DC voltage gradually stabilizes at around 1.08 p.u. and does not exceed the upper limit of 1.1 p.u. during the fault.

As shown in Figure 7g,h, when the internal DC voltage of the WT begins to drop due to energy storage power absorption, the grid-side converter of the WT acts to stabilize the DC voltage, reducing the power supplied by the WT to the HVDC system and maintaining the internal DC voltage of the WT within the range of 0.9–1.1 p.u., thereby achieving load shedding of the WF during the fault. As shown in Figure 7i,j, to verify the effectiveness of the proposed Control Strategy 1 and thereby maximize the system’s safety margin, Strategy 1 was compared with a conventional control strategy (based on proportional allocation of rated power). Under the conventional strategy, the variance in the SOC of each ESU remained unchanged, indicating that the gap in remaining capacity between the SOCs was not reduced. In contrast, the proposed Strategy 1 reduces the variance among ESUs by transferring more redundant power to the ESU of WG2. This indicates that Strategy 1 can effectively minimize peak SOC and prevent premature shutdown.

To further validate the overcurrent safety of the system during the fault, Figure 7k presents the three-phase current waveforms at the AC side of the GSMMC. As shown, throughout the entire fault duration from 5.0 s to 5.625 s, although the current waveforms exhibit distortion, their peak envelope is strictly confined within 1.1 p.u., with the actual peak measuring approximately 1.04 p.u. Consequently, the GSMMC operates within the predefined safe current range, eliminating any risk of equipment overcurrent.

At t = 5.625 s, the system fault was cleared. As shown in Figure 7b, the power injected into the system by the GSMMC gradually increased. At this point, as shown in Figure 7d, the DC voltage begins to decrease. When the DC voltage drops to 1.05 p.u., as shown in Figure 7e, the voltage at the PCC returns to the rated voltage. During the voltage recovery period, when the voltage at the PCC rises to 0.95 p.u., as shown in Figure 7f, the power reference value of the ESS becomes 0, and it no longer absorbs power. As shown in Figure 7h, after the ESS stops absorbing power, the internal DC voltage of the WT begins to rise. To maintain a stable DC voltage, the WT’s GSVSC gradually increases the power supplied by the WT to the HVDC system. When all parameters return to their rated values, the system enters normal operation, completing the AC-FRT process.

3.3. Verification of Ride-Through Strategy for Single-Phase Ground Faults in Receiver-Side AC Systems

To ensure the integrity of the simulation, a simulation was conducted to verify the system’s SLG fault in the receiving AC grid. Since this fault is a relatively minor scenario, Control Strategy 1 was adopted.

Figure 8 shows the system simulation waveforms under Control Strategy 1 during a SLG fault at the grid-side AC grid, with the WF operating at 70% of its rated power.

As shown in Figure 8a, the AC fault occurs at t = 5 s. Before the control strategy is activated, the active power fed into the AC system by the GSMMC drops sharply to approximately 80 MW, while the wind farm continues to supply approximately 280 MW of active power to the WFMMC. Consequently, as shown in Figure 8b, the receiving-end AC voltage drops to approximately 0.60 p.u.

As shown in Figure 8c, the PCC voltage dropped to approximately 0.8 p.u. during the fault. As shown in Figure 8d, the DC bus voltage begins to rise due to the power imbalance. When the DC voltage reaches the threshold of 1.05 p.u., the WFMMC reduces the PCC voltage according to Equation (3). Figure 8c confirms that the actual PCC voltage tracks the reference value well despite the negative-sequence component introduced by the SLG fault.

When the PCC voltage falls below 0.95 p.u., the ESS begins to absorb active power. As shown in Figure 8e, the power reference and actual absorbed power are presented. Due to the lower overall wind power output, the ESS absorbs approximately 2.0 MW and 2.8 MW for WG1 and WG2, respectively. As shown in Figure 8d, this reduction in redundant power effectively stabilizes the DC voltage at approximately 1.06 p.u., a value that remains well below the 1.1 p.u. limit.

As shown in Figure 8f, the SOC trajectories of the ESUs are depicted. Consistent with the power allocation logic, the lower-SOC unit (WG2) receives more power, while the higher-SOC unit (WG1) receives less. This demonstrates that Strategy 1 maintains its SOC-balancing capability even under asymmetric fault conditions and partial-load operation, effectively minimizing the peak SOC and avoiding premature shutdown.

At t = 5.625 s, the SLG fault is cleared. As shown in Figure 8a, the active power transmitted by the GSMMC gradually recovers to approximately 280 MW. As shown in Figure 8d, the DC bus voltage begins to decrease from its peak of 1.06 p.u.

When the DC voltage drops back to the threshold of 1.05 p.u., the WFMMC ceases to depress the PCC voltage, and the voltage at the PCC returns to the rated value of 1.0 p.u., as illustrated in Figure 8c. As shown in Figure 8e, during this recovery period, once the PCC voltage rises above 0.95 p.u., the ESS power reference resets to zero, and the ESUs stop absorbing power.

Subsequently, as indicated in Figure 8f, the proposed control strategy can still reduce the variance among the ESUs when the SLG fails, i.e., it reduces the SOC among the ESUs. With the cessation of ESS absorption, the internal DC voltage of the WTs begins to recover. To maintain this internal voltage, as shown in Figure 8a, the WTs’ GSVSCs gradually ramp up the power supplied to the MMC-HVDC system. By t = 5.8 s, all system parameters have returned to their rated steady-state values, successfully completing the AC-FRT process under partial-load conditions.

4. Conclusions

This paper investigates the DC overvoltage issue in wind power HVDC grid-connected systems during receiving-end AC faults. An energy storage coordinated control strategy is proposed, and its effectiveness is verified through simulation. The conclusions are as follows:

(1)

A DC overvoltage suppression strategy based on wind-storage DC-side coordination is proposed. This strategy optimizes power allocation inversely proportional to SOC to prevent overcharge and maximize the utilization of available storage capacity. By relying on localized ESS absorption, the strategy eliminates the need for source-side WT load shedding, making it particularly suitable for scenarios with sufficient storage resources.

(2)

The robustness of the proposed strategy under asymmetric fault conditions has been confirmed. Although the primary validation focused on severe three-phase short-circuit faults, simulation results demonstrate that the control strategy still effectively suppresses DC overvoltage during a single-line-to-ground (SLG) fault when the WF operates at 70% capacity. Since the control logic is triggered by the PCC voltage magnitude rather than sequence components, it remains effective despite the presence of negative-sequence voltages. Nevertheless, a comprehensive investigation into negative-sequence current suppression and unbalanced dynamics is reserved for future work.

(3)

The strategy achieves overall control through DC-side coordination between WTs and ESS, eliminating the need for additional equipment (such as braking resistors) and reducing costs. Compared to traditional energy-dissipating resistor solutions, the proposed strategy exhibits smaller DC voltage fluctuations and smoother responses, while completely avoiding energy waste. While the present study focuses on active power coordination, the integration of grid-code-mandated reactive current support under current limiting constraints is identified as a key extension for future work.