Energy Stability Strategy for Photovoltaic DC Energy Systems Using Supercapacitor-Based Ride-Through Control and Required Capacity Sizing

Abstract

Standalone photovoltaic DC energy systems must maintain bus voltage stability without grid support; however, abrupt load variations can cause a DC-bus voltage drop, reducing system reliability and disturbing connected equipment. Although battery-based energy storage is effective for long-duration power balancing, its response to instantaneous disturbances can be limited. This study proposes an energy stability strategy using supercapacitor-based ride-through control and required capacity sizing for fast DC-bus voltage support. The proposed controller continuously monitors the DC-bus voltage and, when a voltage drop is detected, immediately triggers supercapacitor discharge to compensate for the power deficit until the bus recovers. In addition, a design formulation is derived to estimate the required compensation energy, ride-through time, and minimum capacitance based on the expected power deficit, allowable DC-bus voltage drop, and initial supercapacitor voltage. Simulation results under step changes in load resistance show that the supercapacitor sized by the proposed method maintains the DC-bus voltage close to its reference value within the specified limit. Hardware experiments further validate the ride-through operation and show good agreement between the predicted and measured compensation times.

1. Introduction

The rapid deployment of renewable generation has increased the interest in stand-alone and microgrid-scale power systems that must regulate voltage and power without strong grid support. In these settings, inverter-based resources are expected not only to inject current but also to establish and maintain the system voltage and frequency. This trend has accelerated the adoption of grid-forming inverters, which can autonomously set the AC voltage/frequency reference and synchronize it through power-based control, unlike grid-following inverters, whose Phase-Locked Loop (PLL)-based voltage tracking can be challenging in weak-grid or low-inertia conditions [1,2,3,4]. Because grid-forming operation ultimately depends on a stable DC energy buffer, maintaining the DC bus voltage is a critical requirement for power quality and reliable operation [4].

In standalone photovoltaic (PV) systems, irradiance variability and abrupt load changes can produce instantaneous DC bus voltage drops or overshoots, which may propagate to the inverter’s AC output and trigger a degraded power quality or protective shutdown. To mitigate these transients, many studies have integrated supercapacitors at the inverter DC-link or upstream converter stage, either as an auxiliary energy path or as part of hybrid battery–supercapacitor storage. Specifically, supercapacitor-based energy support has been utilized to improve low-voltage or fault ride-through capabilities in wind and solar power generation systems [5,6,7,8,9]. Furthermore, such configurations have demonstrated significant benefits in reducing transient voltage stresses [10], smoothing power fluctuations, and enhancing overall system reliability [11,12,13]. However, existing approaches commonly select supercapacitor capacitance empirically or validate their performance only under a limited set of operating conditions, providing little guidance for quantitative sizing that explicitly reflects the expected load disturbance magnitude and allowable DC bus voltage deviation. This gap can lead to undersizing or oversizing.

To address these gaps, this study proposes a supercapacitor-based ride-through control strategy for fast DC bus compensation, coupled with an energy-based capacitance design procedure. First, this work delivers a significant advancement by deriving a deterministic analytical formula to determine the minimum required capacitance based on the quantitative power deficit ($P_{def}$) and the allowable DC bus voltage drop, providing a rigorous alternative to conventional trial-and-error approaches. Second, a systematic state-machine triggering logic comprising ARM, HOLD, and SUPPORT modes is established on a high-speed digital controller to prevent false activations from transient noise. Finally, the mathematical consistency and dynamic effectiveness of the proposed sizing method are thoroughly validated through both time-domain PSIM simulations and scaled laboratory-scale hardware experiments.

The remainder of this paper is organized as follows. Section 2 outlines the operating principles of the ride-through control loop and derives the required capacitance sizing formulation. Section 3 presents the simulation and hardware experimental validation results, along with a detailed description of the laboratory setup. Section 4 provides a comprehensive discussion on the scholarly positioning and operational boundary conditions of the proposed method, and Section 5 concludes the paper.

2. Application of Ride-Through Control in Photovoltaic Systems

2.1. DC Bus Voltage Instability in Standalone PV Systems

In standalone PV-based grid-forming systems, the inverter autonomously establishes the grid voltage and frequency; therefore, the DC bus must continuously provide a stable DC voltage to the inverter even under PV power fluctuations and abrupt load changes. In practical operation, however, a power imbalance between the generated power and load demand repeatedly occurs over short timescales, which can cause instantaneous DC bus voltage drops or transient over-voltages.

The primary cause of DC bus voltage instability is the mismatch between the source power $P_{src}$ and load power $P_{load}$. In particular, when the load increases sharply, the PV flyback converter may not be able to supply the required power immediately owing to its dynamic and control bandwidth limitations, thereby inducing a DC bus voltage drop. This mismatch can be defined as a deficit power $P_{def}$, and is given as

$$P_{def}=P_{load}-P_{src}$$

(1)

Such a deficit power can directly deteriorate the voltage and frequency quality generated by the inverter in grid-forming systems, leading to degraded power quality and unstable system operation.

2.2. Features of Supercapacitors

Supercapacitors provide a high power density owing to their low equivalent series resistance and very fast charge–discharge response, and they exhibit minimal performance degradation even after hundreds of thousands of cycles, making them well suited for transient power compensation [14,15,16]. They can rapidly supply or absorb energy when the DC bus voltage deviates from its reference value, thereby reducing the burden on the grid-forming inverter for maintaining the system voltage and frequency.

The electrical characteristics of a supercapacitor are commonly modeled using equivalent series resistance (ESR) [16], parallel leakage resistance $R_p$, and capacitance C (Figure 1). Accordingly, the equivalent impedance in the frequency domain can be approximated as

$$Z_{sc}\left(jw\right)\approx R_{ESR}+{\displaystyle \frac{1}{jwC}}$$

(2)

Although a low ESR is advantageous for transient power compensation, directly connecting a supercapacitor to a DC bus can induce a large current inrush [14,16]. The initial inrush current is determined by Equation (3). A smaller $R_{ESR}$ results in a higher current, imposing electrical and thermal stresses on the switching devices.

$$i\left(0\right)={\displaystyle \frac{V_{bus}-V_c\left(0\right)}{R_{ESR}}}\approx {\displaystyle \frac{V_{bus}}{R_{ESR}}}$$

(3)

where $V_{bus}$ denotes the DC bus voltage. Therefore, in this study, the supercapacitor was not directly connected to the DC bus. Instead, a bidirectional flyback converter with Constant Current (CC)–Constant Voltage (CV) charging and a soft-start scheme were employed to limit the initial current. Beyond current limiting, the bidirectional converter provides essential voltage decoupling between the wide operating range of the supercapacitor and the stable DC bus, ensuring precisely controlled power flow during ride-through operations [17,18].

While more complex models considering parasitic inductive effects and frequency-dependent ESR are available for high-frequency transient analysis, the classic series $RC$ model is adopted in this study. This simplification is justified as the primary objective is to evaluate the low-frequency energy balance and the total ride-through duration. For capacitance sizing based on deficit power, this model provides sufficient accuracy while maintaining analytical clarity for engineering applications.

2.3. Ride-Through Control Using Supercapacitors

Ride-through refers to the capability of a system to maintain continuous operation for a certain period without immediate shutdown [5,6,7,8], even under grid disturbances or external perturbations (Figure 2). In this study, it was applied to the DC bus voltage drop caused by abrupt load changes in a standalone PV-based grid-forming system [6,10,11]. The objective is to compensate for the deficit power $P_{def}$ induced by load transients through supercapacitor discharge, thereby maintaining the DC bus voltage within an allowable range and ensuring stable inverter operation.

However, ride-through compensation performance strongly depends on the capacitance of the supercapacitor. If the capacitance is undersized, the available stored energy may be insufficient to meet the target compensation duration, leading to an excessive DC bus voltage drop and potentially triggering protective actions or a shutdown. Conversely, oversizing can improve transient support but unnecessarily increases the system cost and volume [5,7,9,12], reducing the overall practicality. Therefore, a quantitative sizing procedure that determines the minimum required capacitance based on the magnitude of the load disturbance and the allowable voltage drop is essential.

The overview and operating logic of ride-through control are as follows: The DC bus voltage $V_{\mathrm{b}\mathrm{u}\mathrm{s}}$ is monitored in real time, and a ride-through action is triggered when $V_{bus}$ deviates from the allowable range around the reference voltage or when a voltage drop is detected. If the supercapacitor voltage $V_{sc}$ lies within the prescribed operating range, a compensation flag is enabled, and a discharge command is generated to inject power into the DC bus through the bidirectional converter. During discharge, the ride-through operation is terminated, and the system returns to the standby state once the DC bus voltage recovers and re-enters the normal range, or once the supercapacitor voltage reaches its minimum allowable value.

Under an abrupt load change, the deficit power required at the DC bus is given by Equation (1). When $P_{def}>0$, insufficient source power is available, and the supercapacitor must compensate for this deficit by discharging. Assuming that the deficit power is compensated as a constant power, the energy required by the DC bus over the compensation interval $t_{hold}$ is

$$E_{req}=P_{def}\times t_{hold}$$

(4)

The ideal stored energy that a supercapacitor ($E_{cap}$) can provide for power compensation is limited by the initial and final voltages, and can be expressed as

$$E_{cap}={\displaystyle \frac{1}{2}}{C}_{sc}(V_{max}^2-V_{min}^2)$$

(5)

where $C_{sc}$ is the supercapacitor capacitance, $V_{max}$ is the discharge-start voltage, and $V_{min}$ is the minimum allowable voltage to prevent overdischarge. In practical compensation, the energy delivered to the DC bus is reduced owing to the conversion efficiency $\eta$ and ESR-related losses; thus, the effective energy $E_{eff}$ can be expressed as follows:

$$E_{eff}=\{{\displaystyle \frac{1}{2}}{C}_{sc}\left(V_{max}^2-V_{min}^2\right)-{(R}_{ESR}\times P_{def}\times C_{sc}\times \mathrm{l}\mathrm{n}{\displaystyle \frac{V_{max}}{V_{min}}})\} \ast \eta$$

(6)

To ensure the reproducibility of the predicted effective energy ($E_{eff}$) and ride-through duration ($t_{hold}$), the exact operational parameters utilized in the theoretical calculations are specified as follows: the nominal DC-bus voltage $V_{Bus}$ = 50 V, the minimum allowable voltage drop $V_{min}$ = 45 V, the measured converter efficiency $\eta$ = 92.4%, and the equivalent series resistance $R_{ESR}$ = 0.12 Ω. Using these static design values, any independent researcher can identically reproduce the analytical results yielded by Equations (6) and (7).

Here, “$\eta$” represents the power conversion efficiency of the bidirectional DC-DC converter, accounting for the losses during the energy transfer between the supercapacitor and the DC bus.

Therefore, assuming that the deficit power is compensated for as a constant power, the ride-through sustained time achieved using the supercapacitor is derived as

$$t_{hold}={\displaystyle \frac{E_{eff}}{P_{def}}}$$

(7)

Given a target ride-through time $t_{req}$, the minimum required supercapacitor capacitance based on the ideal model is as follows:

$$C_{sc,min}={\displaystyle \frac{2P_{def}\times t_{req}}{\eta (V_{max}^2-V_{min}^2)}}$$

(8)

In a practical design, it is advisable to apply a safety margin by accounting for variations in efficiency, ESR, sensing errors, and uncertainties associated with disturbances. Overall, the equations derived in this section provide a quantitative design basis for determining a supercapacitor capacitance that satisfies the required compensation duration.

2.4. Operating Scenarios and Performance Evaluation Metrics

The deficit-power-based compensation formulation and ride-through time derivation presented in Section 2.3 were validated through PSIM simulation. In both the simulation and experiments, abrupt operating conditions frequently encountered in standalone PV systems, such as step changes in load resistance, were considered, and supercapacitor discharge compensation was applied based on the corresponding deficit power $P_{\mathrm{d}\mathrm{e}\mathrm{f}}$ during the transient interval. The results showed that when the supercapacitor capacitance was selected according to the proposed design equations, the DC bus voltage drop was confined within the specified allowable range, and the transient response exhibited a stable recovery to the normal operating region. In addition, the ride-through duration during the compensation interval showed an overall agreement between the analytically predicted time and the time observed in the simulation, confirming that the proposed quantitative sizing procedure is effective in determining the capacitance required to meet the target compensation time.

Figure 3 illustrates the simplified equivalent circuit used for the analytical derivation. In this model, $V_{sc}$ denotes the supercapacitor voltage, while $L$ and $D$ represent the equivalent inductance and diode for energy transfer, respectively. $C_{bus}$ indicates the DC-bus capacitance, and $V_o$ represents the target DC-bus voltage (50 V) maintained during the ride-through operation. This idealized configuration focuses on the fundamental power flow from the supercapacitor to the load, providing a basis for calculating the required capacitance.

To verify the validity of the deficit power estimation for ride-through control, simulations were conducted using the circuit shown in Figure 3; the parameters are listed in

Table 1. Simulation parameters for analytical verification.

Flyback Converter		Supercapacitor Converter
Parameter	Value	Parameter	Value
$P_{max}$ [W]	45	$C_{sc}$ [F]	4.7
$V_{max}$ [V]	50	$V_{min}$ [V]	10
$Load$ [Ω]	60–>20

.

$$P_{load}={\displaystyle \frac{{50}^2}{20}}=125 \left[\mathrm{W}\right] P_{src}\approx 45 \left[\mathrm{W}\right] P_{def}\approx 80 [\mathrm{W}]$$

(9)

$$E_{eff}={\displaystyle \frac{1}{2}}\times 4.7\left({50}^2-{10}^2\right)\approx 5640\times \eta =5402 \left[\mathrm{J}\right]$$

(10)

$$5402-12.1 \approx 5390.3 \left[\mathrm{J}\right]$$

(11)

$$t_{hold}={\displaystyle \frac{E_{eff}}{P_{def}}}\approx {\displaystyle \frac{5390.3}{80}}\approx 67.5 [\mathrm{s}]$$

(12)

Figure 4 presents the detailed transient responses during the ride-through operation. Specifically, Figure 4a shows the time-domain responses of the DC bus voltage and the ride-through compensation signal, while Figure 4b presents the voltage and current waveforms of the supercapacitor. When the load mutation occurs, the DC bus voltage initially drops, but the proposed control strategy immediately triggers the bidirectional converter. The voltage recovery dynamics exhibit a rapid stabilization back to the target operating range within a few milliseconds, demonstrating that the PI controller effectively regulates the power flow from the supercapacitor.

In the PSIM simulation performed with the design capacity of 4.7 F, the compensation hold time calculated from the ideal mathematical model is (67.41 s), and the observed simulation hold time is (67.50 s). The discrepancy between the two results is (0.09 s), which is primarily attributed to the inherent limitation of the discrete Perturb and Observe (P&O) Maximum Power Point Tracking (MPPT) method [13,19]. In this discrete control scheme, the PV output voltage continuously oscillates around the Maximum Power Point, meaning that the $P_{def}$ cannot be maintained as a perfectly constant value, leading to the minor timing deviation.

In practical standalone PV systems, large-capacity supercapacitors on the order of a few to several tens of farads are required to achieve such long-term ride-through capability. However, this study primarily focused on validating the fundamental operating principle of the ride-through control loop and its transient response characteristics at the DC bus side. Therefore, for feasible laboratory-scale hardware verification, the capacitance was intentionally scaled down to (4700 µF) while keeping the underlying control structure and voltage variation mechanism identical. It should be noted as a boundary condition that this laboratory-scale setup was utilized to verify the mathematical validity of the capacity sizing method and the dynamic performance of the controller under scaled conditions, rather than replicating the longhold-time energy capacity or the complex electrochemical behavior inherent to full-scale supercapacitor modules.

This section describes the hardware setup and operating scenarios used to experimentally validate sizing of the supercapacitor capacitance based on the deficit power. The experimental system consisted of a flyback converter driven by a PV panel as the input source and a bidirectional flyback converter that charged and discharged the supercapacitor [14,20]. The system operates in two modes: (i) the charging mode, which prepares the supercapacitor to a target voltage using CC–CV control with a soft start, and (ii) the discharging (ride-through) mode, which compensates for the deficit power caused by abrupt load changes (Figure 5) [14,17,18].

As illustrated in the detailed control structure (Figure 5), the ride-through operation is governed by a digital PI controller implemented on a TMS320F28335 DSP (Texas Instruments, Dallas, TX, USA). To ensure both stability and a rapid dynamic response during transients, the control system employs a dual-loop configuration or a direct voltage regulation loop with high-speed execution at a sampling frequency of 20 kHz. The proportional and integral gains for the DC-bus voltage regulation were designed based on the bandwidth requirements and fine-tuned to $K_{\mathrm{p}\_\mathrm{b}\mathrm{u}\mathrm{s}}$ = 0.1 and $K_{\mathrm{i}\_\mathrm{b}\mathrm{u}\mathrm{s}}$ = 8.0. Furthermore, a slew-rate limit ($D_{\mathrm{s}\mathrm{l}\mathrm{e}\mathrm{w}\_\mathrm{u}\mathrm{p}}$ = 0.10) was applied to the duty cycle command to mitigate transient overshoots while ensuring the controller reacts within a few milliseconds. This identical control architecture and set of gains were utilized in both the PSIM simulations and hardware experiments to maintain consistency in performance validation.

The proposed ride-through control strategy is executed through a systematic state-machine logic consisting of ARM, HOLD, and SUPPORT modes to ensure reliable operation. In the ARM mode, the system waits until the DC-bus voltage stabilizes above a predefined arming threshold (49.0 V) for a specific duration (50 ms). Once armed, the system enters the HOLD mode, where it continuously monitors the bus voltage without triggering the converter. The transition to the SUPPORT (discharging) mode is initiated only when a significant voltage sag is detected—specifically, when the filtered bus voltage drops below a relative threshold (1.0 V drop) or an absolute limit (49.0 V) for at least 30 consecutive samples (1.5 ms). This multi-stage triggering logic prevents unintended activations caused by transient noise and ensures that the supercapacitor power is injected precisely when the ride-through capability is required. The compensation continues until the bus voltage recovers or the supercapacitor reaches its lower voltage limit, at which point the system safely resets to the standby state.

The experimental procedure was as follows. The supercapacitor is first charged within the prescribed voltage window ($V_{max}$–$V_{min}$) and the system then enters a standby state in which the DC bus voltage $V_{\mathrm{b}\mathrm{u}\mathrm{s}}$ is continuously monitored. At a specified time, the load was varied in a stepwise manner (e.g., by reducing the load resistance) to intentionally induce a DC bus voltage drop, and the compensation power level was determined based on the resulting deficit power $P_{def}$. When a voltage drop is detected, the system transitions to discharging mode and injects power into the DC bus through the bidirectional converter. The compensation is terminated when the supercapacitor voltage reaches $V_{min}$ or when the DC bus voltage recovers to the normal operating range. The experimental validation focuses on compliance with the allowable voltage-drop criterion and the reproducibility of the ride-through duration to assess the appropriateness of capacitance sizing.

Figure 3 presents the simplified circuit diagram used for the analytical derivation and simulation of the required capacitance sizing. For the actual hardware implementation, a bidirectional flyback converter topology was employed, as detailed in the control structure of Figure 5.

3. Results

3.1. Design and Fabrication of the PV Converter and Bidirectional Converter for the Supercapacitor

This section covers the hardware experiments that evaluate the DC bus voltage stabilization using a supercapacitor-based ride-through control scheme.

The experimental platform (Figure 6) consisted of a PV flyback converter and bidirectional flyback converter interfacing the supercapacitor with integrated control implemented on a TMS320F28335 DSP. A PV supply and a PV flyback converter emulate the standalone PV operation by generating power via MPPT and delivering it to the load, including voltage/current sensing for MPPT, voltage/current sensing for the supercapacitor, and DC bus voltage sensing. Specifically, for this laboratory-scale validation, an electrolytic capacitor (4700 μF) was utilized as a scaled energy storage element instead of a commercial farad-scale supercapacitor. To establish a clear boundary condition for this validation, it must be noted that an electrolytic capacitor cannot fully replicate the comprehensive electrochemical characteristics of a true supercapacitor, such as frequency-dependent Equivalent Series Resistance (ESR), complex internal self-discharge mechanisms, degradation from long-term aging, or macro-scale thermal variations. However, the scope of this experimental validation is strictly confined to proving the fundamental operating principle of the ride-through control loop and confirming the mathematical scalability of the derived minimum required capacitance formula under a controlled hardware power rating. By focusing on the transient energy balance during short-term disturbances rather than the specific chemical properties of the storage medium, this scaled setup provides a scientifically rigorous proof-of-concept validation without making claims that extend beyond the laboratory test conditions. Since the experimental results demonstrate a high correlation between the predicted and measured times, the proposed methodology is proven to be physically valid and scalable regardless of the specific capacitance range. The circuit configuration and control architecture are shown in Figure 5, and the system parameters are summarized in

Table 2. PV flyback converter specifications for experiments.

Component	Description	Parameter	Value
Current Sensor	LA25-P	${C_1 \mathrm{and} C}_2$ [μF]	1000
Diode	MBR20200CT	$f_{sw}$ [kHz]	20
MOSFET	C3M0120090	$N_1:N_2$	11:11
Voltage Sensor	LV25-P
MCU	TMS320F28335

and

Table 3. Supercapacitor converter specifications for experiments.

Component	Description	Parameter	Value
Electrolytic Capacitor	B43733	$f_{sw}$ [kHz]	20
Diode	MBR20200CT	$N_1:N_2$	11:11
Voltage Sensor	LV25-P
MOSFET	W33N60E

.

3.2. Experimental Validation of the Supercapacitor-Based Ride-Through Control and Capacitance Sizing Method

This section compares the ride-through compensation performance in terms of the compensation duration and success of compensation as a function of the supercapacitor capacitance under deficit-power conditions caused by abrupt load changes. Figure 7 shows the experimental waveforms obtained when the load resistance decreased from. $R_1=60 \mathsf{\Omega }$ to $R_2=50 \mathsf{\Omega }$ Figure 7a,d present the ride-through compensation results using the capacitance calculated by the proposed sizing equation, $C_{cal}=4700 \mathsf{\mu }\mathrm{F}$, whereas Figure 7b,e and Figure 7c,f, show the results obtained using the arbitrarily selected capacitances $C_{Ran1}=2200 \mathsf{\mu }\mathrm{F}$ and $C_{Ran2}=1000 \mathsf{\mu }\mathrm{F}$, respectively. For this load-change condition, the calculated deficit power was $P_{def}=5 \mathrm{W}$. Ride-through compensation was successfully achieved for all tested capacitances, and the measured compensation durations were 1.004 s, 0.479 s, and 0.223 s for $C_{cal}$, $C_{Ran1}$, $C_{Ran2}$ respectively. Overall, a larger capacitance resulted in a longer compensation duration. Similar tendencies were also observed in Figure 8, Figure 9 and Figure 10 for the other load-change conditions. As the deficit power increased, the compensation duration decreased for all capacitance cases, and ride-through failure occurred in some cases with arbitrarily selected capacitances. The detailed experimental results for all load variations are summarized in

Table 4. Ride-through experiment results.

$\mathit{R}\mathsf{\Omega }$	${\mathit{P}}_{\mathit{d}\mathit{e}\mathit{f}}$	${\mathit{C}}_{\mathit{c}\mathit{a}\mathit{l}}$	${\mathit{C}}_{\mathit{R}\mathit{a}\mathit{n}1}$	${\mathit{C}}_{\mathit{R}\mathit{a}\mathit{n}2}$	$\mathit{R}\mathsf{\Omega }$	${\mathit{P}}_{\mathit{d}\mathit{e}\mathit{f}}$	${\mathit{C}}_{\mathit{c}\mathit{a}\mathit{l}}$	${\mathit{C}}_{\mathit{R}\mathit{a}\mathit{n}1}$	${\mathit{C}}_{\mathit{R}\mathit{a}\mathit{n}2}$
50	5	1.004	0.479	0.223	30	38.33	0.134	0.058	0.022
45	10.55	0.487	0.226	0.112	25	55	0.091	0.033	0.012
40	17.5	0.29	0.136	0.061	20	80	0.063	0.023	Fail
35	26.42	0.19	0.089	0.035	15	121.66	0.011	Fail	Fail

.

The same experimental procedure was repeated under additional load-step conditions to evaluate the ride-through behavior at different deficit power levels. The load resistance was sequentially reduced from 60 Ω to 45, 40, 35, 30, 25, 20, and 15 Ω. For all tested cases, the capacitance calculated using the proposed sizing equation $C_{cal}$ successfully maintained the DC bus voltage within the allowable range during the designed compensation interval. This indicates that the proposed sizing method provides sufficient energy capacity to satisfy the required ride-through condition without requiring an excessive capacitance. In contrast, when smaller arbitrarily selected capacitances ($C_{Ran1},C_{Ran2}$) were applied, the compensation duration decreased because of insufficient stored energy, and ride-through failure occurred under larger load disturbances, where the required compensation time could not be sustained. These results show that the ride-through duration is determined by the relationship between the available supercapacitor energy and the deficit power generated by the load change, and confirm that the proposed method enables the selection of an appropriate capacitance that satisfies the compensation requirement while avoiding unnecessary oversizing.

The measured compensation durations for all load step conditions are summarized in Table 4. As the load resistance decreases, the deficit power increases, resulting in a reduced compensation duration for a given capacitance. The capacitance calculated using the proposed sizing equation consistently satisfied the required compensation condition, whereas smaller arbitrarily selected capacitances failed to sustain ride-through operations under larger deficit power conditions.

4. Discussion

The objective of the proposed method is not to maximize the ride-through performance by increasing the supercapacitor capacitance but to determine the minimum capacitance required to satisfy the compensation condition under a given deficit-power scenario. The experimental results demonstrate that the ride-through duration is primarily governed by the relationship between the available stored energy in the supercapacitor and the deficit power generated by abrupt load variations. This observation is consistent with the analytical formulation derived in Section 2, where the achievable compensation time is determined by the ratio between the effective stored energy and the deficit power.

Furthermore, while this study primarily demonstrates the compensation for load-induced transients, the derived analytical formula is equally applicable to disturbances on the source side. In standalone PV systems, an abrupt drop in solar irradiance or a sudden change in temperature results in a deficit power ($P_{def}$) between the generation and demand. Since the proposed sizing methodology is fundamentally based on the energy balance required to bridge this deficit, it provides a universal design criterion regardless of whether the disturbance originates from the load or the PV source.

The results further show that the capacitance calculated using the proposed sizing equation consistently satisfies the required compensation duration across different load-step conditions, whereas smaller arbitrarily selected capacitances fail to sustain ride-through operations when the deficit power increases. This confirms that the proposed sizing method provides a quantitative design criterion for selecting an appropriate supercapacitor, without relying on empirical tuning or excessive safety margins.

From a practical design perspective, increasing the capacitance can improve the ride-through capability; however, excessive capacitance leads to increased system cost, volume, and implementation complexity. Therefore, determining the appropriate capacitance that satisfies the required compensation conditions without oversizing is essential for practical standalone PV systems. Unlike conventional empirical methods or trial-and-error approaches that often result in over-designed systems with unnecessary costs, the proposed deficit-power-based sizing approach enables designers to calculate the mathematically minimum required capacity. It is worth noting that the proposed methodology focuses strictly on a deterministic sizing approach to satisfy the minimum required capacitance under specified ride-through conditions, rather than a full multi-objective or globally optimal sizing scheme that accounts for multi-variable economic trade-offs. By directly relating the expected disturbances and allowable DC bus voltage deviation to the energy capacity, this study offers a more cost-effective and technically rigorous alternative to mainstream empirical coefficient-based sizing.

It should be noted that this study assumed a quasi-constant deficit power during the compensation interval. In practical systems, variations in the PV power and MPPT dynamics may introduce deviations from this assumption, which can slightly affect the compensation duration. Future work may extend the proposed method to adaptive sizing or hybrid energy-storage configurations that consider dynamic power variations and broader operating conditions.

5. Conclusions

This paper proposes a ride-through control strategy and a required capacity sizing method for a supercapacitor intended to provide instantaneous DC bus voltage support in standalone PV systems. A deficit-power-based analytical formulation was derived to determine the minimum required supercapacitor capacitance that satisfies a specified compensation duration under an allowable DC bus voltage deviation.

Simulation and experimental results demonstrated that the ride-through duration is determined by the relationship between the stored energy and deficit power, and that the capacitance calculated using the proposed sizing equation consistently satisfies the required compensation condition across various load-step scenarios. By contrast, arbitrarily selected smaller capacitances resulted in insufficient compensation duration and ride-through failure under larger load disturbances.

The proposed method provides quantitative and practical design guidelines for selecting an appropriate supercapacitor while avoiding unnecessary oversizing. This approach can be applied to standalone PV systems and other power electronic systems that require fast transient energy compensation. Future work will consider dynamic deficit power conditions and integration with hybrid energy storage systems to enhance the operational flexibility.