Fast Fault Identification Scheme for MMC-HVDC Grids Based on a Novel Current-Limiting DC Circuit Breaker

Abstract

The development of high-performance DC circuit breakers (DCCBs) and rapid fault detection schemes is a crucial and challenging part of advancing Modular Multilevel Converter (MMC) HVDC grids. This paper introduces a new current-limiting DCCB that uses the differential discharge times of shunt capacitors to generate artificial current zero-crossings, thus facilitating arc quenching. This mechanism significantly reduces the effect of fault currents on the MMC. The shunt capacitors and arresters in the proposed breaker also offer voltage support during faults, effectively stopping transient traveling waves from spreading to nearby non-fault lines. This feature creates an effective line protection boundary in multi-terminal HVDC systems. Additionally, a fast fault detection scheme with primary and backup protection is proposed. A four-terminal MMC-HVDC (±500 kV) simulation model is built in PSCAD/EMTDC to validate the scheme. The results demonstrate the excellent fault detection performance of the proposed method. The voltage and current behavior during the interruption process of the new DCCB is also analyzed and compared with that of a hybrid DCCB.

1. Introduction

Voltage source converter-based high-voltage direct current (VSC-HVDC) transmission technology is widely regarded as a key solution for integrating large-scale renewable energy sources, such as wind and photovoltaic power [1]. Its advantages—including no commutation failure risk, flexible power control, and the capability to form multi-terminal DC grids—also make it a significant direction for future power system development [2,3]. However, VSC-HVDC systems, which rely on fully controllable power electronic devices, exhibit low overcurrent tolerance and inherent inertia. As a result, DC short-circuit currents can rise extremely rapidly under fault conditions [4]. Moreover, unlike AC faults, DC fault currents lack natural zero-crossing points, which complicates fault interruption [5]. These technical constraints underscore the need for protection systems that can rapidly detect and isolate DC line faults. Therefore, the development of high-performance DC circuit breakers (DCCBs), along with fast and reliable fault identification methods, constitutes a critical research challenge for the further deployment of Modular Multilevel Converter (MMC) HVDC grids [6].

DCCBs are typically classified into three main categories [7]: mechanical oscillatory type (which employs current zero-crossing via oscillation), solid-state type, and hybrid type. The mechanical oscillatory DCCBs can be further divided into passive self-oscillating and active pre-charged oscillating subcategories. The former takes a relatively long time to reach a current zero-crossing, making it challenging to meet the requirements for rapid interruption [8]. Solid-state DCCBs can interrupt within milliseconds but have high on-state losses. Around 2011, ABB successfully developed a hybrid DCCB with a 9 kA interrupting capacity [9]. By the end of 2016, China’s independently developed ±200 kV high-voltage DCCB was put into operation in the Zhoushan five-terminal project, capable of interrupting a 15 kA short-circuit current within 3 milliseconds. In 2017, NR Electric developed the world’s first 500 kV hybrid DCCB with a 25 kA interrupting capacity within 3 ms [10]. Although notable progress has been achieved in DCCB technology, current solutions still face limitations and are very costly, making widespread adoption a long-term goal [11].

To address the high cost of DCCBs, references [12,13,14,15,16] have proposed multi-line DC circuit breakers. This design shares certain branches of a hybrid DCCB among multiple lines, thereby reducing the overall cost of multi-line disconnection in HVDC grids. Reference [16] employs a multiport DC breaker with integrated energy dissipation, thereby addressing the high-cost challenge. Meanwhile, to alleviate the demanding requirement for ultra-fast protection speeds, references [17,18,19,20,21] have introduced DCCBs with inherent current-limiting capabilities. Reference [21] uses a bidirectional current-limited branch in the hybrid DCCB topology to achieve current limitation.

Given the rapid development of DC fault currents in MMC-HVDC grids, DCCBs must cooperate with ultra-fast single-ended protection schemes to prevent the fault current from exceeding the DCCB’s rated breaking capacity. In practice, current-limiting reactors (CLRs) are typically installed at both ends of DC lines to suppress the rapid rise of short-circuit currents [22]. These CLRs consequently form a protective boundary, aiding in fault identification for different lines within a meshed network [23,24]. Building on this, reference [25] proposed fast fault-detection schemes that leverage the way CLRs smooth fault-induced traveling waves and attenuate high-frequency components. However, the vast majority of conventional DCCBs are based on parallel branches across the DC line for interruption [26]. These branches have negligible influence on fault characteristics prior to the DCCB’s operation, making it challenging to study the impact of the DCCB itself on protection schemes or to design protection schemes that leverage DCCB characteristics.

This paper proposes a fast fault identification scheme based on a novel current-limiting DCCB with a line-to-ground parallel capacitor branch. The core innovation lies in how this DCCB’s topology inherently shapes system characteristics. The shunt capacitors and arresters not only provide voltage support and create artificial current zero-crossings for arc quenching but also actively suppress the propagation of transient traveling waves to healthy lines. This mechanism naturally establishes a clear protection boundary in multi-terminal grids. Capitalizing on this distinct feature, we develop a tailored fast fault detection scheme that includes both primary and backup protection. The scheme’s effectiveness is validated through a ±500 kV four-terminal MMC-HVDC model built in PSCAD/EMTDC, with its performance compared against a conventional hybrid DCCB.

The paper is structured as follows: Section 1 details the principle of the novel DCCB. Section 2 analyzes its impact on fault characteristics. Section 3 presents the proposed protection scheme. Section 4 provides simulation verification, and Section 5 concludes the work.

2. Principle of Novel Current-Limiting DCCB

2.1. Topology of the Current-Limiting DCCB

This study proposes a novel current-limiting DCCB structure. While the fundamental principle of utilizing sequential capacitor discharge to induce artificial current zero-crossing is based on the concept introduced in Ref. [27], this paper optimizes the topology for HVDC application. The proposed topology (Figure 1) integrates dedicated pre-charging branches (R₁, S_R1) and, crucially, energy absorption branches (R_C1, S_C1). The proposed current-limiting DCCB primarily consists of three parts: Parallel Branch 1 (PB1), Parallel Branch 2 (PB2), and a Fast Disconnector (FD). The FD consists of an ultra-fast vacuum mechanical switch driven by an electromagnetic repulsion mechanism. PB1 and PB2 share an identical structure, each comprising charging resistors (R₁, R₂) and charging switches (S_R1, S_R2), capacitor banks (C₁, C₂), conventional mechanical switches (S₁, S₂) and branch isolation switches (S₁₁, S₂₂), diode valve groups (D₁, D₂), thyristor valve groups (T₁, T₂), capacitor discharge resistors (R_C1, R_C2) and discharge switches (S_C1, S_C2), metal oxide varistors (MOVs) for capacitor protection (MOV₁₂, MOV₂₂), and MOVs for thyristor protection (MOV₁₁, MOV₂₁). PB1 and PB2 serve as the core components of the current-limiting DCCB and are connected in parallel across the FD branch. The FD consists of an ultra-fast vacuum mechanical switch and an inductor L₀, which prevents excessively rapid discharge between the capacitor banks. Inductors L₁ and L₂ in Figure 1 represent the equivalent current-limiting reactors on the input and output sides of the DCCB, respectively, which serve to suppress the rapid rise in the DC short-circuit current.

2.2. Operating Principle of the Current-Limiting DCCB

During the pre-charging startup phase, switches S₁, S₂, S_R1, and S_R2 are closed. The DC line charges capacitor banks C₁ and C₂ through large resistors R₁ and R₂, respectively. The charging process forms an LCR second-order charging circuit, with the charging rate controlled by R₁ and R₂, and the time constant τ₁ = 1/(R₁C₁). After pre-charging is completed, the voltage difference across S₁ and S₂ is slight, and the required closing speed is not critical; hence, conventional mechanical switches suffice for S₁ and S₂. During steady-state operation, the line intermittently charges C₁ and C₂ through diodes D₁ and D₂ to maintain their voltage.

When a fault occurs on the DC line, the entire sequence of events is shown in Figure 2. At time t₀, a ground fault happens at location f on the line. At time t₁, the fault-induced traveling wave reaches the protection device, triggering it to start fault identification. To keep costs down, the rated voltage of thyristors T₁ and T₂ might not be very high. During the fault detection period (t₁–t₂), the fault traveling wave can cause MOV₂₁ and MOV₁₁ to break down. After the breakdown, C₁ and C₂ discharge slowly into the fault line through MOV₂₁ and MOV₁₁, respectively, helping to clamp the line voltage.

At time t₂, after the protection device detects the specific faulty line, thyristor switch T₁ is triggered. As shown in Figure 3a, C_1I quickly discharges toward the fault point through T₁, K, L₀, L₂, and the fault line (i_C1), forming a secondary LCR discharge circuit. This discharge sustains a gradually decreasing line voltage, alleviating overcurrent stress on the converter. Meanwhile, the ultra-fast mechanical switch K begins to open, accompanied by arcing.

Several milliseconds later, at time t₃, K has opened enough to create a sufficient physical gap (Generally 2–3 ms), and thyristor switch T₂ is triggered. As shown in Figure 3b, since the voltage on C₂ is now higher than that on C₁, C₂ discharges into C₁ through T₂, L₀, and D₁ (i_CtoC), causing the current through K to drop to zero, which quenches the arc and achieves DC interruption. C₂ also discharges to the fault point through L₂ (i_Cf). The inductor L₀, which has a small inductance, mainly acts to prevent excessively rapid discharges between the capacitors (C₂ and C₁) due to their direct parallel connection.

As shown in Figure 3c, after the FD section isolates the faulty line, the power supply charges C₁ through D₁ until it is fully charged (i_C1). The active component C₂ in PB₂ continues to discharge through T₂ (or D₂), L₂, and the DC line, forming a second-order LCR oscillatory circuit (i_C2).

As shown in Figure 3d, when the current oscillates to zero, T₂ turns off. Capacitor C₂ is then charged via D₂ (i_C2), and any remaining energy is gradually dissipated through MOV₂₁ and resistors R₂ and R_C2 (i_CS2). Since active components stay in the isolated faulty line section, the nature of the fault (temporary or permanent) can be determined by analyzing the properties of the oscillating current.

2.3. Parameter Constraints and Stability Analysis of Sequential Discharge

To ensure the reliability of the artificial current zero-crossing, the selection of capacitance parameters (C₁, C₂) and the limiting inductor (L₀) must satisfy specific energy and time constraints.

(1)

Energy Constraint for Zero-Crossing Creation

The core principle of the proposed DCCB involves injecting a reverse current i_inj from C₂ to C₁ to cancel out the fault current i_fault flowing through the mechanical switch K. When thyristor T₂ is triggered at time t₃, a localized L-C oscillation circuit is formed by C₂, C₁, and L₀. The equivalent capacitance of this loop is C_eq = C₁C₂/(C₁ + C₂). The peak magnitude of the injected current, I_{inj_peak}, is determined by the voltage difference between the two capacitor banks:

$$I_{inj\_peak}\approx {\displaystyle \frac{U_{C2}(t_3)-U_{C1}(t_3)}{\sqrt{L_0/C_{eq}}}}$$

(1)

where U_C2(t₃) remains near the rated voltage (as it is isolated before t₃), while U_C1(t₃) has dropped significantly due to its prior discharge into the fault line between t₂ and t₃. To guarantee a successful zero-crossing, the injected current must exceed the fault current with a safety margin k_safe (typically 1.2–1.5):

$$I_{inj\_peak}\ge k_{safe}\cdot i_{fault}(t_3)$$

(2)

This inequality represents the energy constraint. It implies that for a given fault level and inductor L₀, the capacitors must store sufficient energy to generate the required counter-current. The sequential operation naturally enhances stability because the voltage drop on C₁ maximizes the potential difference ΔU = U_C2 − U_C1, thereby allowing smaller capacitance values to interrupt larger fault currents compared to non-sequential topologies.

(2)

Time Constraint for Arc Extinction

The timing of the zero-crossing is critical for the dielectric recovery of the mechanical switch K. The discharge process creates a sinusoidal current pulse with a half-period T_osc:

$$T_{osc}=\pi \sqrt{L_0{C}_{eq}}$$

(3)

The time constraint imposes two requirements:

Delay Coordination: The zero-crossing must occur only after the mechanical switch has achieved a sufficient contact gap (typically 2–3 ms) to withstand the transient recovery voltage.

Current Rate of Change (di/dt): The value of L₀ and C_eq determines the di/dt near the zero-crossing. If C_eq is too small, the pulse width is too narrow, leading to a high di/dt that may cause arc reignition. Conversely, if C_eq is too large, the cost increases unnecessarily.

In this study, C₁ and C₂ are selected as 150 μF and L₀ is tuned to ensure that the injected current pulse creates a stable zero-crossing window of approximately hundreds of microseconds, providing sufficient time for the vacuum switch to de-ionize.

3. Impact of DCCBs on the Fault Detection Scheme

3.1. Impact of Conventional Series Type DCCBs

Hybrid DCCBs are typically used in real systems [9,10,11], mainly composed of a main branch, a transfer branch, and an energy absorption branch, as shown in Figure 4a. After a fault is detected by the protection device, the load commutation switch (LCS) in the transfer branch and the ultra-fast disconnector (UD) operate, diverting the current into the main breaker within the main branch. After a few milliseconds (typically 2–3 ms), once the UD in the main branch has opened sufficiently to create a gap, the main breaker operates, transferring the fault current to the parallel energy absorption branch (MOV) for dissipation.

Figure 4b illustrates the topology of a mechanical DCCB used in another multi-terminal VSC-HVDC real project [7,8]. Here, the DC source (U₀) pre-charges the capacitor (C) through the resistor (R) and the switch (S₂). After a fault, the vacuum circuit breaker (VCB) begins to arc during its opening process. Then, switch (S₁) is closed, allowing the inductor (L) and capacitor (C) to generate a resonant current in the circuit, forcing the current through the VCB to become zero.

3.2. Impact of the Proposed Current-Limiting Types DCCB

Unlike the conventional oscillatory DCCB where the LC branch is connected across the break and remains inactive before tripping, the proposed DCCB employs a line-to-ground shunt topology. This configuration allows the capacitors to actively shape the fault characteristics immediately upon the arrival of the traveling wave, acting as a protection boundary. Before the fault is identified, the proposed types DCCB can be equivalently represented as Protection Boundary 1 in Figure 5 (ignoring the large pre-charging resistors and diodes), where C represents the equivalent capacitance. In VSC-HVDC grids, the MMC must avoid locking during the protection process. Thus, the MMC can be modeled as a capacitor with an initial voltage discharging through a resistor and an inductor [22]. In Figure 5a, C_eq, R_eq, and L_eq represent the equivalent capacitance, resistance, and inductance of the MMC, respectively.

As shown in Figure 5, after a monopolar ground fault, the fault resistance R_f is located at position f on the DC line. The transmission line is modeled as a distributed-parameter system. Using the Laplace transform, the phase-domain fault equivalent circuit shown in Figure 5b can be constructed, where the DC transmission line is modeled as a Thevenin equivalent. If the length of the left section of the fault line is d, the Thevenin model can be written as follows:

$$\left\{\begin{array}{l}{B}_t=2H(d)\cdot \mathsf{\Delta }{U}_f\\ B_f=2H(d)\cdot \mathsf{\Delta }{U}_t\end{array}\right.$$

(4)

where ΔU_t and ΔU_f are the fault voltage components at the line port and fault point, respectively, and B_t and B_f are the reverse and forward traveling waves, respectively. The transfer function H(d) needs to consider the delay, attenuation, and distortion of fault traveling waves propagating along the transmission line, which can be expressed as follows:

$$H(d)={\displaystyle \frac{1-k_{a}d}{1+t_{a}d\cdot s}}{e}^{-d\cdot s/v}$$

(5)

where H(d) consists of two parts, the numerator part is the equivalent propagation delay, and the denominator part simulates the attenuation and distortion of traveling waves through a first-order inertial element [25]. When a fault occurs in the circuit, the fault additional state is t = 0. The fault power supply −u_N/s is applied at the fault point, and the fault resistance is R_f. Before the fault traveling wave arrives, B_f = 0, so the voltage at the fault point is solved as

$$\mathsf{\Delta }{U}_L=2H(d)\mathsf{\Delta }{U}_f({\displaystyle \frac{Z_{con}+s{L}_2}{Z_c+Z_{con}+s{L}_2}})$$

(6)

where Z_c is the surge impedance of the line, u_N is the rated line voltage, and ε(t) is the unit step function. The voltage ΔU_f will propagate along the DC line toward the line terminal. Upon encountering the series inductor L₂, the wave will undergo reflection and refraction due to the impedance discontinuity.

$$\mathsf{\Delta }{U}_L=2H(d)\mathsf{\Delta }{U}_f({\displaystyle \frac{Z_{con}+s{L}_2}{Z_c+Z_{con}+s{L}_2}})$$

(7)

where Z_con is the equivalent impedance on the left side of L₂. Transform the fault voltage traveling wave ΔU_L from the phase domain to the time domain, and ignore the attenuation distortion effect of H(d). The resulting change in voltage, Δu_L, across the inductor can be expressed as

$$\mathsf{\Delta }{u}_L={\displaystyle \frac{-2Z_c{u}_N\cdot \epsilon (t-\tau )}{2R_f+Z_c}}\cdot ({\displaystyle \frac{Z_{con}}{Z_c+Z_{con}}}+{\displaystyle \frac{Z_c}{Z_c+Z_{con}}}{e}^{-(t-\tau )/T})$$

(8)

where traveling wave propagation delay τ = d/v, v is the traveling wave velocity. When the fault-induced traveling wave reaches the terminal, it begins to decay from an initial amplitude of approximately twice the fault voltage. The decay time constant of the voltage traveling wave is given by T = L₂/(Z_c + Z_con). Meanwhile, at point u_c in Figure 5a, the voltage is clamped by the equivalent capacitance C and the conducting MOV group. After the traveling wave arrives at the terminal, Δu_c will be clamped to

$$-u_{mov}\le \mathsf{\Delta }{u}_c\le 0$$

(9)

where u_n is the rated voltage of the capacitor (i.e., the rated line voltage), and u_mov is the breakdown voltage of the MOV. Applying voltage division and neglecting the equivalent resistance R_eq of the MMC, the voltage on the DC bus can be approximated as

$${\displaystyle \frac{-u_{mov}\cdot L_{eq}}{L_{eq}+L_1}}\le \mathsf{\Delta }{u}_b\le 0$$

(10)

From the above derivation, it can be observed that after the fault-induced traveling wave passes through Protection Boundary 1, the magnitude of the voltage change on the DC bus, |Δu_b|, is less than u_mov. Similarly, the voltage change Δu_s on the non-faulty line connected to the same DC bus, after passing through Protection Boundary 2, must also satisfy Δu_s < u_mov.

4. The Proposed Fast Fault Identification Scheme

The overall flowchart of the proposed protection scheme is depicted in Figure 6. It comprises both main and backup protection. The main protection utilizes single-ended measurements to enable ultra-fast tripping of the faulty line. The backup protection, in contrast, employs directional information from both line ends to ensure reliable fault area identification.

4.1. Primary Protection

As derived in the previous section, due to the presence of the protection boundary, the magnitude of the voltage change on the faulty line will exceed u_mov, while that on the non-faulty line will remain below u_mov. Based on this characteristic, this paper proposes the following fast fault identification criterion:

$$\left\{\begin{array}{c}\left|\mathsf{\Delta }{u}_L(k)\right|>u_{set}\\ \mathsf{\Delta }{u}_L(k)={\displaystyle \sum _{i=1}^3\left(\mathsf{\Delta }{u}_L(k)-\mathsf{\Delta }{u}_L(k-i)\right)/3}\end{array}\right.$$

(11)

where ∆u_L(k) denotes the average rate of change in the measured voltage (ARCMV) on the line side at the k-th sampling point, and u_set represents the protection setting threshold, which should be greater than u_mov ≈ 90 kV. According to Equation (8), the minimum theoretical voltage drop for a 500 Ω fault is 285 kV. In this study, it is set to 1.3 times u_mov. This provides a wide reliability margin against external clamping effects while maintaining high sensitivity for high-resistance faults.

Because of the coupling between the two poles in a bipolar DC transmission line built on the same tower, a significant interference may be induced on the sound pole when a single-pole ground fault occurs on the other pole, requiring further discrimination. According to Ref. [22], a single-pole fault produces both α-mode and zero-mode transient components at the fault point, with the α-mode component propagating faster than the zero-mode component. For the non-faulty pole, when the α-mode transient arrives at the terminal, the fault voltage initially decreases. Then, with the arrival of the zero-mode transient, the fault voltage rises again, as shown in Figure 7.

Figure 7 shows the voltage variations measured by R₁₂ after a positive-pole ground fault F₁ occurs 100 km from the Beijing station.

The area enclosed between the rated line voltage and the measured voltage waveform is illustrated in Figure 7. For the faulty pole (positive pole), S_p is a significantly large positive value. In contrast, for the non-faulty pole (negative pole), the area S_N1 is positive, while S_N2 is negative, resulting in a relatively small net area. Based on this characteristic, the proposed faulted pole identification criterion in this paper is as follows:

$$S(k)={\displaystyle \sum _{i=0}^{N-1}\left(U_N-u(k-i)\right)>S_{set}}$$

(12)

where u is the measured pole voltage, U_N is the rate voltage, and k is the current sampling instant. The number of window data points, N, is critical for distinguishing the faulty pole. S_set is empirically determined from simulations to exceed the maximum mutual-coupling interference induced on the healthy pole. As established in wave propagation theory, the line-mode component travels close to the speed of light, while the zero-mode component travels significantly slower due to ground impedance. When a single-pole-to-ground fault occurs, the faulty pole voltage drops immediately upon the arrival of the line-mode wave. In contrast, the healthy pole voltage initially drops due to mutual coupling but recovers rapidly once the slower zero-mode wave arrives (as shown in Figure 7). To reliably capture this characteristic “dip-and-recover” behavior on the healthy pole, the window data points N must cover the time delay between the line-mode and zero-mode arrivals. In our simulation, we selected a window of 0.3 ms (N = 6), which provides a robust margin for discrimination while ensuring ultra-fast operation.

4.2. Backup Protection

To enhance the reliability of the protection system by identifying faults with extremely high fault resistance and addressing potential failure of the primary protection, this paper proposes a communication-based backup pilot protection scheme. Leveraging the fault current-limiting reactor’s (CLR) ability to smooth fault-induced traveling waves. The proposed method uses the ratio of the ARCMV on the line side to that on the bus side to determine fault direction.

The direction criterion is defined as follows:

$$R(k)=\left\{\begin{array}{c}1 , \left|\mathsf{\Delta }{u}_L(k)/\mathsf{\Delta }{u}_b(k)\right|>K_{set}\\ -1, otherwise\end{array}\right.$$

(13)

where Δu_L(k) and Δu_b(k) denote the ARCMV on the line side and on the DC bus at the k-th sampling point, where the reliability coefficient K_set is set to 1.2 (Providing a 20% safety margin). When a forward fault occurs (on the line), the ARCMV on the line side exceeds that on the bus side, fault directional signal R(k) = 1 is sent to the opposite terminal of the line. Conversely, for a backward fault (on the bus or adjacent lines), the voltage change propagates through the bus to the line side, but is dampened by the CLR, resulting in a ratio less than K_set. During the maintenance period of the fault directional signal (typically a few milliseconds, including signal and transmission delays), if the directional signals at both ends are positive, it indicates an internal fault.

Backup protection is generally used to identify high-resistance faults. When a high-resistance fault occurs, using the amplitude in Equation (12) to distinguish the fault becomes inefficient and may cause misoperation. To improve the sensitivity of the fault pole criterion, we distinguish the fault line by comparing the relative magnitude of S(k) of the positive (S_P(k)) and negative poles (S_N(k)). The faulty pole is then identified using the following criteria:

$$D(k)=\left\{\begin{array}{c}1, \left|S_P(k)/S_N(k)\right|>k_p\\ -1, \left|S_P(k)/S_N(k)\right|<1/k_p\\ 0, otherwise\end{array}\right.$$

(14)

where k_p should be slightly greater than 1; in this study, it is set to 1.2 (Providing a 20% safety margin). A calculated result of D(k) = 1 indicates a positive-pole-grounding (P-G) fault, D(k) = −1 indicates a negative-pole-grounding (N-G) fault, and D(k) = 0 represents a bipolar pole-to-pole (P-P) fault.

5. Simulation Results

5.1. Introduction to the Simulation System

The 4-terminal MMC-HVDC grid simulation model is built in PSCAD/EMTDC, utilizing parameters derived from a practical project in China. The topology of the MMC-HVDC grid is depicted in Figure 8, where half-bridge submodule (SM) MMCs and high-capacity hybrid DCCB are adopted. To accurately represent the dynamic behavior of the converters while maintaining computational efficiency for system-level protection studies, the Detailed Equivalent Model (DEM) available in PSCAD/EMTDC is utilized for all MMC stations, and the Nearest Level Control (NLC) modulation strategy is adopted. The main grid topology is a symmetrical bipolar structure, with overhead transmission lines used [22]. The converter stations operate under a hierarchical control structure based on dual-loop vector control in the d-q synchronous reference frame. The entire system forms a ring shape, with stations connected to Station I, II, III, and IV. Among these, the station I acts as the slack bus for the DC grid, employing constant DC voltage control, while the other stations operate with constant active power control [22].

Since the DC grid has low inertia, fault CLRs are installed in series at both ends of each line to prevent a rapid rise in short-circuit currents. In Figure 8, the CLRs at both ends of Line 23 are 300 mH, while those on the other lines are 200 mH. Faults F1–F4 occur in different zones, and R(1–4)(1–4) indicate the signal measurement points of the line protection devices.

Each converter station uses dual-loop vector control, with simulation parameters listed in

Table 1. Main parameters of the converter stations in the simulation system.

	Stations	I	II	III	IV
Parameters
SM/mF		10	10	15	15
Number of SM		228	228	312	312
Arm reactor/mH		150	150	100	100
Lt/%		15	15	15	15
Ratio (kV/kV)		520/265	235/265	235/265	520/265
SCR/kA		16.3	18.2	18.7	23.8
Capacity/MW		3000	3000	1600	1600

[22]. The bipolar overhead DC lines are composed of type 4 × JL/G2A-720/50, which are modeled with frequency-dependent properties in the simulation. The lengths of the lines are as shown in Figure 8, and the transmission line tower structure is depicted in Figure 9.

5.2. Operating Characteristics of the Novel DCCB

5.2.1. Voltage and Current Behavior During the Interruption Process

This section examines the interruption process of the DCCB at location R21 following a positive-pole-to-ground fault that occurs 50 km from Station I on Line 12. The interruption sequence is illustrated in Figure 10. In the simulation, C₁ and C₂ are set to 150 μF, and the breakdown voltage of the MOV₁₁ and MOV₂₁ is approximately 90 kV. The thyristor T₂ is triggered 3 ms after the mechanical switch K operates to quench the arc.

The overall interruption process is consistent with the expected DCCB operating sequence. A fault occurs at time t₀, and the resulting traveling wave reaches the protection location at time t₁. At this point, both MOV₁₁ and MOV₂₁ break down to limit the voltage across thyristors T₁ and T₂ to the MOV breakdown voltage, as shown in Figure 10b. Meanwhile, the voltage u_C is clamped to the value given by Equation (9), and the DC bus voltage u_b is clamped to the value specified by Equation (10), as depicted in Figure 10c.

At time t₂, after fault identification is completed, thyristor T₁ is triggered. Capacitor C₁ discharges through T₁, causing its voltage to decrease, as shown in Figure 10d. The voltage across the still-inactive thyristor T₂ increases gradually, as illustrated in Figure 10b. At time t₃, thyristor T₂ is conducting, and the current i_dc through the mechanical switch K is forced to zero artificially, thereby extinguishing the arc and achieving DC interruption.

In Figure 10a, i_dc1 represents the short-circuit current contributed by the converter. Throughout the interruption process, the voltage clamping effect limits the magnitude of this current, demonstrating the current-limiting capability of the proposed DCCB. This effectively prevents overcurrent damage to the converter valves, ensuring their safety. i_dc2 denotes the current flowing from the DCCB toward the fault. After K opens, this current oscillates in a second-order circuit formed by capacitor C₂, inductor L₂, and the DC line. MOV₂₁ ultimately absorbs the energy after T₂ is turned off. During the oscillation, the voltage across C₂ may become negative and reach substantial magnitudes, with any overvoltage being absorbed by MOV₂₂. Meanwhile, after the faulted section is isolated, capacitor C₁ is charged back to its rated voltage, u_n, through a diode, as shown in Figure 10d.

Similar interruption behavior is observed for different fault types and locations; therefore, detailed descriptions are omitted here.

5.2.2. Comparison with Hybrid DCCBs

The Hybrid DCCB is selected as the benchmark because it is the adopted solution in the reference Zhangbei ±500 kV project and represents the current industrial state-of-the-art for high-voltage applications. This section compares the operational characteristics of the proposed current-limiting DCCB and a hybrid DCCB during a positive-pole-to-ground fault near station I at location R21. The results are shown in Figure 11. Figure 11a,b illustrate the performance of the proposed current-limiting DCCB, while Figure 11c,d depict that of the hybrid DCCB.

In Figure 11c, i_main represents the current through the main branch of the hybrid DCCB, i_b denotes the current in the transfer branch, and i_dc indicates the short-circuit current contributed by the converter station during the fault. Compared to i_dc1 in Figure 11a, it is evident that although the hybrid DCCB operates more quickly, the converter must withstand a significantly larger short-circuit current than with the proposed DCCB.

Figure 11b,d show the current variations in the upper half-bridge arm of the Station I converter. A comparison reveals that when the proposed current-limiting DCCB is employed, the current change in the converter arms during the entire interruption process is minimal. This further demonstrates the novel current-limiting DCCB’s ability to enhance converter protection and reduce the required short-term overcurrent capability of the converter.

5.3. Fault Identification Results

This section verifies the performance of the proposed voltage-based protection scheme. The following analysis focuses on the voltage transient characteristics utilized by the protection criteria. To validate the proposed scheme, the high-fidelity voltage waveforms generated in PSCAD/EMTDC: 5.0.0 were exported to Matlab: 24.2.0.3070828 (R2024b) for digital signal processing. To emulate the behavior of a physical protection device and ensure data consistency, Discretization, Noise Injection, and Sliding Window Processing are applied.

5.3.1. Single-Pole-to-Ground Faults

A simulation was conducted for a negative-pole-to-ground fault with a 300 Ω fault resistance at location F₁, 15 km from Station I on line 12 in Figure 1. The resulting voltage variations at different locations are shown in Figure 12a. Here, R12-P denotes the positive-pole voltage at protection location R12, R12-N represents the negative-pole voltage, and similarly for R21-P, R14-P, and so on. Bus1-P indicates the positive-pole voltage on the DC bus at Converter Station 1 (Beijing Station).

As observed in Figure 12a, when the fault-induced traveling wave reaches protection location R12, the voltage on the faulty pole at the Beijing Station DC bus drops from u_n to u_b. After approximately 0.5 ms, fault identification is completed, and with the activation of the thyristor switch, the voltage recovers to u_n, consistent with the derivation in Equation (4). Furthermore, by comparing the voltage changes at in-zone protection locations (R12, R21) and the nearest out-of-zone protection location (R14), it is evident that the voltage variation remains significant within the zone even with a 300 Ω fault resistance, while the out-of-zone voltage change is minimal due to attenuation by the line protection boundary.

Similarly, Figure 12b shows the voltage variations for a direct positive-pole-to-ground fault at location F₁, 100 km from the Beijing converter station. As illustrated, the low fault resistance results in larger voltage changes at in-zone protection locations, and the non-faulty pole experiences considerable interference (which can be eliminated using the faulty pole identification criterion). Nevertheless, due to the presence of the line protection boundary, the voltage variations on the Beijing Station DC bus and at location R14 remain small and nearly identical to those in Figure 12a.

5.3.2. Bipolar Pole-to-Pole Faults

Similarly to the analysis of the single-pole-to-ground fault, Figure 13a illustrates the voltage variations at various locations following a bipolar short-circuit fault at location F₁, which is 100 km from the Beijing converter station. As observed, the voltage changes on the positive and negative poles are identical. The DC bus voltage at Station I converter behaves similarly to the single-pole fault case, dropping to u_b after the arrival of the fault-induced traveling wave. It recovers to u_n after fault identification and subsequent thyristor operation. In contrast, the magnitude and rate of change in the voltage at the nearest out-of-zone protection location, R23, remain very small.

Similarly, Figure 13b illustrates the voltage variations for a bipolar short-circuit fault at location F₁, which is 206.6 km from the Beijing converter station (the end of the line). As shown, the voltage behavior at the DC bus of Station I and location R23 is nearly identical to that in Figure 13a. This further confirms that the proposed line protection boundary effectively blocks the propagation of fault-induced traveling waves to adjacent lines.

5.3.3. Fault Identification Results Under Various Faults

This section assesses the performance of the proposed primary protection scheme for faults occurring at three different locations along the line: 15 km from Station I, 100 km from Station II, and at the line’s end. For each location, three fault types were simulated: positive-pole-to-ground fault with 100 Ω fault resistance, negative-pole-to-ground fault with 100 Ω fault resistance, and bipolar short-circuit fault. The protection results are summarized in Figure 14.

In Figure 14, Δu₁₂-P and Δu₁₂-N represent the protection values of the fault identification criterion for the positive and negative poles, respectively, calculated at the in-zone location R12. Δu_o-max denotes the maximum value of the fault identification criterion among all out-of-zone locations and different poles. S₁₂-P and S₁₂-N indicate the protection values of the faulty pole identification criterion for the positive and negative poles, respectively, also calculated at R12 (all values are normalized).

As observed in Figure 14, for positive-pole-to-ground faults at different locations, both Δu₁₂-P and Δu₁₂-N exceed the setting threshold. Meanwhile, S₁₂-P is greater than the threshold while S₁₂-N is lower, correctly identifying a positive-pole fault. Similarly, for negative-pole-to-ground faults, the results are analogous: S₁₂-P is below the threshold and S₁₂-N exceeds it, enabling accurate detection of a negative-pole fault. In the case of bipolar short-circuit faults, all protection values at R12 surpass the threshold, confirming a bipolar fault.

For all fault types and locations, Δu_o-max remains significantly below the setting threshold and is largely unaffected, ensuring reliable non-operation for out-of-zone faults. Furthermore, during busbar faults (F₂), AC-side three-phase faults (F₄), power flow variations, and transient processes resulting from DCCB operations, the calculated protection values at all locations remain well below the setting threshold, thereby preventing maloperation.

5.3.4. Influence of Fault Resistances and Noise Environment

This section examines the impact of fault resistance on the performance of the fault identification criterion. Simulations were conducted for positive-pole-to-ground faults with varying fault resistances (0–500 Ω) at a location 50 km from Station II on line 12. The corresponding protection results are shown in Figure 15.

As observed in Figure 15, the values of Δu_o-max at out-of-zone locations remain largely unaffected by the increase in fault resistance and stay well below the setting threshold throughout the variation. In contrast, the in-zone values Δu₁₂-P and Δu₂₁-P decrease gradually as the fault resistance increases. Nevertheless, even at 500 Ω, the distinction between in-zone and out-of-zone values remains clear, allowing the protection device to identify the fault correctly.

To evaluate protection reliability in noisy environments, we added Gaussian white noise at different signal-to-noise ratios (SNRs) to the measured signals, and protection remained reliable. The results at an SNR of 35 dB are in Figure 15. Compared to noise-free conditions, for faults within the protection zone, the protection value is less affected because the voltage changes are large. Outside the protected zone, the protection value increases with noise but stays below the threshold. The results show that even in high noise, the protection boundary stays clear and retains reliable operation.

5.3.5. Verification of the Backup Protection Scheme

A simulation was conducted for a positive-pole-to-ground fault with a significant fault resistance of 800 Ω at a location 50 km from Station II on line L12. The results obtained using the backup protection scheme are shown in Figure 16.

As observed in Figure 16, the values of |du_L/du_b| at the in-zone locations, R12 and R21, significantly exceed the protection setting threshold, whereas at most one end of the out-of-zone locations exceeds the threshold. This enables the identification of a fault in the line 12 section and triggers the faulty pole discrimination procedure. The calculated |S_P/S_N| ratio is far greater than the protection setting value, confirming a positive-pole-to-ground fault.

The backup protection scheme ensures reliable backup operation in the event of primary protection failure. However, practical implementation must account for factors such as communication delays. This study focuses on validating the correctness of the principle; further detailed analysis is not expanded upon here.

The timing of the backup protection scheme is shown in Figure 17. After a fault occurs 50 km from R12. After a delay time t_d for traveling-wave transmission, R12 detects the fault first (R = 1). The action time of backup protection can be expressed as

$$t_{\Sigma }=t_d+t_f+t_c$$

(15)

where t_f is the total delay of signal processing, and t_c is the total communication delay.

Communication systems are typically fiber-optic, and transmission-theoretical delay and node delay must be considered. In an optimistic situation, the communication delay t_c is about 1.5–2 ms for a 200 km line. There is a similar process in the remote protection of R21. As shown in Figure 17, with the protection of R12 and R21, the overall action time is optimistically estimated to be less than 3 ms.

5.3.6. Comparison with Other Methods

This study compares the proposed scheme with various protection methods utilizing the CLR-based line boundary in terms of reliability, cost, complexity, and capability to detect high-impedance faults. The comparison results are summarized in

Table 2. Comparing with different Primary Protection methods.

Methods	Direction Protection	Detection Time	Signal Position	Fault Resistance Identification
Proposed	None	<1 ms	1	>500 Ω
Change rate of line-side voltage [28]	None	<1 ms	1	>100 Ω
Ratio of voltage on both sides of CLR [29]	Yes	<1 ms	2	200 Ω
High frequency signal ratio on both sides of CLR [30]	Yes	1 ms	2	>200 Ω

.

Reference [28] employed the change rate of line-side voltage (du/dt) to identify the fault, but it primarily relies on the steepness of the initial traveling wave header. Reference [29] used the ratio of voltage on both sides of CLR to distinguish the fault, but relying on the smoothing effect of CLR, if the CLR is small, the performance will decrease. Reference [30] utilized the high-frequency signal ratio on both sides of CLR to set up the direction protection. However, these high-frequency features are highly susceptible to the damping effect of fault resistance and the smoothing effect of CLRs. In contrast, the proposed scheme does not rely solely on the transient edge. Instead, it leverages the unique topology-dependent response of the current-limiting DCCB. The shunt capacitor and MOV branches actively clamp the bus voltage while allowing the line-side voltage to drop significantly. This creates a sustained and distinct voltage difference (Δu) determined by the circuit structure rather than just the transient frequency.

As shown, all methods meet the requirement for rapid fault detection in terms of identification time. However, the proposed scheme offers distinct advantages: it eliminates the need for directional criteria, relies solely on single-pole single-point voltage information, and exhibits lower complexity and higher reliability. Moreover, it demonstrates superior performance in identifying high-impedance faults compared to other methods.

These benefits primarily stem from the novel current-limiting DCCB, which establishes an effective line protection boundary. This boundary efficiently blocks the propagation of fault-induced traveling waves to non-faulted lines, thereby preventing maloperation and enhancing the overall robustness of the protection system.

6. Conclusions

This paper presents a novel current-limiting DCCB and a corresponding fast fault-identification scheme. The proposed DCCB utilizes the sequential discharge of shunt capacitors to create artificial current zero-crossings, enabling efficient arc interruption. A key feature of its unique topology is that the shunt capacitors and MOVs provide crucial voltage support during faults. This mechanism effectively suppresses the propagation of transient traveling waves to adjacent healthy lines, thereby establishing a reliable protection boundary in multi-terminal HVDC grids.

Leveraging this distinctive characteristic, a rapid fault identification scheme incorporating both primary and backup protection was developed based on the analysis of fault-induced voltage traveling waves. Simulation tests conducted on a realistic four-terminal MMC-HVDC system demonstrated the scheme’s effectiveness. The results confirm its ability to accurately and reliably identify various fault types, including high-resistance faults up to 800Ω, showcasing excellent protection performance.

Future work will extend this research in several directions:

(1) Research will be conducted on the coordination strategy between the proposed boundary-based scheme and other protection layers; (2) the long-term impact of component degradation, specifically the aging of MOVs and capacitors under repeated discharge stresses; and (3) the applicability of the proposed DCCB and detection algorithm in more complex, large-scale MTDC networks and extreme operating conditions.