A Si and SiC Hybrid Arms ANPC Converter Achieving Comprehensive Optimization of Power Quality, Efficiency, and Cost

Abstract

Wide bandgap (WBG) power semiconductors such as silicon carbide (SiC) can significantly improve the performance of multilevel converters. However, there are three challenges for large-scale application: high cost, limited power ratings, and reliability issues. In this paper, we propose a Si and SiC hybrid arms active neutral-point-clamped (ANPC) converter, using smaller current rating SiC devices compared to other Si devices in this topology. By employing the hybrid-frequency modulation scheme, the Si devices switch at fundamental frequency (FF) or low frequency (LF), while the SiC devices switch at high frequency (HF). The equivalent circuit of the proposed converter is derived to analyze the principle of LF current ripple compensation. The closed-loop cooperative current control strategy is proposed to realize unequal current sharing in two arms and complete LF current ripple compensation. The Si arm processes major power, while the SiC arm compensates the LF current ripple generated by the Si arm and processes minor power. The proposed topology and control strategy are validated by simulation and experimental results. Compared with the existing typical topologies, the comprehensive optimization of power quality, efficiency, and cost is realized.

1. Introduction

Multilevel converters have evolved over many years and are considered a preferred solution for electric energy conversion in high-power applications [1]. Recently, with the rapid development of emerging power conversion applications such as renewable energy generation [2], electric vehicles [3], more electric aircraft (MEA) [4], and medium-voltage motor drives [5], the efficiency, power quality, cost, and power density of multilevel converters have reached a higher level. Due to the inherent material limitations of silicon, the operating temperature and switching frequency of Si-based devices are approaching their theoretical boundaries. As a result, enhancing the performance of high-power multilevel converters based on silicon devices has grown increasingly impossible. WBG power semiconductors represented by SiC MOSFET feature high voltage withstanding capability, low on-state resistance, and high switching frequency [6], which can further improve the performance of multilevel converters. However, the large-scale application of SiC devices still faces three major bottlenecks: high cost, limited power ratings, and reliability issues. Firstly, a SiC MOSFET is four to eight times more expensive than a Si IGBT, particularly in the high current ratings [7]. Secondly, the maximum current rating of an individual SiC MOSFET die lags significantly behind that of a Si IGBT. Thirdly, compared with Si IGBTs, the ruggedness and reliability of SiC MOSFETs are still subjects of widespread concern, particularly due to unresolved issues such as gate oxide degradation [8], threshold voltage drift [9], and body diode reliability [10]. Therefore, the large-scale industrial application of SiC devices in high-power multilevel converters remains significantly constrained.

To overcome these challenges, researchers have introduced hybrid concepts that combine the strengths of both Si and SiC devices. One widely adopted example is the hybrid three-level (3L) ANPC converter, which offers a practical balance between efficiency and device cost in advanced grid-connected inverter and rectifier systems [11,12]. In high-power rectifier applications, hybrid unidirectional rectifiers using SiC MOSFETs and Si diodes in 3L and five-level (5L) topologies have been proposed to reduce system cost in [7,13]. Similarly, three five-level converters with hybrid Si and SiC legs were presented in [14,15,16]. The above designs employ hybrid-frequency modulation strategies where Si devices switch at fundamental or low frequency, and SiC devices operate at carrier frequency. Thus, these topologies have lower losses, improved harmonic performance, and reduced cost. However, the SiC devices in these topologies handle the full load power, which results in relatively high cost. Moreover, the topologies in [14,15,16] are just single-phase circuits, which cannot be applied to three-phase high-power scenarios. Therefore, how to configure a three-phase hybrid multilevel converter with lower cost and better performance is still a challenge.

Recently, a novel concept known as WBG fractional power processing (WFPP) has been introduced [17,18,19]. In these structures, the LF Si two-level converter carries most of the power, while the HF SiC two-level converter is in parallel to cancel the ripple current and process partial power. The equivalent switching frequency of these topologies is the same as that of the SiC devices, maintaining excellent HF performance. Meanwhile, only low current rating WBG devices are required. Based on these topology-specific studies, a WBG and Si hybrid half-bridge (HHB) structure has been proposed in [20], aimed at improving power quality without significantly increasing cost. The HHB configuration has already shown promising results in power factor correction (PFC) application [21]. Further, the efficiency optimization based on the switching frequency and power sharing control has been achieved in [22,23]. Therefore, the WFPP concept provides feasibility for cost reduction in existing hybrid multilevel topologies. However, the implementation of the WFPP concept in three-phase DC-AC hybrid multilevel converters remains unsolved.

In this paper, a three-phase Si and SiC hybrid arms ANPC converter is proposed. The concepts of hybrid-frequency modulation and WFPP are combined to achieve comprehensive optimization of cost, power quality, and efficiency. Compared to the all-SiC and the existing hybrid converters, the number and current rating of SiC devices are further reduced. Meanwhile, from the AC output perspective, the equivalent switching frequency and power quality of the converter are similar to those of an all-SiC solution. The corresponding closed-loop cooperative current control strategy is also proposed to achieve the current tracking and power sharing. The SiC devices process minor power, which are switched under lower current conditions. This significantly reduces the high-field stress events on the SiC gate oxide.

The rest of this paper is organized as follows. Section 2 presents the proposed hybrid arms ANPC topology and operation principle of current ripple compensation. Section 3 discusses the closed-loop cooperative current control strategy. In Section 4, simulation results are presented. In Section 5, experimental results are presented to validate the proposed converter. In Section 6, performance comparison with existing topologies is presented. Finally, Section 7 concludes this paper.

2. Proposed Hybrid Arms ANPC Converter

2.1. Topology and Modulation Scheme

The per-phase configuration of the proposed converter is illustrated in Figure 1a. Each phase comprises a Si-based 3L-ANPC arm paired with a SiC-based half-bridge arm. The Si 3L-ANPC arm integrates six full-power-rating Si IGBTs, where S₁, S₂, S₃, and S₄ switch at the fundamental frequency (FF), while S₅ and S₆ switch at LF. In contrast, the SiC half-bridge arm employs two lower-power-rating SiC MOSFETs (S₇ and S₈), switching at a comparatively HF. The Si arm in each phase connects a filter inductance L₁, and i_{x1, x = A, B, C} is the Si arm current, which includes a notable LF ripple. The SiC arm in each phase connects a filter inductance L₂, and i_{x2, x = A, B, C} is the SiC arm current, which includes the compensated LF ripple. The i_{x, x = A, B, C} is the total output current of the Si and SiC arms.

The corresponding hybrid-frequency sinusoidal pulse width modulation (SPWM) scheme is shown in Figure 1b. There are LF (about 2–5 kHz) and HF (above 50 kHz) two carrier frequencies. In the Si-based 3L-ANPC arm, the FF Si IGBT pairs S₁ and S₃, as well as S₂ and S₄, consistently share identical gating signals. Also, the two FF Si IGBT pairs operate complementarily. The LF Si IGBTs S₅ and S₆ are switched by complementary PWM signals. In the SiC-based half-bridge arm, the HF SiC MOSFETs S₇ and S₈ are switched complementarily. Using the modulation scheme, the switching frequency of Si IGBTs is decreased to reduce the switching loss. Meanwhile, HF switching events are moved to SiC MOSFETs to improve efficiency. The low-conduction-loss advantage of Si IGBT under high current conditions can also be fully utilized.

2.2. Operation Principle of Current Ripple Compensation

Before designing the current control strategy, it is necessary to explore the operation principle of current ripple compensation in this converter. Firstly, taking the grid-connected application as an example, the three-phase equivalent circuit of the proposed converter is derived as shown in Figure 2. In SPWM, the line-to-neutral voltage consists of the fundamental frequency component and the harmonic component by Fourier decomposition. Moreover, the harmonic component is primarily concentrated around the switching frequency, ignoring the effects of dead-time, device nonlinear characteristics, and other factors.

To improve readability, the equivalent circuits at different frequency ranges are derived as shown in Figure 3, taking phase A as an example. In Figure 3a, for the full frequency range, the line-to-neutral voltages can be expressed.

$$v_{A1N}=v_{A1N,FF}+v_{A1N,LF}$$

(1)

$$v_{A2N}=v_{A2N,FF}+v_{A2N,HF}$$

(2)

where V_A1N represents the line-to-neutral voltage of the Si arm, V_A1N,FF represents its fundamental frequency component, and V_A1N,LF represents its harmonic component. Similarly, V_A2N represents the line-to-neutral voltage of the SiC arm, V_A2N,FF represents its fundamental frequency component, and V_A2N,HF represents its harmonic component. In practical applications, it is assumed that ωL₁ >> R_L1 and ωL₂ >> R_L2. Thus, the resistance value of the filter inductors is allowed to be neglected. In Figure 3b, at the fundamental frequency, the Si arm current and grid current can be expressed.

$$i_{A1,FF}={\displaystyle \frac{1}{L_1}}{\displaystyle \int (v_{A1N,FF}-v_{A2N,FF})dt}$$

(3)

$$i_{A,FF}={\displaystyle \frac{1}{L_2}}{\displaystyle \int (v_{A2N,FF}-v_{GA,FF})dt}$$

(4)

where v_GA,FF represents the grid voltage. In Figure 3c, since the switching frequency of the SiC arm is much higher than that of the Si arm, the SiC arm has no harmonic voltage at the LF range. The LF current ripple generated by the Si arm harmonic voltage can be expressed.

$$i_{A1,LF}={\displaystyle \frac{1}{L_1}}{\displaystyle \int v_{A1N,LF}dt}$$

(5)

The SiC arm is equivalent to a short circuit for the LF current ripple, preventing it from flowing into the grid. In Figure 3d, the HF harmonic voltage of the Si arm can be disregarded, so the HF harmonic current is only generated by the SiC arm. Moreover, this HF current is insignificant compared to the FF and LF components. Thus, the Si arm current is approximately equal to the main FF current plus LF harmonic current.

$$i_{A1}\doteq i_{A1,FF}+i_{A1,LF}$$

(6)

The SiC arm current is approximately equal to the compensated LF harmonic current plus fractional FF current.

$$i_{A2}\doteq -i_{A1,LF}+i_{A2,FF}$$

(7)

The grid current contains the FF component and the HF harmonic component.

$$i_A=i_{A1,FF}+i_{A2,FF}+i_{A,HF}$$

(8)

Therefore, the proposed converter has the potential for high power quality.

Based on the above analysis, the schematic diagram of current ripple compensation waveforms is given in Figure 4. It is assumed that the average current value remains constant within one Si arm switching period T_{sw_Si}. In order to reduce cost and volume, the inductance value L₁ is minimized as much as possible. Meanwhile, the switching frequency of the Si arm is decreased to reduce losses, resulting in a large LF current ripple, as shown by the blue solid line in Figure 4. By appropriate current control strategy, the SiC arm operates at HF to compensate the Si arm current ripple and process the minor power, as shown by the yellow solid line in Figure 4. The current ripple of the SiC arm consists of two components. The first is the LF component, which is opposite to that of the Si arm. The second is the HF component, which is generated by the own HF switching events. As shown in the gray solid line in Figure 4, the total current ripple only has the HF component, which is determined only by the SiC arm and has nothing to do with the Si arm, achieving complete LF component compensation. Because of the high switching frequency of the SiC arm, the inductance value L₂ is smaller than L₁. The volume of inductors can be reduced while enhancing power quality.

In Figure 4, the dotted lines represent the average values corresponding to the solid lines. Since the Si and SiC arms share the output power, the average current relationships can be derived as follows.

$$M\_i_{A1}=K\ast M\_i_A$$

(9)

$$M\_i_{A2}=(1-K)\ast M\_i_A$$

(10)

where M_i_A1, M_i_A2, and M_i_A represent the Si arm average current, the SiC arm average current, and the total average current, respectively. K (0 < K < 1) represents the major power-sharing ratio. The current ripple ratio of the Si arm r_A1 is defined by the following formula.

$$r_{A1}=\Delta i_{A1}/M\_i_{A1}$$

(11)

where Δi_A1 represents the maximum peak-to-peak current ripple of the Si arm in one FF period. Since the SiC arm completely compensates the LF ripple, the following equation holds true.

$$\Delta i_{A2}=\Delta i_{A1}$$

(12)

During this LF switching period, the peak current of the Si arm i_A1,peak can be expressed.

$$i_{A1,peak}=M\_i_{A1}+{\displaystyle \frac{1}{2}}\Delta i_{A1}$$

(13)

To avoid the circulating current in the SiC arm, i_A1,peak should be less than the average value of the total current. Thus, the range of major power-sharing ratio K is limited by the following inequalities.

$$0<K<{\displaystyle \frac{1}{1+r_{A1}/2}}$$

(14)

3. Proposed Current Control Strategy

In this section, the closed-loop cooperative current control strategy is proposed to realize unequal current sharing and complete LF current ripple compensation. The block diagram of the control strategy is shown in Figure 5, which consists of two parts: the Si arm control loop (purple box) and the SiC arm control loop (red box). The following provides a detailed explanation of these two parts.

3.1. Si Arm Current Control

According to the control objective, the Si arm processes the main power. The major power sharing ratio K is used to generate the three-phase reference value of the Si arm current.

$$i_{ABC1\_ref}=K\ast i_{ABC\_ref}$$

(15)

where i_{ABC_ref} is the three-phase reference value of the total current, which is usually determined by the target output power. The current distribution in the Si arm can be adjusted by modifying the parameter K, enabling flexible power-sharing capabilities. Considering the reference value is the FF current, the control loop is designed in the dq-frame, rotating with the grid angular frequency ω₀. To enhance the dynamic response and disturbance resistance of the system, the grid voltage v_g is used for feed-forward control. The traditional proportional-integral (PI) controller is used to achieve no-static-error tracking of FF current. The proportional gain K_p is designed to achieve the desired closed-loop bandwidth. Applying the magnitude condition (0 dB gain at the crossover frequency f_c) leads to the dominant relationship K_p ≈ 2πf_cL, ensuring fast dynamic response. The integral gain K_i is designed to shape the phase margin. By setting the zero frequency f_z of the PI controller, we can compensate for the phase lag introduced by the plant’s pole, following K_i = K_p⋅2πf_z, guaranteeing stability and robustness. The Si arm controller proportional coefficient K_p1 and the integral coefficient K_i1 are designed as follows.

$$K_{p1}=2\pi f_{c1}{L}_1$$

(16)

$$K_{i1}=2\pi f_{z1}{K}_{p1}$$

(17)

where the control bandwidth f_c1 and integral corner frequency f_z1 can be designed as follows.

$$f_{c1}\le {\displaystyle \frac{f_{sw\_Si}}{10}}\sim {\displaystyle \frac{f_{sw\_Si}}{5}}$$

(18)

$$f_{z1}={\displaystyle \frac{f_{c1}}{10}}\sim {\displaystyle \frac{f_{c1}}{5}}$$

(19)

where f_{sw_Si} is the switching frequency of the Si arm. In order to increase the control stability, the control period is equal to the switching period of the SiC arm. Therefore, the updating frequency of the Si arm reference voltage is equal to f_{sw_SiC}, while the carrier frequency is equal to f_{sw_Si}.

3.2. SiC Arm Current Control

The control objective of the SiC arm is to compensate for the LF ripple current and process the minor power. Thus, the SiC arm three-phase current reference can be divided into two parts. The LF ripple current generated by the Si arm can be expressed.

$$\Delta i_{ABC\_comp}=i_{ABC1\_ref}-i_{ABC1}$$

(20)

Thus, the three-phase current reference of the SiC arm can be expressed.

$$i_{ABC2\_ref}=(1-K)\ast i_{ABC\_ref}+\Delta i_{ABC\_comp}$$

(21)

Considering the reference value consists of the FF and LF current, the control loop is designed in the abc-frame. Similarly, the PI controller is selected to track the FF and LF ripple current. The SiC arm controller proportional coefficient K_p2 and the integral coefficient K_i2 are designed as follows.

$$K_{p2}=2\pi f_{c2}{L}_2$$

(22)

$$K_{i2}=2\pi f_{z2}{K}_{p2}$$

(23)

where the control bandwidth f_c2 and integral corner frequency f_z2 can be designed as follows.

$$f_{c2}\le {\displaystyle \frac{f_{sw\_Si\mathrm{C}}}{10}}\sim {\displaystyle \frac{f_{sw\_SiC}}{5}}$$

(24)

$$f_{z2}={\displaystyle \frac{f_{c2}}{10}}\sim {\displaystyle \frac{f_{c2}}{5}}$$

(25)

where f_{sw_SiC} is the switching frequency of the SiC arm.

4. Simulation Verification

In this section, a three-phase Si and SiC hybrid arms ANPC converter based on the cooperative current control strategy is simulated in PLECS (4.8.9) software, considering its extremely fast simulation speed and unique thermal analysis function. The parameters of the simulation system are provided in

Table 1. Simulation parameters.

Parameter	Value
DC Bus Voltage Vdc	800 V
Fundamental Frequency fb	50 Hz
Si Arm Switching Frequency fsw_Si	2.5 kHz
SiC Arm Switching Frequency fsw_SiC	50 kHz
Si Arm Filter Inductance L1	1 mH
SiC Arm Filter Inductance L2	500 μH
Load Resistor Rload	3 Ω

. The results of performance comparison between the proposed topology and existing typical topologies are also presented.

Taking phase-A as an example, the simulation waveforms of the Si arm current, the SiC arm current, and the total current are displayed in Figure 6. The results are consistent with the theoretical analysis. As can be seen in Figure 6a, the Si arm generates a large current ripple because of the low switching frequency, and the total harmonic distortion (THD) is 13.46%. Under the condition K = 1, the SiC arm only compensates the LF current ripple. By employing the proposed current control strategy, the THD of the total current is reduced to 1.04%. Figure 6b shows the detailed waveforms of the current ripple compensation. It can be concluded that the SiC arm can completely compensate for the LF ripple current generated by the Si arm, and the total current only includes the FF and HF ripple components. It can be seen from Figure 6c, when K changes from 1 to 0.8, the good power quality can be maintained while the circulating current between the Si and SiC arms can be reduced. The three-phase voltage and current waveforms are shown in Figure 7. At t = 0.1 s, the reference value of the three-phase current i_{ABC_ref} changes from 70 to 100. At t = 0.15 s, the cosine value of the angle reference changes from 1 to 0.8. It can be concluded that the proposed converter can achieve high control dynamics for the step changes in the current reference and angle reference. A grid-connected operation case where the converter undergoes a step change from outputting pure active power to combined active and reactive power is presented in Figure 8. It can be demonstrated that the proposed control strategy exhibits excellent transient performance with rapid dynamic response, while maintaining superior power quality both before and after the transition period.

5. Experimental Results

To further verify the effectiveness of the proposed closed-loop cooperative current control strategy, experiments are carried out on a hardware-in-loop platform, as shown in Figure 9. The controller is implemented by a DSP (TMS320F28377D) control system. The power part of the proposed converter is simulated by the RTScale real-time simulator. Critical waveforms were captured and analyzed using a high-bandwidth digital oscilloscope, ensuring accurate measurement of dynamic performance and power quality. Due to the symmetry of the circuit, the waveforms of current in phase A are selected for presentation. The steady-state experimental waveforms of the current under i_{ABC_ref} = 90 A and K = 1 are presented in Figure 10. It can be seen from Figure 10a that the Si arm processes the total load current while generating a considerable ripple current due to the reduced switching frequency. Under this condition, the SiC arm only compensates the LF ripple current. It can be seen from Figure 10b that the LF ripple current is eliminated, but there is a circulating current between the Si and SiC arms, leading to additional power losses. The steady-state experimental waveforms of the current under i_{ABC_ref} = 90 A and K = 0.7 are presented in Figure 11. It can be seen from Figure 11a that the SiC arm compensates the LF ripple current while sharing minor load current. It can be seen from Figure 11b that there is no circulating current between the Si and SiC arms by adjusting the major power sharing ratio K. It can be concluded from Figure 10 and Figure 11 that the flexible power sharing and complete ripple current compensation can be realized by employing the proposed current control strategy. Meanwhile, because of the extremely high equivalent switching frequency, the excellent power quality of the output total current can be achieved. It can also be maintained regardless of changing K.

Furthermore, the dynamic waveforms of the current while K changes from 1 to 0.7 are presented in Figure 12. During the dynamic process of changing the power sharing ratio, there are no fluctuations occurring in the total output current. This provides the possibility of adjusting the optimal K under different operation conditions. Figure 13 shows the dynamic experimental waveforms of the current while i_{ABC_ref} changes from 70 A to 100 A. It can be found that the high control dynamics for the step changes in the current reference can be achieved. When the load power is changed, the steady-state current sharing between the Si and SiC arms can remain unchanged. The dynamic changes in the current sharing between the Si and SiC do not affect the total output current. The dynamic experimental waveforms of the line-to-neutral current while changing the current reference are presented in Figure 14. It can be found that the proposed current control can be applied effectively in the three-phase circuits.

6. Performance Comparison

6.1. Cost Comparison

To prove the cost-effectiveness of the proposed converter, the all-SiC and all-Si 3L-ANPC topologies are chosen for comparison. Considering the DC bus voltage is 800 V, the 650 V voltage rating Si IGBTs or SiC MOSFETs are selected to configure the all-SiC or all-Si topologies. For the proposed hybrid arms converter, Si IGBTs S₁–S₆ select the 650 V voltage rating devices, while SiC MOSFETs S₇–S₈ select the 1200 V voltage rating and smaller current rating devices. For a fair comparison, the filter inductors of the three topologies are selected to have the same inductance value. It should be considered that the proposed converter uses one more driver chip and current sensor in each phase than the all-SiC and all-Si converters. The chosen components and total price for each phase of three topologies are summarized in

Table 2. Chosen components and cost comparison.

Components	All-SiC	All-Si	Proposed
SiC MOSFET	C3M0015065K ($35.20 × 6)	/	C3M0040120K1 ($11.19 × 2)
Si IGBT	/	IKZ75N65EL5 ($4.01 × 6)	IKZ75N65EL5 ($4.01 × 6)
Driver IC	UCC21732 ($2.22 × 3)	UCC21732 ($2.22 × 3)	UCC21732 ($2.22 × 4)
Current Sensor	CASR 50-NP ($9.92 × 1)	CASR 50-NP ($9.92 × 1)	CASR 50-NP ($9.92 × 1) CASR 15-NP ($9.06 × 1)
Total Cost	$227.78	$40.64	$74.3

. The unit price of each component is taken from www.mouser.com, accessed on 10 October 2025. It can be found that, compared to the all-SiC converter, the proposed converter can achieve more than 60% total cost reduction.

6.2. Efficiency Comparison

To evaluate the efficiency performance of the proposed converter, the thermal model was created in the PLECS software environment. The power losses distribution of the proposed converter under i_{ABC_ref} = 90 A and K = 0.8 is presented in Figure 15. Due to the symmetry of the circuit, only half of the devices are presented. According to the results, the FF Si IGBTs S₁ and S₂ have almost no switching losses. The LF Si IGBT S₅ has very little switching loss because of reduced switching frequency. The power losses of the HF SiC MOSFET S₇ are very low due to its excellent switching characteristics. The results are consistent with the designed modulation scheme. Meanwhile, the power-sharing ratio between the Si and SiC arms can seriously affect the efficiency performance. Therefore, the proper selection of the major power sharing ratio K is very important for the efficiency optimization. In Figure 16, the relationship curve between the major power sharing ratio K and power losses under i_{ABC_ref} = 90 A is presented. From this curve, the optimal K under this operating condition can be obtained. In Figure 17, the junction temperature of the devices under different major power sharing ratio K with i_{ABC_ref} = 90 A is presented. It can be found that a key feature of our control strategy is the optimization of temperature equilibrium between the Si and SiC devices via adjusting K. This active balancing prevents localized overheating in any single SiC device, thereby directly countering the temperature-activated mechanisms of gate oxide degradation and threshold voltage drift.

The all-SiC and all-Si 3L-ANPC converters are also chosen for the efficiency comparison. To ensure fairness, the three converters select the same value of filter inductance. Thus, the filter inductance values for all-SiC and all-Si converters are both 1.5 mH. The same modulation scheme is applied in the three converters. Moreover, the switching frequencies of all-SiC and all-Si converters are decided by the THD of the output current, which should be almost equal to that of the proposed converter. Based on the abovementioned conditions, the comparison results are fair and persuasive. In Figure 18, the simulated power losses and efficiency comparisons under different output power are presented. It can be found that the all-Si ANPC converter has the highest power losses. The proposed hybrid arms ANPC converter can achieve 30–40% power loss reduction compared to the all-Si converter in the full power range. In particular, under high-power operation conditions, the efficiency of the proposed converter is higher than that of the all-SiC ANPC converter. The reason is that Si IGBT has a lower conduction voltage than SiC MOSFET under large current conditions, leading to lower conduction losses. Meanwhile, the SiC arm processes the minor load current, which can fully leverage its advantages of low-switching-loss and low-conduction-loss under this condition. Therefore, the proposed topology fully leverages the respective advantages of Si IGBT and SiC MOSFET. It is more attractive than an all-SiC converter in many high-power industrial applications due to higher efficiency and lower cost.

7. Conclusions

In this paper, a Si and SiC hybrid arms ANPC converter combined with the hybrid-frequency modulation scheme and the WFPP concept was proposed. The advantages of the proposed converter can be concluded as follows.

(1)

The proposed converter uses smaller current rating SiC devices, which can achieve more than 60% total cost reduction compared to the all-SiC 3L-ANPC converter.

(2)

Although the switching frequency of Si devices is decreased to reduce power losses, the equivalent switching frequency is equal to that of the all-SiC design. Thus, excellent power quality can be achieved.

(3)

By employing the hybrid-frequency modulation scheme and proposed current control strategy, the proposed converter can reduce 30–40% power losses compared to the all-Si converter in the full power range. Moreover, the efficiency under high-current conditions is higher than that of the all-SiC design.

The proposed converter fully leverages the respective advantages of Si IGBT and SiC MOSFET, achieving the comprehensive optimization of power quality, efficiency, and cost. It is more attractive than an all-SiC converter in high-power industrial applications due to higher efficiency and lower cost. For extension to medium- and high-voltage applications (e.g., 10-kV grid-connected inverters), the proposed topology offers two clear paths for voltage scaling. On one hand, it can serve as a submodule in cascaded H-bridge (CHB) or the modular multilevel converter (MMC). On the other hand, direct series-connection of devices within each switch presents another viable route.