Carrier Reconfiguration for Improving Output Voltage Quality and Balancing Capacitor Voltages in MMDTC-Based STATCOM

Abstract

For Modular Multilevel DC-Link T-Type Converter (MMDTC)-based STATCOMs, under identical operating conditions, the submodule (SM) capacitor voltage ripple is inversely proportional to its capacitance value. A configuration with a lower capacitance will inevitably result in significant capacitor voltage ripples. During the PWM modulation process, these ripples can lead to distortions in the output voltage waveform. To address this issue, this paper proposes an innovative carrier reconfiguration method that not only compensates for the output voltage pulse deviation caused by SM capacitor voltage ripples but also achieves effective balancing of the SM capacitor voltages. Finally, the validity and performance of the proposed carrier reconfiguration method are verified through both simulations and experimental results.

1. Introduction

Modular Multilevel DC-Link T-Type Converters (MMDTCs) present significant advantages for high-voltage, high-capacity Static Synchronous Compensators (STATCOMs), including reduced component count, low power loss, and robust tolerance to grid imbalances [1]. A critical challenge in conventional MMDTC-STATCOM design, however, is the reliance on large electrolytic capacitors within submodules (SMs) to suppress capacitor voltage ripples and ensure high-quality output waveforms. While effective, electrolytic capacitors suffer from inherent limitations such as shorter lifespan, an ability to withstand lower voltage/current, and reduced reliability compared to film capacitors. Film capacitors offer superior performance in these aspects but are characterized by lower capacitance density and higher cost [2,3,4,5]. To facilitate the adoption of more reliable film capacitors, there is a compelling need to develop operational strategies that enable MMDTC-STATCOMs to function effectively with significantly reduced SM capacitance values.

Addressing this need, the concept of a low-capacitance operation mode for MMDTC-STATCOMs has been introduced [6]. This mode exploits the phase relationship between the SM capacitor voltage and the arm voltage during reactive power compensation, allowing for substantial SM capacitor voltage ripples while maintaining the fundamental output performance. Crucially, this permits the use of low-capacitance, film-based capacitors. However, operating with low capacitance inherently introduces significant SM capacitor voltage ripples. These ripples propagate through the Pulse Width Modulation (PWM) process, directly distorting the output voltage waveform and degrading its quality Furthermore, ensuring stable operation demands effective balancing of the SM capacitor voltages under these high-ripple conditions.

Existing SM capacitor voltage balancing strategies primarily fall into two categories: the sorting method and Carrier Phase-Shifted PWM (CPS-PWM). Sorting methods dynamically select which SMs to insert based on capacitor voltage measurements and the arm current direction within each control cycle [7,8,9,10,11,12,13,14,15,16]. While various enhancements exist (e.g., incorporating preservation factors [6], equalization coefficients [13], or fundamental frequency operation [16]), sorting methods inherently suffer from drawbacks: they often lead to uneven switching distribution and power loss among SMs, compromise long-term reliability, and do not guarantee a fixed switching frequency. Conversely, CPS-PWM techniques inherently maintain a fixed switching frequency and promote balanced SM utilization. Numerous CPS-PWM variants have been developed for modular converters, achieving voltage balancing through modulation wave adjustments [17,18,19,20,21,22,23], as shown in Figure 1. Techniques include controlling high-frequency current components [17], decoupled sampling schemes [18], linearized pulse sorting [19], hybrid control strategies [20], generalized balancing algorithms [21], methods addressing asynchronous sampling [22], and flexible voltage control via reference signal manipulation [23].

However, a critical limitation persists across both sorting methods and CPS-PWM variants: none comprehensively address the detrimental impact of large SM capacitor voltage ripples—inherent in low-capacitance operation—on the quality of the output voltage waveform. While focused on achieving voltage balance, these methods neglect the fact that the fluctuating capacitor voltage itself becomes the source voltage during PWM switching. This ripple directly modulates the amplitude of the output voltage pulses, introducing significant harmonic distortion that existing balancing controls do not compensate for. Therefore, operating MMDTC-STATCOMs in a low-capacitance mode necessitates a control strategy that simultaneously achieves two tightly coupled objectives: (1) effective balancing of SM capacitor voltages, and (2) compensation for the output voltage distortion caused by the permitted capacitor voltage ripples.

To bridge this gap, this paper proposes an innovative carrier reconfiguration method specifically designed for low-capacitance MMDTC-STATCOMs. The core insight is that dynamically adjusting the carrier signal, rather than the modulation wave, offers a pathway to independently control both objectives. The key contributions are as follows:

(1)

Problem Analysis and Coupling Mechanism: A detailed analysis of how the carrier signal influences both output voltage quality and capacitor charging/discharging durations, revealing the inherent coupling and potential conflict between these two control objectives under carrier adjustment.

(2)

Dual-Objective Carrier Reconfiguration: A novel strategy involving two sequential carrier adjustments per control cycle:

The first reconfiguration targets the AC component of the capacitor voltage ripple to compensate for output voltage pulse deviations, preserving waveform quality.

The second reconfiguration targets the DC component deviation to achieve precise SM capacitor voltage balancing.

This paper is organized to provide a comprehensive understanding of the proposed carrier reconfiguration method. Section 2 introduces the MMDTC-STATCOM topology and its low-capacitance operation—a relatively new concept that creates unique control challenges. Section 3 presents novel analysis revealing the coupling between output quality and voltage balancing objectives under high-ripple conditions. Building on these insights, Section 4 develops the carrier reconfiguration method. Readers familiar with MMDTC fundamentals may proceed directly to Section 3, while those seeking only the method implementation can start from Section 4, though the full context enhances understanding.

2. The Operating Principle of an MMDTC-STATCOM with Low Capacitance

As depicted in Figure 2, the MMDTC-STATCOM consists of two arms and a T-type switching structure. The upper and lower arms are constructed using Half-Bridge Submodules (HBSMs). Each phase of the T-type structure comprises three high-voltage switches (T_ku, T_kn, T_kl; k = a, b, c). These high-voltage switches can be implemented using series-connected IGBTs, series-connected IGCTs, or series-connected thyristors [1,6].

As depicted in Figure 3, the switching functions for each phase of the T-type structure are defined as S_x (x = a, b, c). Specifically, S_x = 1, 0, and −1 correspond to the conduction states of the upper, middle, and lower switches of phase x, respectively, and then the relationship between the arm voltages and the line-to-line voltages can be derived [1,2].

The output phase voltages of the MMDTC can be defined as follows:

$$u_{\mathrm{a}\mathsf{o}, \mathrm{bo}, \mathrm{co}} = V_{\mathsf{o}}\sin (\mathsf{\omega }t+\pi /6+2k\pi /3)$$

(1)

where k takes the values of 0, −1, and 1 accordingly; V₀ represents the amplitude of the phase voltage; and ω = 2πf.

Then, the output line voltage can be obtained:

$$u_{\mathrm{ab}, \mathrm{bc}, \mathrm{ca} }=\sqrt{3}{V}_{\mathsf{o}}\sin (\mathsf{\omega }t+\pi /3+2k\pi /3)$$

(2)

The instantaneous expressions of the arm voltages are as follows:

$$u_{\mathrm{UN}}=\left\{\begin{array}{ll}\sqrt{3}{V}_o\sin \theta ,& \theta \in [0,{\displaystyle \frac{\pi }{3}})\\ \sqrt{3}{V}_o\sin (\theta +{\displaystyle \frac{\pi }{3}}),& \theta \in [{\displaystyle \frac{\pi }{3}},{\displaystyle \frac{2\pi }{3}}]\end{array}\right.$$

(3)

$$u_{\mathrm{NL}}=\left\{\begin{array}{ll}-\sqrt{3}{V}_o\sin (\theta -{\displaystyle \frac{\pi }{3}}),& \theta \in [0,{\displaystyle \frac{\pi }{3}})\\ \sqrt{3}{V}_o\sin (\theta -{\displaystyle \frac{\pi }{3}}),& \theta \in [{\displaystyle \frac{\pi }{3}},{\displaystyle \frac{2\pi }{3}}]\end{array}\right.$$

(4)

where $\theta =\mathsf{\omega }t-floor\left(\mathsf{\omega }t/({\displaystyle \frac{2\pi }{3}})\right)$, floor (α) refers to rounding down the elements of α to the nearest integers.

As depicted in Figure 4, the MMDTC-STATCOM features two reactive power compensation modes: the capacitive compensation mode and the inductive compensation mode. In the capacitive compensation mode, the output voltage of the MMDTC is marginally higher than the grid voltage. Conversely, in the inductive compensation mode, the output voltage of the MMDTC is slightly lower than the grid voltage. The inductive voltage drop associated with AC filtering inductor influences this difference, as follows:

$$V_{\mathrm{o}}=\left\{\begin{array}{l}(1+\lambda )V_{\mathrm{g}}, \mathrm{In} \mathrm{capacitive} \mathrm{mode}\\ (1-\lambda )V_{\mathrm{g}}, \mathrm{In} \mathrm{inductive} \mathrm{mode}\end{array}\right.$$

(5)

where V_g refers to the amplitude of the grid phase voltage, and λ = ωLI_o/V_g refers to the ratio of the voltage drop across AC filtering inductor.

As depicted in Figure 4, a comparison is presented between the high-capacitance operation and the low-capacitance operation of the MMDTC-STATCOM [6]. In the high-capacitance operation, capacitors with larger capacitance values are employed to suppress voltage ripples, ensuring that the cluster capacitor voltage remains consistently higher than the arm voltage, regardless of whether in capacitive mode (Figure 4a) or in inductive mode (Figure 4b). Specifically, the valley value (NU_{c_valley}) of the cluster capacitor voltage must always exceed the peak value of the arm voltage of 1.5(1 + λ)V_g in the capacitive compensation mode. Conversely, the low-capacitance operation leverages the characteristic wherein the SM capacitor voltage and the arm voltage are in phase during capacitive compensation, allowing for a relatively large ripple in the capacitor voltage, as shown in Figure 4c. In the inductive compensation mode, as shown in Figure 4d, as the SM capacitor voltage is inverted relative to the arm voltage, it is essential to ensure that the valley value (NU_{c_valley}) of the cluster capacitor voltage is not less than the peak value of 1.5(1 − λ)V_g of the arm voltage. This represents the condition that must be satisfied in low-capacitance operation.

From the above analysis, it can be concluded that by utilizing the phase characteristics of the capacitor voltage and the arm voltage, a considerable ripple in the capacitor voltage is permissible. This mode of operation is referred to as low-capacitance operation. By modulating the width of a series of pulses in the PWM modulation process, the desired waveform shape and amplitude can be effectively achieved. Taking Figure 5a as an example, when the ripple of the capacitor voltage is minimal (typically within 10%), the ripple component can be neglected. In other words, the capacitor voltage only contains the DC component (u_c = U_dc). Assuming the modulated wave is V_ref, when the carrier frequency is sufficiently high, the switching harmonics can be ignored. Consequently, the output voltage after modulation can be expressed as:

$$u_o(t)=u_c{V}_{ref}(t)=U_{dc}{V}_{ref}(t)$$

(6)

However, when the capacitor voltage exhibits the larger ripples, the ripple component becomes non-negligible. Owing to the triple-frequency ripple of the SM capacitors in the MMDTC-STATCOM, expressed a: u_c = U_dc + U₃sin(3ωt), the same PWM modulation method is applied. As illustrated in Figure 5b, the resulting output voltage after modulation can be represented as:

$$\begin{array}{llll}{u}_o(t)=u_c{V}_{ref}(t)& =\underline{U_{dc}{V}_{ref}(t)}& +& \underline{U_3\cos (3\mathsf{\omega }t)V_{ref}(t)}\\ & \mathrm{Designed\; voltage}& & \mathrm{Undesigned\; voltage}\end{array}$$

(7)

Equation (7) reveals a critical phenomenon: the fluctuating component of the capacitor voltage is propagated to the output side through the PWM modulation process, thereby increasing the harmonic distortion in the output voltage. This indicates that under the low-capacitance operation mode, the influence of capacitor voltage ripples on the output voltage quality must be carefully assessed. To address this issue, this paper proposes an innovative SM capacitor-voltage-balancing control technique based on carrier reconfiguration.

3. Impact of Carrier Signal on Output Voltage Quality and Capacitor Voltage Balance

In the PWM modulation process, maintaining a constant modulated wave signal while dynamically adjusting the carrier signal can achieve capacitor voltage balancing and compensation for the influence of the SM capacitor voltage ripple on the output voltage quality. However, when pursuing the dual control objectives of capacitor voltage balancing and output voltage quality simultaneously, complex scenarios involving mutual constraints or mutual enhancements often arise. The following section will present a detailed analysis.

3.1. Impact of Carrier Signal on Output Voltage Quality

In fact, ripples in the capacitor voltage modify the amplitude of the output voltage pulse signal during the PWM modulation process, leading to deviations from the desired value and consequently affecting the total harmonic distortion (THD) of the output voltage. To effectively compensate for this deviation, the pulse width can be adjusted by fine-tuning the carrier signal. As illustrated in Figure 6, within any carrier period T_c, when the instantaneous value u_c of the capacitor voltage is lower than the DC component U_dc*, it results in a reduced amplitude of the output voltage pulse signal. In this case, the pulse width can be increased by appropriately decreasing the carrier amplitude, thereby compensating for the pulse deviation. Conversely, when u_c exceeds the DC component U_dc*, the amplitude of the output voltage pulse signal increases. At this point, the carrier amplitude should be increased accordingly to decrease the pulse width, thereby reducing the pulse deviation.

3.2. Impact of Carrier Signal on Capacitor Voltage Balancing

In essence, capacitor voltage balancing can be achieved by precisely controlling the charging and discharging durations of each SM. For analytical purposes, the direction of the arm current is defined as illustrated in Figure 7. Since the MMDTC’s arm comprises multiple SMs connected in series, the current through each SM corresponds to the arm current i_arm. When the arm current direction is defined as positive, the capacitor enters a charging state; conversely, it transitions to a discharging state.

As shown in Figure 8, the detailed implementation for achieving capacitor voltage balancing is as follows:

(1)

When the capacitor voltage is lower than its reference value u_c*:

(a)

If the arm current i_arm is positive (indicating a charging state), the carrier amplitude should be decreased to extend the capacitor’s charging duration, as shown in Figure 8a.

(b)

If the arm current i_arm is negative (indicating a discharging state), the carrier amplitude should be increased to decrease the amount of charge released from the capacitor, as shown in Figure 8b.

(2)

Conversely, when the capacitor voltage is higher than its reference value u_c*:

(a)

If the arm current i_arm is positive, the carrier amplitude should be increased to restrict further charging of the capacitor, as shown in Figure 8c.

(b)

If the arm current i_arm is negative, the carrier amplitude should be reduced to enhance the capacitor’s discharge process, as shown in Figure 8d.

Figure 8. Impact of carrier signal on capacitor voltage balancing under the conditions of (a) u_c < u_c* and i_arm > 0, (b) u_c < u_c* and i_arm < 0, (c) u_c > u_c* and i_arm > 0, and (d) u_c > u_c* and i_arm < 0, respectively.

Figure 8. Impact of carrier signal on capacitor voltage balancing under the conditions of (a) u_c < u_c* and i_arm > 0, (b) u_c < u_c* and i_arm < 0, (c) u_c > u_c* and i_arm > 0, and (d) u_c > u_c* and i_arm < 0, respectively.

This control precisely regulates the conduction time of the SMs by dynamically adjusting the carrier amplitude, thereby ensuring accurate and balanced control of the capacitor voltage.

3.3. Mutual Influence and Coupling Between Control Objectives

From a fundamental perspective, regardless of whether it is pulse deviation compensation or capacitor voltage balancing control, both are achieved by modulating the carrier amplitude to adjust the pulse width. Since both control objectives are regulated via the carrier signal, a coupling relationship inherently exists between them, as illustrated in Figure 9.

Figure 9a,b illustrate the relationship between carrier fine-tuning and pulse width variation under different conditions. It is evident that there is a mutual constraint between voltage pulse deviation compensation and capacitor voltage balancing control. Specifically, in the case shown in Figure 9a, pulse deviation compensation requires increasing the carrier amplitude to reduce the pulse width, whereas capacitor voltage balancing control necessitates decreasing the carrier amplitude to increase the pulse width. These two control objectives impose entirely opposing requirements on the carrier signal. Similarly, in the scenario depicted in Figure 9b, pulse deviation compensation demands reducing the carrier amplitude, while capacitor voltage balancing control requires increasing the carrier amplitude to narrow the pulse width. This further underscores the mutually restrictive nature of the two control objectives.

Conversely, when the arm current i_arm > 0, as shown in Figure 9c,d, the requirements of the two control targets for carrier fine-tuning exhibit consistency, establishing a mutually reinforcing relationship. However, this mutual enhancement could potentially result in an overestimation of the required carrier adjustment amount, thereby introducing additional modulation errors. Therefore, the coupling effect between these two control objectives must be carefully analyzed and fully considered.

4. Proposed Carrier Reconfiguration Method

To address the aforementioned issues, this paper proposes a reconfiguration of the carriers for each SM. As illustrated in Figure 10, when the capacitor voltage becomes unbalanced, it essentially indicates that the DC component U_dc deviates from the reference U_dc^*. In other words, as long as the measured value U_dc accurately tracks the reference value U_dc^*, the balance of the capacitor voltage can be effectively achieved.

The voltage difference Δu_c can be expressed as:

$$∆u_{\mathrm{c}}=u_{\mathrm{c}}-U_{dc}^{*}$$

(8)

And then, Δu_c can be further divided into two parts:

$$∆u_{\mathrm{c}}=∆u_{\mathrm{c}\_dc}+∆u_{\mathrm{c}\_ac}$$

(9)

Based on the preceding analysis, it is clear that the pulse deviation in the output voltage of the SM predominantly stems from the AC component of the capacitor voltage. Therefore, to compensate for this pulse deviation, only Δu_{c_ac} needs to be considered.

Based on the analytical conclusions presented in the previous section, the carrier can be reconfigured twice to achieve independent control. The first reconfiguration focuses on the AC component Δu_{c_ac}, aiming to compensate for the output voltage pulse. The second reconfiguration targets the DC component Δu_{c_dc}, aiming to implement capacitor voltage balancing control.

The specific implementation of carrier reconfiguration is illustrated in Figure 11. The carrier reconfiguration process will dynamically reconstruct the carrier for the next period within the current sampling period. The predicted value of the capacitor voltage is as follows:

$$u_c(k+1)=u_c(k)+{\displaystyle \frac{T_s}{C}}{i}_{arm}(k)S(k)$$

(10)

where u_c(k) denotes the measured capacitor voltage at time k; u_c(k + 1) represents the predicted capacitor voltage for the next sampling period at time k; i_arm(k) signifies the arm current at time k. The symbol T_s stands for the sampling period, and S is a switching function. Specifically, when the SM is active at time k, S(k) = 1; otherwise, S(k) = 0.

After obtaining u_c(k + 1), Δu_c(k + 1) at the moment of k + 1 can be calculated as follows:

$$∆u_{\mathrm{c}}(k+1)=u_{\mathrm{c}}(k+1)-U_{dc}^{*}$$

(11)

Further signal separation of Δu_c(k + 1) can yield Δu_{c_ac}(k + 1) and Δu_{c_dc}(k + 1) at the (k + 1)^th moment. These are then utilized for the first carrier reconfiguration and the second carrier reconfiguration, respectively.

4.1. The First Carrier Reconfiguration

The implementation of the first carrier reconfiguration is depicted in Figure 12. As can be observed, according to the voltage-second balance principle, introducing Δu_{c_ac}(k + 1) to adjust the carrier allows for the compensation of the SM’s output voltage. By employing the similar triangle rule, the mathematical expression for the carrier u_{carry_1} after the first carrier reconfiguration can be derived from Figure 12:

$$u_{\mathrm{carry}\_1}=\left\{\begin{array}{c}{\displaystyle \frac{U_{\mathrm{dc}}^{*}+∆u_{\mathrm{c}\_\mathrm{ac}}(k+1)}{U_{\mathrm{dc}}^{*}}}-{\displaystyle \frac{2}{T_{\mathrm{c}}{U}_{\mathrm{dc}}^{*}}}{\displaystyle {\int }_{k_0-\frac{T_c}{2}}^{k+1}\left[U_{\mathrm{dc}}^{*}+∆u_{\mathrm{c}\_\mathrm{ac}}(k+1)\right]d(k+1),k_0-\frac{T_{\mathrm{c}}}{2}\le k+1<k_0}\\ {\displaystyle \frac{2}{T_{\mathrm{c}}{U}_{\mathrm{dc}}^{*}}}{\displaystyle {\int }_{k_0}^{k+1}\left[U_{\mathrm{dc}}^{*}+∆u_{\mathrm{c}\_\mathrm{ac}}(k+1)\right]d(k+1),k_0\le k+1\le k_0+\frac{T_{\mathrm{c}}}{2}}\end{array}\right.$$

(12)

Also by the similar triangle rule, it can be concluded in Figure 12 that:

$${\displaystyle \frac{d_1/2}{V_{\mathrm{ref}}}}={\displaystyle \frac{∆d}{\frac{2}{T_c}{\displaystyle {\int }_{k_0}^{k_1}∆u_{\mathrm{c}\_\mathrm{ac}}(k+1)d(k+1)}}}$$

(13)

Transforming Equation (13) yields:

$$\gamma ={\displaystyle \frac{2∆d}{d_1}}={\displaystyle \frac{\frac{2}{T_c}{\displaystyle {\int }_{k_0}^{k_1}∆u_{\mathrm{c}\_\mathrm{ac}}(k+1)d(k+1)}}{V_{\mathrm{ref}}}}$$

(14)

It can be further concluded that:

$$d_2=(1-\gamma )d_1$$

(15)

where γ is the rate of change in d₂ with respect to d₁. From this analysis, it can be concluded that when Δu_{c_ac}(k + 1) > 0, γ > 0 and d₂ < d₁; when Δu_{c_ac}(k + 1) = 0, γ = 0 and d₂ = d₁; when Δu_{c_ac}(k + 1) < 0, γ < 0 and d₂ > d₁.

Through the first carrier reconfiguration, the expression of the arm voltage can be expressed as:

$$u_{\mathrm{arm}}={\displaystyle \sum _{j=1}^N\left[S_j(1-{\gamma }_j)u_{\mathrm{c}j}\right]}$$

(16)

where S_j represents the switching function of the jth SM; γ_j represents the rate of change in the jth SM d₂ with respect to d₁, and u_cj represents the capacitance voltage of the jth SM.

Let $∆u_{\mathrm{arm}}=-{\displaystyle \sum _{j=1}^N(S_j{\gamma }_j{u}_{\mathrm{c}j})}$. The aforementioned equation can be further reformulated as follows:

$$u_{\mathrm{arm}}={\displaystyle \sum _{j=1}^N(S_j{u}_{\mathrm{c}j})}+∆u_{\mathrm{arm}}$$

(17)

That is to say, Δu_arm is a compensation variable added to u_arm to eliminate the influence of capacitor voltage ripples on the output voltage.

4.2. The Second Carrier Reconfiguration

The second carrier reconfiguration is specifically designed to eliminate Δu_{c_dc}. Given that Δu_{c_dc} is relatively small, it can be effectively mitigated by adjusting the error proportional coefficient ρ. Notably, the precise value of ρ can be dynamically optimized based on the voltage balancing effect of the capacitor.

Figure 13 illustrates the implementation of the second carrier reconfiguration, which is performed based on the outcome of the first carrier reconfiguration. The specific formula is as follows:

$$u_{\mathrm{carry}\_2}=u_{\mathrm{carry}\_1}+\rho ∆u_{\mathrm{c}\_d\mathrm{c}}(k+1)*sign(i_{\mathrm{arm}}(k+1)),k_0-{\displaystyle \frac{T_c}{2}}\le k+1\le k_0+{\displaystyle \frac{T_c}{2}}$$

(18)

where sign(i_arm(k + 1)) represents the direction of the arm current at the (k + 1)^th moment.

From Equation (18), it can be inferred that when Δu_{cj_dc}(k + 1) = 0, no secondary reconfiguration is required. If Δu_{cj_dc}(k + 1) > 0 or Δu_{cj_dc}(k + 1) < 0, the carrier is dynamically compensated by constructing the product of ρ, Δu_{cj_dc}(k + 1), and sign(i_arm(k + 1)). This method ensures precise dynamic compensation for the carrier signal, ultimately eliminating the DC offset in the capacitor voltage. After undergoing two reconfigurations, the carrier can be expressed as follows:

$$u_{\mathrm{carry}}=\left\{\begin{array}{c}{\displaystyle \frac{U_{\mathrm{dc}}^{*}+∆u_{\mathrm{c}\_\mathrm{ac}}(k+1)}{U_{\mathrm{dc}}^{*}}}-{\displaystyle \frac{2}{T_{\mathrm{c}}{U}_{\mathrm{dc}}^{*}}}{\displaystyle {\int }_{k_0-\frac{T_c}{2}}^{k+1}\left[U_{\mathrm{dc}}^{*}+∆u_{\mathrm{c}\_\mathrm{ac}}(k+1)\right]d(k+1)+\rho ∆u_{\mathrm{c}\_\mathrm{dc}}(k+1)\ast sign(i_{\mathrm{arm}}(k+1)),k_0-\frac{T_c}{2}\le k+1<k_0}\\ {\displaystyle \frac{2}{T_{\mathrm{c}}{U}_{\mathrm{dc}}^{*}}}{\displaystyle {\int }_{k_0}^{k+1}\left[U_{\mathrm{dc}}^{*}+∆u_{\mathrm{c}\_\mathrm{ac}}(k+1)\right]d(k+1)}+\rho ∆u_{\mathrm{c}\_\mathrm{dc}}(k+1)\ast sign(i_{\mathrm{arm}}(k+1)),k_0\le k+1\le k_0+{\displaystyle \frac{T_c}{2}}\end{array}\right.$$

(19)

The reconfigured carriers, as depicted in Figure 14, are utilized for PWM modulation. This approach significantly differs from the conventional PWM modulation method illustrated in Figure 1. It can be observed that in the proposed method, each SM employs a shared modulation wave signal, and capacitor voltage balancing is achieved through precise adjustment of the carrier wave signal. Simultaneously, this method mitigates output voltage distortion caused by capacitor voltage ripples.

The proposed carrier reconfiguration method represents a paradigm shift from existing CPS-PWM strategies in several key aspects. Firstly, while conventional methods [17,18,19,20,21,22,23] achieve voltage balancing by adjusting the modulation wave signal, the proposed approach manipulates the carrier signal directly. This fundamental difference enables addressing not only voltage balancing but also the output voltage distortion caused by capacitor voltage ripples—a critical issue that existing methods overlook. Secondly, the proposed two-stage reconfiguration process (targeting AC and DC components separately) provides a systematic solution to the inherent coupling between voltage balancing and output quality objectives. This is particularly crucial for low-capacitance operation with a large ripple across the capacitor voltage.

Table 1. Comparison between existing CPS-PWM methods and the proposed carrier reconfiguration method.

Aspect	Existing CPS-PWM Methods [17,18,19,20,21,22,23]	Proposed Carrier Reconfiguration Method
Control Variable	Modulation wave adjustment	Carrier signal adjustment
Primary Objective	Capacitor voltage balancing only	Dual objectives: voltage balancing and output quality improvement
Handling of Voltage Ripples	Neglects impact on output quality	Actively compensates for ripple-induced distortions
Low-Capacitance Operation	Not specifically designed for high ripple conditions	Optimized for low-capacitance operation with high ripples
Control Structure	Single-stage adjustment	Two-stage reconfiguration
Pulse Deviation Compensation	No	Yes, through first carrier reconfiguration
Switching Frequency	Fixed	Fixed

summarizes the key differences between our method and existing approaches, demonstrating both conceptual innovations and quantitative improvements.

5. Simulation and Experimental Verification

5.1. Simulation Verification

To validate the correctness of the carrier reconfiguration proposed in this paper, a simulation model was developed in MATLAB/SIMULINK R2023b. The primary simulation parameters are presented in

Table 2. Main parameters of simulation.

Variable	Symbol	Values
Rated reactive power	Qrated	10 MVar
Rated grid line voltage	Vline	10 kV
Rated grid phase voltage	Vg	$\sqrt{2}{V}_{line}/\sqrt{3}$
AC filtering inductor	L	2.5 mH
Number of SMs per arm	N	18
Rated phase current amplitude	Io	817 A
SM capacitance	C1	2.6 mF
Peak voltage of SM capacitor	Uc_peak	735/800 V
Carrier frequency	fc	500 Hz
Sampling period	Ts	10 μs

. Crucially, for both the proposed method and the existing CPS-PWM method, an identical carrier frequency (f_c = 500 Hz) and sampling period (T_s = 10 μs) were strictly maintained throughout all simulations.

(a)

Verification of Capacitor Voltage Balancing

To evaluate the control effectiveness of carrier reconfiguration on capacitor–voltage balancing, simulation analyses were conducted for scenarios both without and with carrier reconfiguration. The absence of carrier reconfiguration indicates that the carrier remains unmodified; specifically, the initial carrier is used without incorporating any control strategy for capacitor voltage balancing. Figure 15a–c present the simulation results of output phase voltages, output currents, and SM capacitor voltages, respectively. It can be observed from Figure 15c that without carrier reconfiguration, the performance of capacitor voltage balancing is inadequate, resulting in significant distortion in both the output voltage and current waveforms, as shown in Figure 15a and Figure 15b, respectively. In contrast, the implementation of the proposed carrier reconfiguration technique markedly improves the capacitor voltage balancing across all SMs.

(b)

Verification of Voltage Quality Improvement

To verify the compensation effect of the proposed carrier reconfiguration on the output voltage pulse, a comparison with the existing control method (shown in Figure 1, conventional CPS-PWM with modulation wave adjustment for voltage balancing [17,18,19,20,21,22,23]) is presented. The number of SMs N increases progressively from 3 to 18 in increments of 3. Notably, during this process, the amplitude of the rated phase current, the peak value of the capacitor voltage, and the ripple rate of the capacitor voltage remain unchanged. Figure 16 and Figure 17 illustrate the simulation results for both the existing control method and the proposed method under varying numbers of SMs. It can be seen that the THD of both output voltages (Figure 16a,b) and output currents (Figure 16c,d) decrease with the increase in the number of SMs. However, using the proposed carrier reconstruction method, the THD value is lower than that using the existing method under the same conditions.

As can be observed from Figure 17a,b, the voltage pulse compensation does not compromise the capacitor voltage balancing effect. Furthermore, Figure 17c,d illustrate the arm current waveforms. The findings indicate that after the implementation of carrier reconfiguration method, the arm current remains largely unaffected.

A comprehensive statistical analysis was performed on the THD of both the output voltage and current, as shown in Figure 18a,b, respectively, for the two methods. The results indicate that the THD under the proposed method is significantly lower than that under the traditional method approach. Notably, when the number of SMs is constrained, this disparity becomes increasingly evident.

In addition, the proposed method is comprehensively compared with existing methods in both the capacitive compensation mode and inductive compensation mode. The simulation results are illustrated in Figure 19. As depicted in Figure 19a,b,e, the proposed method achieves accurate compensation for voltage pulse deviations caused by capacitor voltage ripples, irrespective of whether the converter operates in the capacitive or inductive reactive power compensation mode. Compared to the existing method, the waveform quality of the output voltage and current under the proposed method has been significantly enhanced.

By analyzing Figure 19c,d, it can be observed that both methods achieve capacitor voltage balancing under the two compensation modes. However, the proposed method introduces real-time carrier reconfiguration, dynamically adjusting the carrier amplitude in response to variations in capacitor voltage ripples. This adjustment aligns closely with the trend of capacitor voltage ripples, enabling the SM to achieve an optimized conduction time and effectively compensating for voltage pulse deviations.

5.2. Experimental Verification

The experimental platform constructed in the laboratory is illustrated in Figure 20. In this setup, RT-LAB functions as the controller, and the specific experimental parameters are outlined in Table 3. Identical hardware and timing parameters, specifically the carrier frequency (f_c = 3000 Hz) and sampling period (T_s = 10 μs), were applied to both the proposed carrier reconfiguration method and the existing CPS-PWM method with modulation wave adjustment during comparative testing.

(1)

Verification of Capacitor Voltage Balancing

To evaluate the effectiveness of the capacitor voltage balancing control, two operating conditions were considered: (1) inductive compensation mode without carrier reconfiguration, and (2) inductive compensation mode with carrier reconfiguration. As illustrated in Figure 21, the experimental results are presented for the output current (Figure 21a), output phase voltages (Figure 21b), and HBSM capacitor voltages (Figure 21c), respectively.

Figure 20. Photograph of MMDTC-STATCOM prototype.

Figure 20. Photograph of MMDTC-STATCOM prototype.

Table 3. The main experimental parameters.

Variable	Symbol	Value
Grid phase voltage	Vg	$110\sqrt{2}$ V
Rated amplitude of phase current	Io	5 A
Fundamental frequency	f	50 Hz
SM capacitance	C1	200 µF
AC filtering inductor	L	10 mH
Number of SMs per arm	N	5
Peak voltage of SM capacitor	Uc_peak	55 V
Carrier frequency	fc	3000 Hz
Sampling period	Ts	10 μs

Table 3. The main experimental parameters.

Variable	Symbol	Value
Grid phase voltage	Vg	$110\sqrt{2}$ V
Rated amplitude of phase current	Io	5 A
Fundamental frequency	f	50 Hz
SM capacitance	C1	200 µF
AC filtering inductor	L	10 mH
Number of SMs per arm	N	5
Peak voltage of SM capacitor	Uc_peak	55 V
Carrier frequency	fc	3000 Hz
Sampling period	Ts	10 μs

Figure 21. Experimental results of (a) grid voltage of phase-a and output currents, (b) output phase voltages, and (c) HBSM capacitor voltages without and with carrier reconfiguration, respectively.

Figure 21. Experimental results of (a) grid voltage of phase-a and output currents, (b) output phase voltages, and (c) HBSM capacitor voltages without and with carrier reconfiguration, respectively.

As illustrated in the left half of Figure 21, without carrier reconfiguration, no balancing measures were implemented for the capacitor voltages, leading to a divergent state in their operation. This divergence subsequently induced distortions in both the output voltage and output current. In contrast, as shown in the right half of Figure 21, the proposed method effectively achieves superior voltage balancing for the SM capacitors. As a result, the total THD of the output voltage is reduced from 29.21% to 25.68%, and the THD of the output current decreases from 6.34% to 3.85%.

(2)

Verification of Output Voltage Quality Improvement

Verification of pulse compensation for the output voltage of SMs was conducted under both the capacitive and inductive compensation modes. To demonstrate the improvement achieved, an experimental comparison was performed between the existing method and the proposed method. The experimental results are presented in Figure 22.

From Figure 22a,b, it can be clearly observed that the proposed control method reduces the THD of the output voltage by approximately 15% and the THD of the output current by approximately 25% compared to the existing method. This improvement is mainly attributed to the compensation for pulse deviation caused by ripples in the capacitor voltage during carrier reconfiguration. By precisely adjusting the carrier amplitude, the pulse width of the output voltage is regulated to effectively mitigate this deviation.

Figure 22c,d depict the waveforms of the arm voltages and the SM capacitor voltages, respectively. The results demonstrate that when the capacitor voltage undergoes significant ripples, applying the proposed method to compensate for the SM voltage pulse not only markedly enhances the quality of the arm voltage waveform but also effectively improves the balancing of the capacitor voltage.

Figure 22e illustrates the PWM signals for the upper-arm HBSM1 and lower-arm HBSM6. It can be observed that regardless of the method employed, the switching frequency of the submodule remains unchanged. In other words, the proposed method modifies only the amplitude of the carrier signal, without affecting its frequency.

6. Conclusions

This paper proposes a carrier reconfiguration method designed to simultaneously achieve capacitor voltage balancing and improved output voltage quality in low-capacitance MMDTC-STATCOM systems. First, the study highlights how the carrier signal affects the output waveform quality when significant capacitor voltage ripples occur. Then, it investigates voltage pulse deviation compensation and capacitor voltage balancing through precise carrier fine-tuning while also analyzing the intrinsic relationship between these two control objectives. The key innovation involves decoupling these dual control targets by implementing two sequential carrier adjustments per cycle: (1) the first adjustment compensates for AC-component-induced pulse deviations (Equation (12)), thereby directly enhancing voltage waveform fidelity; (2) the second adjustment eliminates DC offset errors through dynamic carrier amplitude modulation (Equation (18)), enabling accurate capacitor voltage balancing. The simulation results (Figure 18) show that the proposed method reduces the output voltage THD by 18–32% compared to conventional CPS-PWM methods under the same number of submodules. The experimental validation further demonstrates a 17% reduction (from 22.21% to 18.34%) and a 23% reduction (from 26.39% to 20.42%) in the output voltage THD under the capacitive and inductive operating modes, respectively, as shown in Figure 22.