Topology Analysis and Modeling Comparison of SI-SIMO Boost Converter Used in Multiple Output Applications

Abstract

This paper presents the analysis and modeling of a single-input, single-inductor, multiple-output (SI-SIMO) boost converter to address limitations of conventional SISO converters in distributed power supply applications. Based on switching-state analysis, a sequential PWM modulation strategy is proposed to achieve independent voltage regulation across multiple outputs using a single inductor. An average circuit model is developed considering steady-state characteristics. Inductor conduction mode boundaries and the critical inductor value are derived. A complete modeling process is introduced, transitioning from nonlinear dynamics to small-signal approximation at the steady-state operating point. PSIM and MATLAB Simulink experiment results validate the proposed control method and confirm the theoretical analysis under various operating conditions.

1. Introduction

Escalating global energy demands have positioned electricity as the primary energy medium due to its efficiency and sustainability, driving the need for multiport power converters to optimize energy distribution. While advancements in converter topologies address heterogeneous source–load integration, technical limitations persist. In PV systems, DC-DC converters boost solar panel outputs to grid-compatible levels. Recent designs like switched-inductor–capacitor modules enhance voltage gain but increase component complexity and cost [1,2]. Alternative dual-inductor configurations with capacitors achieve comparable gains without extreme duty cycles [3,4] yet suffer from 10 kHz switching losses and ESR-related inefficiencies, capping maximum efficiency at 92–93%. These challenges highlight critical trade-offs between performance gains and operational reliability in converter design.

Residential AC-DC conversion requires efficient grid-to-appliance interfaces. While [5] proposes a zero-current switching (ZCS) current-fed full-bridge converter with 15% lower conduction losses via resonant commutation, it suffers from 600 V+ voltage stress on primary devices. In paper [6], the author mitigates this with an active lossless clamp (ALC) (450 V spikes, <5% THD), yet transient load shifts induce DC bus ripples (~2.5%) due to limited control bandwidth. Collectively, [1,2,3,4,5,6] reveal systemic trade-offs: DC-DC designs balance voltage gains vs. parasitic losses, while AC-DC systems face soft-switching benefits versus resonance challenges. Future efforts must integrate modular topologies, wide-bandgap devices, and adaptive controls to address efficiency, stress, and dynamic response limitations.

Although existing multiport power converters have many limitations, they still play a significant role in modern society and provide substantial convenience to users. Hence, advanced study on multiple-port DC-DC converters is critical in modern intelligent energy systems and consuming electronic devices [7].

In recent research focused on multiport power converters, related literature studies are primarily categorized into two groups: isolated and non-isolated types. Owing to the absence of isolation transformers, non-isolated converters exhibit advantages such as simplified design, reduced weight, lower cost, and more compact dimensions. Non-isolated converters employ shared grounding between input and output ports, offering simplified designs and reduced component counts. Common topologies include bidirectional buck-boost, Cuk/SEPIC/ZETA, interleaved, switched capacitor, and cascaded converters. For instance, bidirectional buck-boost converters regulate power flow through duty cycle modulation, operating in buck mode (when input voltage exceeds output) or boost mode (vice versa). Similarly, interleaved converters reduce current ripples by splitting current across multiple phases, enhancing power density [8]. However, non-isolated topologies face inherent limitations: the absence of galvanic isolation increases vulnerability to fault propagation between ports, and high-voltage/current stresses on switches degrade efficiency in high-power applications. Additionally, coupled inductors or cascaded designs introduce control complexity and component redundancy, limiting scalability [9].

Isolated converters, in contrast, utilize high-frequency transformers to decouple input and output ports, ensuring safety and electromagnetic isolation. Key topologies include flyback, dual active bridge (DAB), and multi-winding transformer-based converters. Flyback converters, functioning as isolated buck-boost converters, are constrained to low-power applications (≤150 W) due to high voltage stress on switching devices and the necessity for bulky transformer cores [10]. In contrast, DAB converters excel in high-power scenarios (>2 kW) by leveraging phase-shift control between dual active bridges to regulate bidirectional power flow [11]. To achieve high-power density and soft-switching capabilities, their control complexity escalates with circulating currents, leakage inductance effects, and the need for precise phase-shift modulation. Multi-winding transformer-based converters further integrate multiple ports but struggle with independent output regulation due to magnetic coupling between windings, necessitating advanced decoupling algorithms to mitigate cross-regulation [12,13].

Comparative analyses reveal trade-offs between these categories. Non-isolated converters exhibit higher efficiency and lower costs for low-power applications but lack fault tolerance and voltage flexibility [14]. Isolated converters, though bulkier and costlier, provide superior voltage scalability and safety for grid-connected systems [15]. Challenges persist in both domains: non-isolated designs grapple with efficiency degradation at high duty cycles, while isolated variants face switching loss minimization and transformer optimization hurdles [16]. Innovations such as soft-switching techniques (ZVS/ZCS) and modular multiport architectures are being explored to address these limitations, aiming to enhance power density, efficiency, and controllability in hybrid energy systems [17].

DC-DC converters play a pivotal role in renewable energy integration and power management systems [18], with diverse topologies addressing specific requirements while exhibiting inherent limitations. Non-isolated topologies such as SEPIC, Cuk, and Zeta converters offer voltage gain flexibility but face challenges including component complexity, high voltage stress on switches, and efficiency trade-offs. For instance, SEPIC converters require multiple inductors and capacitors, increasing system footprint and cost, while Cuk converters exhibit polarity inversion and elevated switching losses. Coupled-inductor-based designs like Z-source converters achieve moderate voltage gain with reduced duty cycle dependence [19], yet they suffer from leakage inductance effects and limited scalability for multiport applications. Multi-phase interleaved converters demonstrate reduced input current ripple, but their high device count (e.g., 27 components in six-phase configurations) and complex control algorithms hinder cost-effectiveness. Recent advancements in three-port converters enable flexible energy exchange in microgrids, though their reliance on multi-switch architectures introduces control coupling challenges and switching loss accumulation [20]. While voltage multiplier cells and switched-capacitor techniques achieve ultra-high gains (>10×), they often require extensive passive components and suffer from capacitor voltage imbalance issues. Boost-derived topologies remain prevalent in photovoltaic systems due to their structural simplicity, yet conventional implementations struggle with extreme duty cycle requirements (>0.75) that exacerbate switching losses and electromagnetic interference [21]. These limitations highlight the need for innovative single-inductor architectures that balance voltage gain, component count, and control simplicity—a gap addressed by advanced boost-based designs through topological optimization and multi-output integration. Therefore, a multiport boost converter with a single inductor and fully independently controllable operation is demanded in distributed power storage and consumption systems.

In recent advancements in DC-DC converter technology, the Single-Inductor Multi-Output (SIMO) boost converter has emerged as an optimal topology for applications requiring multiple regulated voltage outputs from a single power source [22]. This architecture employs time-multiplexed switching control to power multiple-output channels through a shared magnetic component (single inductor), demonstrating significant advantages in component minimization and system miniaturization [23]. The unified magnetic structure fundamentally simplifies power stage design: by consolidating energy storage and distribution into a single inductive element, it eliminates redundant magnetic components to achieve compact physical footprints, while the centralized energy transfer mechanism inherently reduces magnetic path redundancy for higher power density [24]. This structural consolidation not only enhances spatial efficiency in vertically stacked systems like wearable devices but also drives cost reduction through simplified PCB routing, minimized bill-of-materials, and streamlined manufacturing processes enabled by standardized magnetic component integration. To address inherent challenges such as cross-regulation and dynamic response limitations, SIMO converters have achieved critical technological breakthroughs [25]. The Voltage-Ripple-based Dynamic Freewheeling (VR-DF) control mechanism enhances transient performance through adaptive freewheeling period adjustment based on output voltage ripple characteristics, achieving 92.03% efficiency at 25 kHz switching frequency. The Output-Voltage-Aware Charge Control (OVACC) strategy effectively suppresses cross-regulation in dual-bus architectures serving mixed heavy/light loads via intelligent energy allocation algorithms [26]. Furthermore, state-space modeling integrated with cross-derivative feedback controllers successfully decouples multiple outputs, maintaining ±3% voltage regulation accuracy under 50% load steps across a 2.5–10 V output range [27].

Under the present research on SI-SIMO converters, this paper proposed a novel single-inductor SIMO boost converter topology can be widely used in multiple-output power supply systems with independent voltage control with a single inductor. In this paper, Section 2 analyzes the SI-SIMO boost converter topology with a proposed modulation scheme. In Section 3, the paper derives the differential equations governing inductor current and capacitor voltage under different switching states while accounting for the influence of various parasitic parameters, thereby establishing a nonlinear dynamic model. The nonlinear dynamic model, resistive network model, and small-signal model of the circuit are proposed in Section 4, with the critical inductance value derived from boundary condition analysis. Section 5 focuses on the implementation and comparative analysis of the proposed SI-SIMO boost converter through experiment studies; finally, the output responses of the three circuit models are comparatively analyzed under identical step-input conditions. This paper is finally summarized in the Conclusion.

2. SI-SIMO Boost Converter

2.1. Topology

Derived from basic boost DC-DC converter, a single-inductor single-input multiple-output (SI-SIMO) DCDC converter is shown in Figure 1. Different from the traditional boost converter, the output stage is divided into three ports by separate unidirectional switches, which are composed of a MOSFET and a diode. The inductor discharge interval is divided into three by switching on Q₁~Q₃ sequentially. Switch Q₀ is modulated to charge the inductor, resulting in the overall power regulation in the circuit.

Each output port is a voltage source represented by an RC circuit. The equivalent load resistor varies dependently in variable load conditions. This topology requires only one inductor to feed current to three outputs by adjusting the turning-on intervals for each production.

In practical experimental circuits, real-world electronic devices inherently require finite time intervals to transition between on and off states. In voltage source inverters, to prevent shoot-through resulting from simultaneous conduction of Q₀ and Q₁, a dead-time interval is typically incorporated into their respective PWM control signals. This dead-time implementation ensures a brief period where both switches remain in the off state following Q₀’s turn-off and preceding Q₁’s activation. However, this protection mechanism introduces a critical operational challenge. As derived from the fundamental voltage–current relationship of inductors $L{\displaystyle \frac{di}{dt}}=V$, the abrupt cessation of inductor current during dead-time intervals induces significant voltage spikes across the inductive load. Such transient overvoltage phenomena pose substantial risks of component failure, including potential damage to MOSFETs, diodes, and associated circuit elements.

To mitigate this hazardous condition, a transient voltage suppression (TVS) diode is strategically integrated into the circuit topology. This protective device functions by clamping excessive voltages during transient events, thereby maintaining operational voltage levels within safe thresholds and safeguarding sensitive components from overvoltage-induced degradation.

2.2. Modulation Scheme

There are two types of carrier waveforms commonly employed, the sawtooth carrier and the triangular carrier, both utilized for generating PWM signals. The sawtooth carrier waveform linearly ascends from an initial value to a maximum before rapidly resetting, repeating cyclically. As shown in Figure 2a, during the generation of the PWM signal, the modulation signals m₁, m₂, m₃ are compared with the sawtooth carrier via a comparator. When the amplitude of the modulation signal exceeds that of the carrier, a high-level output is produced; conversely, a low-level output is generated, thereby forming an initial PWM signal with single-edge modulation (x₁, x₂, x₃).

To modify rising edge-aligned logic signals to sequential PWMs logic, x₁ corresponds to PWM0 directly, while PWM1 is generated from the AND logic of x₁ inversion and x₂. With the same method, PWM2 can be generated consecutively. The whole process and logic circuit used for this generation is shown in Figure 2c. Generally, this logic used for sequential PWMs can be modeled (1). The PWM signals shown in arrows is used to drive the switches with gate driver IC logically.

$${\mathrm{PWM}}_{\mathrm{k}}={\bar{x}}_k\wedge x_{k+1},\mathrm{Where}:x_k=\left\{\begin{array}{c}1m_k>c\left(t\right)\\ 0m_k<c\left(t\right)\end{array}\right.$$

(1)

where c(t) is the ramp value of the sawtooth waveform carrier, which is implemented as a digital counter in the microprocessor.

The triangular carrier waveform, on the other hand, linearly rises from an initial value to a maximum and then descends back to the initial value periodically. The process of generating PWM signals with the triangular carrier is analogous to that of the sawtooth pattern. However, due to the symmetry of the triangular waveform, two edges are produced within each cycle, enabling double-edge modulation (named the centrally aligned mode in the digital controller). While PWM signals generated by the sawtooth carrier are simpler to implement, they exhibit higher harmonic content. In contrast, PWM signals generated by the triangular carrier contain fewer harmonics and offer smoother output, making them suitable for high-performance applications.

2.3. Overlap PWM Logic to Avoid Overvoltage

Alternatively, the overvoltage issue discussed in Section 2.1 (Topology) can be resolved through pulse–width modulation (PWM) signal adjustment by introducing controlled overlap time intervals in the gate drive signals of adjacent MOSFETs, as shown in Figure 3b. A brief interval is intentionally allocated to allow simultaneous conduction of both devices. This overlap ensures the smoothness of the inductor current, thereby eliminating abrupt current spikes that induce overvoltage transients. Additionally, this strategy reduces system costs by minimizing reliance on voltage-clamping components (e.g., TVS diodes) and mitigates power losses associated with voltage regulation, ultimately enhancing overall conversion efficiency.

It should be noted that the overvoltage can also be eliminated by removing the active switch from any of the output branches. In this way, the inductor current has a backup path to delivering power to the highest voltage output. However, that requires the specific output always be the highest voltage. Otherwise, the other two outputs cannot be boosted higher than that since the branch cannot be actively disconnected from the inductor. In this paper, for its specific application requirements, the output voltage varies for different load conditions. Hence, we keep the flexibility of the circuit output and consider the overvoltage in this circumstance, as well as the protection solution.

3. Switching-State Analysis

From the introduction of the SI-SIMO topology in Section 2, a switching-state analysis and circuit model derivation are presented in this part. This result determines the dynamic performance and evaluation of circuit design regarding the steady state and transient process In practical circuit design, due to the existence of various parasitic parameters in physical components, failure to account for their influences would result in significant discrepancies between experiment models and actual circuit implementations. Therefore, as shown in Figure 4, the following refinements are implemented in the circuit modeling:

• Inductor model enhancement: The conventional inductor is replaced with a composite structure comprising an inductor in series with a resistor. This modification explicitly accounts for the parasitic resistance inherent in practical inductors.
• MOSFET parasitic resistance incorporation: The MOSFET device is represented by an equivalent model incorporating series resistance, graphically depicted as a switch–resistor combination. This refinement quantitatively captures the influence of the MOSFET’s on-state resistance.
• Diode forward voltage characterization: The ideal diode model is substituted with a unidirectional voltage source element. This substitution effectively models the non-negligible forward voltage drop characteristic of semiconductor diodes during conduction.

With the sequential PWM signals, the proposed SI-SIMO boost circuit has four switching states, shown in Figure 5. The inductor and output capacitors satisfy differential equations for its instant dynamic characteristic.

3.1. Switching-State 0 (Figure 5a SS0)

In this switching-state condition, switch S₀ is closed (the corresponding MOSFET is turned on, and the rest of them are turned off). As shown in Figure 5a, the inductor is charged by the input voltage, and the three outputs are RC circuits with a specific initial voltage on each capacitor. Explicitly,

$$L{\displaystyle \frac{d{i}_L}{dt}}=v_{in}-i_L{R}_s$$

(2)

$$C_k{\displaystyle \frac{d{\nu }_k}{dt}}=-{\displaystyle \frac{{\nu }_k}{R_k}},k=1,2,3.$$

(3)

where R_s = R_L + R_on; explicitly, R_L is the equivalent series resistance in the inductor and input loop, and Ron is the MOSFET on-state resistance. C_x are output capacitor values and u_x are output voltage values with an equivalent load resistor R_x, while R_on is the on-state resistance of both diodes and MOSFETs. This switching state continues for a time interval determined by the switching period T_s and modulation index value m₁. We define a duty cycle d₀ for convenience.

3.2. Switching-State 1 (Figure 5b SS1)

Following the previous SS0, in this SS1, switch S₁ is closed. As shown in Figure 5b, the inductor releases its stored energy, and the current flows through the MOSFET Q₁ and diode D₁ to the V₁ port. The three outputs are RC circuits. Explicitly,

$$L{\displaystyle \frac{d{i}_L}{dt}}=v_{in}-V_f-i_L{R}_s-v_1$$

(4)

$$C_x{\displaystyle \frac{d{\nu }_x}{dt}}=-{\displaystyle \frac{{\nu }_x}{R_x}}x=2,3$$

(5)

$$C_1{\displaystyle \frac{d{v}_1}{dt}}=-{\displaystyle \frac{v_1}{R_1}}+i_L$$

(6)

where v_f characterizes the conduction voltage of diodes in their on-state.

3.3. Switching State 2 (Figure 5c SS2)

Similar to SS1, the second output port V₂ is tied to the inductor during the next interval; the inductor and capacitor satisfy the equation below:

$$L{\displaystyle \frac{d{i}_L}{dt}}=v_{in}-v_f-i_L\cdot R_s-v_2$$

(7)

$$C_x{\displaystyle \frac{d{\nu }_x}{dt}}=-{\displaystyle \frac{{\nu }_x}{R_x}}x=1,3$$

(8)

$$C_2{\displaystyle \frac{d{v}_2}{dt}}=-{\displaystyle \frac{u_2}{R_2}}+i_L$$

(9)

3.4. Switching State 3 (Figure 5d SS3)

In the last switching state, the third output V₃ is tied to inductor with corresponding differential Equations in (10)–(12):

$$L{\displaystyle \frac{d{i}_L}{dt}}=v_{in}-v_f-i_L\cdot R_s-v_3$$

(10)

$$C_x{\displaystyle \frac{d{v}_x}{dt}}=-{\displaystyle \frac{v_x}{R_x}}x=1,2$$

(11)

$$C_1{\displaystyle \frac{d{v}_3}{dt}}=-{\displaystyle \frac{v_3}{R_3}}+i_L$$

(12)

The four switching-state intervals are repetitively applied in the circuit by adjusting the PWM duty cycles. It should be mentioned that the total switching period consists of these four states. Their duration is determined by the other three in the CCM conditions. Hence, the four duty cycles are related by (13).

$${\displaystyle \sum _{k=0}^3{d}_k}=1$$

(13)

The switching-state analysis (SS0-SS3) establishes the SI-SIMO converter’s operational dynamics, with each state governing energy transfer via sequential PWM. This framework enables steady-state and small-signal modeling in Section 4, critical for optimizing design and control performance under varying load conditions.

4. SIMO Boost Modeling and Analysis

Different mathematical models are necessary to completely understand the SI-SIMO boost converter behavior. These models help evaluate the converter’s performance regarding dynamic process and steady-state parameters.

4.1. Complete Nonlinear Dynamic Model

By averaging the four switching states with corresponding duty cycles, the inductor current and output capacitor voltage can be derived over a switching period, i.e.,

$$L{\displaystyle \frac{d{i}_L}{dt}}=v_{in}-i_L{R}_s-{\displaystyle \sum _{k=1}^3{d}_k}\left(v_k+V_f\right)$$

(14)

$$C_k{\displaystyle \frac{d{\nu }_k}{dt}}=-{\displaystyle \frac{{\nu }_k}{R_k}}+d_k{i}_{L}k=1,2,3$$

(15)

This approach is valid due to the time-scale separation between the circuit’s slow dynamics (e.g., capacitor voltage/inductor current variations) and the high switching frequency. Specifically, the dynamic processes evolve at millisecond-level timescales, while the switching actions induce microsecond-scale ripple. Such separation allows the high-frequency ripple to be neglected without compromising the accuracy of low-frequency system behavior. Consequently, the state variables can be approximated as quasi-static within a switching cycle, enabling the averaged model to retain essential dynamics for stability analysis and controller design. Moreover, this approximation avoids computationally intensive switching details while preserving predictive accuracy for both steady-state and transient responses.

With the averaging modeling approach explained above, the nonlinear circuit model with consideration of some circuit parameters can be drawn as a signal flow diagram, shown in Figure 6a. Since this dynamic model is represented in differential equations with nonlinear properties, an integration block is used for circuit-state transferring instead of the s-domain diagram as a linear system representation. Explicitly, the inductor current is a first-order system driven by the average voltage across the inductor. On the other hand, the three output voltages are driven by the inductor current and the related duty cycle by which the output capacitor is charged. It can be simplified into a first-order linear system if we consider the second term in (15) as an average input. However, due to the three outputs sharing the same inductor current multiplied by related duty cycles, any disturbance in inductor current must cause output voltage fluctuation. In other words, the three outputs are indirectly coupled through the inductor current. The output voltage coupling problem can also be seen in Figure 6a, in which the inductor current drives three output voltage with related interval durations; as a feedback effect, any dynamic process on output will change the inductor current reversely and will be coupled to the other output.

4.2. Steady-State Equivalent Circuit

Considering a steady state, the inductor and capacitors are balanced over a switching period. In other words, there is no incremental, on-average inductor current and capacitor voltage in (14) and (15). Consequently, the left-hand side is zero, i.e.,

$$0=V_{in}-V_f-I_L{R}_s-{\displaystyle \sum _{k=1}^3{D}_k}{V}_k+D_0{V}_f$$

(16)

$$0=-{\displaystyle \frac{V_k}{R_k}}+D_k{I}_{L}k=1,2,3$$

(17)

where V_in and V_k represent the average input voltage and the average output voltage in the steady state, respectively; the same applies to D_x and I_L rather than d_x and i_L.

To facilitate the numerical experiment, the state variables in Equations (16) and (17) are rearranged on the left-hand side and expressed in matrix form, thereby yielding the matrix equation: MX = P. The matrices M and P are explicitly formulated in the following equations:

$$M=\left[\begin{array}{cccc}{R}_s& D_1& D_2& D_3\\ D_1& -{\displaystyle \frac{1}{R_1}}& 0& 0\\ D_2& 0& -{\displaystyle \frac{1}{R_2}}& 0\\ D_3& 0& 0& -{\displaystyle \frac{1}{R_3}}\end{array}\right]$$

$$P={\left[V_{in}-V_f+D_0{V}_f,0,0,0\right]}^T$$

Subsequently, the state variable matrix X can be obtained through matrix inversion:

$$X=M^{-1}P$$

To systematically investigate the steady-state characteristics of the circuit, as shown in Figure 6b, the circuit averaging method is employed to derive an equivalent resistive network composed of power sources, controlled sources, and linear resistors. As indicated by Equation (8), the three output ports are mathematically represented by voltage-controlled voltage sources (VCVSs) regulated by the output voltages and proportionally scaled by their corresponding duty ratios, while the inductor’s current delivery behavior under specific switching states is equivalently modeled as current-controlled current sources (CCCSs) governed by the inductor current and linearly modulated by the associated duty cycles. In this framework, RL explicitly quantifies the intrinsic resistance of the inductor, whereas V_f and D₀V_f characterize the forward voltage drop of the diode. This averaged model, rigorously validated under continuous conduction mode (CCM) conditions, captures the steady-state power transfer dynamics with high fidelity, explicitly encapsulating both conduction and switching losses inherent to the circuit components. By correlating simulated power dissipation metrics—such as inductor copper loss and diode forward loss—with theoretical predictions, the model enables precise verification of component parameter selection accuracy while providing a diagnostic basis for circuit health monitoring through anomalies in duty ratio proportionality coefficients or resistance deviations caused by aging or fault conditions.

From Equations (16) and (17), the average inductor current in steady state can be derived as (18). At the same time, the output voltage is determined by load resistance and duty cycles, as well as inductor current in the steady-state condition.

$$I_L={\displaystyle \frac{V_{in}-V_f+D_0{V}_f}{{\displaystyle \sum _{k=1}^3{D}_k^2{R}_k}+R_s}}$$

(18)

$$V_k=R_k{D}_k{I}_L,k=1,2,3.$$

(19)

Additionally, the coupling effect is also observed in an average circuit model, which is proved in matrix M as well as Figure 6b. This results implies the SI-SIMO converter challenge to the control and closed-loop regulation, especially during transient processes.

4.3. Small-Signal Model

By considering the small-signal perturbation, the circuit states can be represented by $x=X+\widehat{x}$, where $x={\left[v_{in},i_L,v_1,v_2,v_2\right]}^T$ with their capital and small-signal counterparts. With the small-signal modeling approach in [28,29,30], the SI-SIMO converter small-signal model can be derived into (20) and (21):

$$L{\displaystyle \frac{d{\widehat{i}}_L}{dt}}={\widehat{v}}_{in}-{\widehat{i}}_L{R}_s-{\displaystyle \sum _{k=1}^3\left[\left.D_k{\widehat{v}}_k+{\widehat{d}}_k\left(V_k+V_f\right)\right]\right.}$$

(20)

$$C_k{\displaystyle \frac{d{\widehat{\nu }}_k}{dt}}=-{\displaystyle \frac{{\widehat{\nu }}_k}{R_k}}+D_k{\widehat{i}}_L+I_L{\widehat{d}}_{k}k=1,2,3$$

(21)

Equations (20) and (21) can be formalized into state-space Equation (22) in a matrix:

$$\left\{\begin{array}{l}\dot{x}=Ax+Bu\hfill \\ y=Cx+Du\hfill \end{array}\right.$$

(22)

In (22), the input vector is selected as $u={\left[{\widehat{v}}_{in},{\widehat{d}}_1,{\widehat{d}}_2,{\widehat{d}}_3\right]}^T$, the state variables is: as $x={\left[{\widehat{i}}_L,{\widehat{v}}_1,{\widehat{v}}_2,{\widehat{v}}_3\right]}^T$, and output as $y={\left[{\widehat{v}}_1,{\widehat{v}}_2,{\widehat{v}}_3\right]}^T$, while the coefficient matrices are derived as below:

$$\begin{gathered} A=\left[\begin{array}{cccc}-{\displaystyle \frac{R_s}{L}}& -{\displaystyle \frac{D_1}{L}}& -{\displaystyle \frac{D_2}{L}}& -{\displaystyle \frac{D_3}{L}}\\ {\displaystyle \frac{D_1}{C_1}}& -{\displaystyle \frac{1}{R_1{C}_1}}& 0& 0\\ {\displaystyle \frac{D_2}{C_2}}& 0& -{\displaystyle \frac{1}{R_2{C}_2}}& 0\\ {\displaystyle \frac{D_3}{C_3}}& 0& 0& -{\displaystyle \frac{1}{R_3{C}_3}}\end{array}\right] \\ B=\left[\begin{array}{cccc}{\displaystyle \frac{1}{L}}& -{\displaystyle \frac{V_1+V_f}{L}}& -{\displaystyle \frac{V_2+V_f}{L}}& -{\displaystyle \frac{V_3+V_f}{L}}\\ 0& {\displaystyle \frac{I_L}{C_1}}& 0& 0\\ 0& 0& {\displaystyle \frac{I_L}{C_2}}& 0\\ 0& 0& 0& {\displaystyle \frac{I_L}{C_3}}\end{array}\right] \\ C=\left[\begin{array}{cccc}0& 1& 0& 0\\ 0& 0& 1& 0\\ 0& 0& 0& 1\end{array}\right] \\ D=0 \end{gathered}$$

According to the small-signal modeling process, as shown in Figure 7, the perturbation response in the SIMO converter is represented as a linear, multi-input multi-output (MIMO) system, as well as coupling terms between state variables. Small-signal circuit models are widely employed to analyze nonlinear electronic devices under small perturbations around a steady-state operating point. Their primary advantage lies in simplifying circuit behavior through linear approximation, enabling efficient frequency-domain analysis using linear network theory while neglecting high-order nonlinear terms. These models facilitate performance prediction for amplifiers and oscillators through parameters like gain and impedance. However, their validity is restricted to signal amplitudes where nonlinear effects remain negligible, and they cannot predict large-signal distortion or temperature-dependent parameter variations. Additionally, model accuracy critically depends on proper bias condition characterization.

4.4. CCM/DCM Analysis

To effectively evaluate circuit performance and guide converter design, CCM/DCM analysis is required. Since the parasitic R_s and V_f in the circuit are negligible compared to the port voltage and load resistance, they are ignored in this section for simplicity.

In the continuous conduction mode (CCM), as shown in Figure 8, the inductor current of the circuit remains above zero throughout the entire switching cycle, ensuring a continuous flow of energy. The CCM operation is characterized by two primary phases: Phase 1, the inductor charging phase (where switch S₀ is turned on, allowing the inductor to store energy from the input source), and Phase 2, the inductor discharging phase (where switch S₀ is turned off, and the stored energy is transferred to the output branches corresponding to the different switching states, maintaining a steady current flow).

In the discontinuous conduction mode (DCM), the inductor current of the circuit rises during the SS0 state of each switching cycle, decreases during the SS1 and SS2 states, and drops to zero during the SS3 state, remaining at zero until the next cycle begins. As shown in Figure 8, the DCM operation is divided into three phases. Note that in the DCM condition, in Phase 3, the inductor current crosses zero and reaches negative values. This is assumed for illustration of the DCM/CCM investigation. In the actual converter, regardless of whether in simulation or experiments, the inductor current will stop by the end of Phase 2 in DCM and keep zero until the next switching cycle.

4.4.1. CCM Criteria

In the first method, as shown in Figure 8, the current ripple during the rising segment is described as ΔiL^rise. After that, the current ripple during the falling segment is ΔiL^fall, which is an accumulated decrease driven by inductor voltage. From Equations (4), (7), and (19), the current ripple can be linearly derived:

$$\mathsf{\Delta }{i}_L^{rise}={\displaystyle \frac{1}{L}}{D}_0{T}_s{V}_{in}$$

(23)

$$\mathsf{\Delta }{i}_L^{fall}=V_{in}{\displaystyle \frac{T_s}{L}}{\displaystyle \sum _{k=1,2,3}{D}_k\left(1-g_k\right)}$$

(24)

where g_k represent the gain of the corresponding output port. It is assumed that the inductor current continues decreasing below zero crossing (although this does not actually happen due to the presence of the diode).

Based on the definitions of CCM and DCM mentioned above, the circuit operates in CCM if it satisfies the equation

$$\mathsf{\Delta }{i}_L^{rise}+\mathsf{\Delta }{i}_L^{fall}=0$$

(25)

Otherwise, the summation in (25) must be negative, and it operates in DCM, i.e.,

$$\mathsf{\Delta }{i}_L^{rise}+\mathsf{\Delta }{i}_L^{fall}<0$$

(26)

To explicitly derive the criteria of the inductor current conduction mode, substitute (23) and (24) into (25):

$$0=V_{in}{\displaystyle \frac{T_s}{L}}{\displaystyle \sum }_{k=0,1,2,3}{D}_k\left(1-g_k\right).g_0=0$$

(27)

Since the Vin, Ts, and L are always positive, they do not affect whether the equation equals zero. Therefore, (27) can be simplified and abstracted as λ:

$$\lambda ={\displaystyle \sum _{k=0,1,2,3}{D}_k\left(1-g_k\right)}.\hspace{0.33em}{g}_0=0$$

(28)

Accordingly, if λ = 0, the circuit will operate in CCM; otherwise, λ < 0, and the circuit operates in DCM.

4.4.2. Critical Inductor Value

Before the converter prototyping, the inductor should be carefully designed. Hence, we find the critical inductor value by which the circuit is operated at critical points between CCM and DCM with rated parameters.

Approximately, the input power equals the output power, that is, the left-hand side in (29) equals its right-hand side:

$$V_{in}{I}_L\approx {\displaystyle \sum _{k=1,2,3}\frac{V_k^2}{R_k}}$$

(29)

where I_L is the average inductor current. Assuming the converter has extreme efficiency, the average inductor current can be expressed in (30):

$$I_L={\displaystyle \frac{1}{V_{in}}}{\displaystyle \sum _{k=1,2,3}\frac{V_k^2}{R_k}}$$

(30)

In the critical condition, the average inductor current equals half of the peak-to-peak inductor current, as shown in Figure 8. From the inductor current ripple analysis, as aforementioned, in CCM, the following formula is satisfied:

$$I_L>0.5\left|\mathsf{\Delta }{i}_L^{rise}\right|=0.5\left|\mathsf{\Delta }{i}_L^{fall}\right|$$

(31)

Substitute (30) and (23), and the critical inductor value can be derived in (32):

$$L_c={\displaystyle \frac{V_{in}^2{T}_s{D}_0}{2{\displaystyle \sum _{k=1,2,3}\frac{V_k^2}{R_k}}}}$$

(32)

This section presents a systematic modeling approach and theoretical derivation to establish the analytical expression (Equation (32)) for the critical inductance value in the SI-SIMO boost converter, based on the principle of energy conservation and inductor current ripple characteristics. The derivation process comprehensively incorporates the dynamic relationships among duty cycle, load parameters, and input voltage, thereby quantitatively characterizing the correlation between critical inductance and circuit parameters.

5. Simulation and Experimental Validation

5.1. SI_SIMO Circuit Validation

A switching circuit model is first built in PSIM to validate the topology design and modulation scheme proposed in this paper. In the open-loop control condition, steady-state performance is tested in the PSIM experiment model.

5.1.1. Circuit Model and Experiment Parameters

In this work, an open-loop controlled SI-SIMO DC-DC converter is designed and implemented in the PSIM experiment environment, as illustrated in Figure 9. The circuit features three independent output ports, each capable of delivering distinct output voltages. The core component of the design is a 68 μH inductor, which serves as the primary element for energy storage and transfer. The switching frequency is set to 50 kHz to ensure high-efficiency energy conversion while optimizing the size of the components. To enable three outputs, the output terminal of the inductor is connected to three independent rectifier RC filter branches.

5.1.2. Modulation Logic and PWM Signal

Since the circuit operates under open-loop control, the output voltages are regulated by adjusting the corresponding PWM duty cycle. In Figure 10, the input modulation values m₁, m₂, m₃ are compared with the triangle carrier, which subsequently generates centrally aligned PWM signals. To output the proper sequential switching signals for MOSFETs, the logic circuit is implemented in a specific mode. Sequential PWM signals for switching action are shown in Figure 10b. Note that the triangle carrier generates the symmetrical PWM sequence, and the average current for the four switching states are the same, which improves the accuracy in the derived.

5.1.3. CCM/DCM Simulation

The inductor current waveforms for CCM and DCM are shown in Figure 11a and 11b, respectively. Figure 11a demonstrates CCM operation, where the inductor current remains above zero, ensuring continuous energy transfer. In contrast, Figure 11b illustrates DCM operation, with the inductor current dropping to zero, reflecting intermittent energy transfer under light loads. These results validate the circuit’s modulation principles in CCM and adaptability in DCM.

5.1.4. Critical Inductor Value Simulation

Under the conditions where the duty cycles of the PWM signals for the MOSFETs at each output port are 0.25, 0.2, and 0.2 and the parallel resistance at the respective output ports are 80 Ω, 100 Ω, and 75 Ω, the critical inductance value for the current circuit parameters is calculated in (32) to be 42 μH. By setting the inductor value as 42 μH, as well as the duty cycles and resistor values, the simulated inductor current (I_L) waveform is shown in Figure 12. This result indicates a correction in the theoretical steady-state derivation and critical mode analysis.

5.1.5. Steady-State Average Test

In

Table 1. Open-loop output voltage comparison.

RX Vx DX	[100 100 100]	[75 80 100]	[60 90 80]
[0.2 0.3 0.4]	[18.70 12.47 15.58]	[12.47 15.58 18.70]	[21.05 16.84 16.84]
	{20.03 12.98 14.91}	{13.84 15.60 18.28}	{22.29 17.01 16.97}
[0.2 0.25 0.3]	[16.67 12.85 18.52]	[10.59 14.12 21.18]	[18.93 16.15 20.19]
	{16.33 11.59 18.04}	{11.10 14.14 20.62}	{18.64 15.87 19.76}
[0.25 0.2 0.2]	[15.43 15.43 17.14]	[9.458 17.73 18.92]	[17.06 20.47 18.20]
	{15.12 15.04 16.73}	{9.686 17.49 18.53}	{16.74 20.05 17.82}

, to verify the steady-state circuit model derived in Section 3, with a specific duty cycle and load resistance, the calculated and simulated output voltage values are compared. For each test condition (the duty cycle and output resistance combination), the upper group value is the calculated output voltage by (19), and the lower group is simulated in a steady state. Considering the diode and switch resistance in the experiment model, the variation between the calculated value and simulated value is acceptable and matches well.

5.2. SI-SIMO Dynamic Modeling Comparison

To validate the SI-SIMO boost converter modeling accuracy, a nonlinear model and a small-signal model at the steady-state operation point are built in MATLAB/Simulink 2024a. By introducing small input perturbations, the state variables’ transient responses are compared between the PSIM switching circuit model and the Simulink model. In Figure 13, the circuit variables are tested with the input voltage step of 12–13 V. It is observed that the inductor current and output voltages are increased with transient dynamics. Moreover, the output voltages are the same proportion since the duty cycle and load resistance are constant in this test condition. In addition, the original nonlinear differential equation model is more accurate than the small-signal model approximation at the static operation point. It is the fact that the original dynamic model includes the all-necessary state variable coupling terms in the equation, whereas the small-signal model is a linear approximation with state-space equations.

Similarly, the transient response is also investigated with perturbation at duty cycle inputs d₁, d₂, and d₃, shown in Figure 14, Figure 15, and Figure 16, respectively. It is worth noting that the small duty cycle perturbation introduced will affect the d₀ value to keep the other two duty cycles constant in the derived model and to ensure the entire switching period satisfies d₀ + d₁ + d₂ + d₃ = 1. Furthermore, the input duty cycle changes the output power allocation, and the output voltage shows increasing and decreasing between different ports.

The dynamic model experiment on the dynamic and steady-state comparison provides the circuit evaluation before implementation, as well as controller design for high-performance power supply systems. Nonlinear model response and small-signal model approximation help evaluate the linear design margin under certain requirements.

5.3. Experiment

To validate the proposed SI-SIMO boost converter, an evaluation board with an input of 12 V is designed, shown in Figure 17. The single inductor is tied to switch S0 and three unidirectional switches S1~S3, which comprise a diode series with the MOSFET. Sequential PWM logic is generated by and decoded by IC 74HC128. A bootstrap gate driver IC DRV8300D is used to drive the four switches for low-cost consideration. In Figure 18, the three output voltages are monitored in scope. With proper duty cycle step input, the output voltages are changed from one operation point to another, demonstrating the separated output control capability. It is also observed that the three outputs are coupled during the transient dynamics. This result is firmly consistent with the theoretical analysis in this paper and validates the simulation results accordingly. Future research will focus on its closed-loop control and decoupled regulation for its high-performance applications.

6. Discussion

The proposed SI-SIMO boost converter topology and its analytical framework resolve longstanding trade-offs between component complexity, control flexibility, and efficiency in multi-output DC-DC systems. By integrating sequential PWM modulation with a single-inductor architecture, this work achieves independent voltage regulation across multiple outputs—reducing system footprint and manufacturing costs. This advancement addresses critical needs for compact, cost-effective power management in portable electronics and renewable microgrids.

Theoretical contributions include CCM/DCM boundary conditions and a critical inductance formula, providing quantitative tools to suppress voltage ripple and optimize inductor size. A comprehensive modeling framework (nonlinear dynamics, steady-state circuits, and state-space formulation in Equation (12)) quantifies cross-regulation effects.

Practically, TVS diodes and overlapping PWM enhance reliability without snubber-related efficiency losses. The 50 kHz switching frequency supports compatibility with GaN/SiC devices for future efficiency gains. While single-inductor current sharing limits scalability beyond three outputs (applicable to <500 W systems), this aligns with IoT and residential PV auxiliary demands.

7. Conclusions

To fill the gap in distributed power supply in industry applications with existing SISO DC-DC converters, this paper analyzes an SI-SIMO DC-DC converter from a switching-state and modulation strategy perspective. A sequential PWM signal generation logic is proposed. The average circuit model is derived based on switching state analysis. Its steady-state model is discussed, and the CCM/DCM condition is presented. The critical inductor value is derived analytically. With these fundamental analyses, the complete circuit modeling process is derived from a nonlinear dynamic model to a small-signal approximation at the steady-state operation point. An experimental model in PSIM and MATLAB Simulink shows that the proposed SI-SIMO boost converter can independently regulate the output voltage with proper duty cycle inputs with a sequence pulse modulation method. These contribute to prototyping design and circuit performance evaluation. Experiment results validate the proposed modulation scheme and verify the theoretical analysis in different test conditions. From this work, advanced control and implementation solutions can be further investigated in future research.