A Low Inrush Current Pre-Charging Strategy of M3C with Improved Nearest Level Modulation

Abstract

The modular multilevel matrix converter (M3C) can perform AC/AC conversion directly. However, M3C operation often requires a pre-charging process, which can be challenging due to the need for fast pre-charging with low inrush current. To address the issue, a closed-loop fast pre-charging strategy is proposed that utilizes an improved nearest level modulation (NLM) based on a quick-sorting algorithm for M3C. By improving the current limiting resistor and the number of Sub-Modules (SMs) inserted into the NLM, we achieve a reduction in inrush current when connected to the grid, and unlock the control algorithm, respectively. This paper presents the relationship between the current-limiting resistor, the pre-charging current, and the pre-charging time. Reactive power compensation is applied on the AC grid during the pre-charging process to ensure stability. Furthermore, the balanced control of capacitor voltage is employed to achieve synchronized and coordinated growth of capacitor voltages in SMs using a quick-sorting algorithm based on NLM. The simulation and experimental results demonstrate the effectiveness of this approach, making it suitable for M3C with a high number of SMs.

1. Introduction

The Modular Multilevel Matrix Converter (M3C) enables direct AC-to-AC frequency conversion without requiring a DC-link, making it an attractive technology due to its modularity, scalability, reliability, and conversion efficiency [1]. Most studies on M3C assume that the initial SM capacitor voltages are at their rated value, whereas reaching the rated value usually requires a pre-charging stage [2,3,4]. This aspect is crucial, as SM capacitors in M3C start with zero voltage, and the system’s low equivalent impedance can lead to significant inrush currents, which could stress the IGBTs. Therefore, it becomes essential to charge all SM capacitor voltages in the bridge arms to their rated levels to ensure a safe and reliable charging process [5,6,7,8]. Unlike the Modular Multilevel Converter (MMC), the M3C is a three-input, three-output system that relies solely on the AC side for charging, and algorithms cannot control the IGBTs during the initial charging phase [9]. As a result, M3C pre-charging is divided into two stages: an uncontrolled pre-charging stage, where the system charges through the three-phase input line voltage, and a controlled pre-charging stage.

At the start of M3C pre-charging, the SM capacitors have zero voltage, and both the input and output of the SMs behave like a short circuit, causing significant inrush currents when a high voltage is applied to the bridge arm. To mitigate this, previous studies, such as [10] and [11], suggest using current-limiting resistors in series to reduce the inrush current. Additionally, [12] explores the relationship between the maximum current and the value of the current-limiting resistor. However, while current-limiting resistors effectively reduce inrush currents, the selection of the resistor value also affects the charging time, which has not been fully analysed in the literature.

Various charging strategies have been proposed for MMCs, which can serve as a reference for M3C. Reference [13] proposes an open-loop charging approach by gradually reducing the number of SMs during the controlled pre-charging stage. However, this approach lacks stability and results in longer charging times. In contrast, [14] achieves closed-loop pre-charging in MMC using traditional carrier phase-shifted pulse width modulation (CPS-PWM). Reference [15] suggests grouping SMs and charging them sequentially, though this method also leads to longer charging times. Other methods, such as in [16], employ constant current charging with feedback control, while [17] presents a fast pre-charging method using deadbeat predictive current control, eliminating the need for parameter setting. Furthermore, [18] introduces a semi-controlled pre-charging stage for hybrid sub-modules in MMC, solving the problem of unbalanced charging, which provides new ideas for M3C pre-charging strategies. Among these methods, nearest level modulation (NLM) has gained attention for its ability to improve voltage quality and enhance control in MMCs, especially as the number of SMs or levels increases. However, NLM requires sorting a large amount of data, and traditional algorithms like bubble sort significantly reduce the sorting efficiency, particularly when dealing with a high number of SMs, which can render NLM impractical for large-scale systems [19,20,21,22].

This paper establishes the relationship between the current-limiting resistor, charging current, and charging speed, with the aim of achieving fast pre-charging for M3C without excessive inrush currents. An optimal current-limiting resistor is calculated based on the desired charging time and inrush current limits, effectively shortening the uncontrolled stage of the pre-charging process. Additionally, an improved closed-loop pre-charging method based on NLM is proposed, utilizing a quick-sorting algorithm to efficiently handle the SM capacitor voltages. This method gradually reduces the number of active SMs during the charging process, improving the accuracy in determining the number of SMs, reducing inrush currents during switching, and minimizing voltage fluctuations in the bridge arm capacitors.

Furthermore, the proposed strategy includes reactive current compensation on the input side and implements balance control between the bridge arms and SMs to ensure synchronous and uniform charging across all SMs. When compared with other pre-charging strategies, the NLM-based approach using a quick-sorting algorithm proves to be more efficient in reducing inrush current while handling large data volumes. The effectiveness of the proposed strategy is validated through simulation and experimental results.

This paper is organized as follows. Section II presents the mathematical model of M3C and the method for selecting the current-limiting resistor. Section III discusses traditional pre-charging strategies for M3C, including uncontrolled and controlled pre-charging methods. Section IV introduces the proposed improved NLM pre-charging strategy, comparing bubble sorting and quick-sorting algorithms. Sections V and VI provide the validation of the proposed method through simulation and experimental results. Finally, conclusions are drawn in the last section.

2. Operating Principles and Selection of Current-Limiting Resistors for M3C

2.1. The Mathematical Model of M3C

The M3C bridge topology is shown in Figure 1. The system utilizes three-phase input and three-phase output with nine bridge arms, each having an identical configuration. Each bridge arm consists of N identical submodules (SMs) and an inductor connected in series. In the figure, S₁ and S₂ control the connection of the current-limiting resistor and the three-phase load, respectively. Each module is comprised of four IGBTs, four anti-parallel diodes, and one capacitor. The module is capable of outputting three voltage levels: 0, ±U, which are controlled by T₁~T₄. The module operates in one of four different modes, depending on the driving signals: block mode, charging mode, discharging mode, and bypass mode.

2.2. Selection of Current-Limiting Resistors

To ensure the secure operation of electronic equipment and prevent the inrush current from damaging the M3C system, a current-limiting resistor can be connected in series in the system. However, this will increase the system loss, and, therefore, a trade-off must be made to ensure safe pre-charging of the system by increasing part of the power consumption. The maximum charging current is generated when the AC line voltage reaches its peak for the first time. It can be expressed as follows:

$$\left\{\begin{array}{l}{I}_m={\displaystyle \frac{\sqrt{6}{U}_s}{\sqrt{R_e^2+X_e^2}}}\hfill \\ R_{eq}=2\cdot 3R_l=6R_l\hfill \\ X_{eq}=2{\omega }_s(3L_s+L_b)-{\displaystyle \frac{N}{{\omega }_{s}C}}\hfill \end{array}\right.$$

(1)

where I_m represents the inrush current when powered on, U_s represents the effective value of the input-side phase voltage, R_eq represents the equivalent resistor in the circuit, R_l represents the current-limiting resistor in the circuit, X_eq represents the equivalent reactance, ω_s represents the input-side frequency, and C represents the capacitance of the SMs.

The relationship between the current-limiting resistor and the current can be obtained by rearranging (1) as follows:

$$R_l={\displaystyle \frac{1}{6}}\sqrt{{\displaystyle \frac{6U_s^2}{I_m^2}}-{\left({\omega }_s(6L_s+2L_b)-{\displaystyle \frac{N}{{\omega }_{s}C}}\right)}^2}$$

(2)

Furthermore, the required charging speed is affected by the value of the current-limiting resistor. The cutoff frequency of the circuit can be expressed as follows:

$$f_0={\displaystyle \frac{1}{2\pi \sqrt{L_{eq}{C}_{eq}}}}$$

(3)

When the input frequency of the topology exceeds the cutoff frequency, the charging rate decreases as the capacitors’ voltage continues to increase. The capacitor is deemed fully charged when its voltage reaches 95%. The charging time for the capacitor in a DC RC circuit is calculated as follows:

$$\left\{\begin{array}{l}{v}_c=\sqrt{6}{U}_s(1-e^{-{\displaystyle \frac{t}{\tau }}})\hfill \\ \begin{array}{l}\tau =R_{eq}{C}_{eq}=6R_l{\displaystyle \frac{C}{2N}}={\displaystyle \frac{3R_{l}C}{N}}\\ t=3R_{eq}{C}_{eq}=9{\displaystyle \frac{R_{l}C}{N}}\end{array}\hfill \end{array}\right.$$

(4)

However, when charging all SM capacitors in full-bridges with AC voltage, the capacitor is consistently charged in the forward direction. The charging time is affected by a fixed value k₀ when the number of SMs, the capacitor voltage, and the current-limiting resistor are fixed. Therefore, the charging time for all SM capacitors in the bridge with AC voltage can be expressed as follows:

$$t=9k_0{\displaystyle \frac{R_{l}C}{N}}$$

(5)

When the ratio of the input voltage to the CCV at the completion of charging remains constant, the charging time is unaffected by the input voltage. After analyzing a large dataset, we can express the fitting equation as follows:

$$t={\displaystyle \frac{(14.2+12R_l)C}{N}}+0.004$$

(6)

Bring (5) into (6) as follows:

$$k_0={\displaystyle \frac{N}{2250R_{l}C}}+{\displaystyle \frac{71}{45R_l}}+{\displaystyle \frac{4}{3}}$$

(7)

Another limitation of the current-limiting resistors can be obtained as follows:

$$R_l={\displaystyle \frac{(t-0.004)N}{12C}}-{\displaystyle \frac{71}{60}}$$

(8)

In summary, the equation for obtaining the current-limiting resistor is as follows:

$$\left\{\begin{array}{l}{R}_l={\displaystyle \frac{1}{6}}\sqrt{{\displaystyle \frac{6U_s^2}{I_m^2}}-{\left({\omega }_s(6L_s+2L_b)-{\displaystyle \frac{N}{{\omega }_{s}C}}\right)}^2}\hfill \\ R_l={\displaystyle \frac{(t-0.004)N}{12C}}-{\displaystyle \frac{71}{60}}\hfill \end{array}\right.$$

(9)

The first equation is derived based on the maximum allowable charging current, ensuring that the inrush current does not exceed the rated capacity of the power devices. The second equation focuses on the desired charging time and is more relevant for setting the time constant to achieve a target voltage within a specific duration. Choosing the appropriate current-limiting resistor in practical applications can depend on factors such as the circuit’s rated current, the power device’s maximum current, and the charging time.

3. The NLM-Based Pre-Charging Strategy of M3C

The traditional pre-charging strategy does not address the inrush current problem during the transition to the controllable stage when CPS-PWM is utilized. Additionally, as the number of SMs increases, continuing the use of CPS-PWM would result in the loss of several benefits. To overcome these limitations, this paper utilizes an improved NLM approach for M3C pre-charging control. By improving the traditional NLM and selecting specific SMs for insertion by sorting the number of SMs, the inrush current during the controlled pre-charging stage can be decreased.

3.1. Traditional NLM Pre-Charging Strategy

3.1.1. Number of SMs in Operation

The traditional NLM determines the number of SMs in operation based on the current bridge arm voltage reference v_{xy_ref} (x∈{a, b, c}, y∈{u, v, w}) and the rated value of the capacitor voltage U_c. It can be represented as follows:

$$n_{xy}=\mathrm{round}(|{\displaystyle \frac{v_{xy\_ref}}{U_c}}|)$$

(10)

where n_xy is the number of SMs inserted in the xy bridge arm (x∈{a, b, c}, y∈{u, v, w}), and the round(x) is to round the nearest integer.

However, the traditional NLM cannot be directly used for pre-charging due to the potential generation of inrush current. In addition, as v_xy__ref increases during switching, too many SMs may be inserted, leading to a larger current. Furthermore, the SM number judgment does not account for the issue of inrush current during the switching algorithm. Therefore, this paper improves the number of SMs inserted:

$$n_{xy}=\mathrm{floor}({\displaystyle \frac{\sqrt{2}{U}_s}{v_c}})$$

(11)

where the floor(x) rounds down to the nearest integer, producing the largest integer that is less than or equal to the current value, and v_c is the average capacitance voltage of all SMs in the current bridge arm.

The optimal number of active SMs is determined by evaluating the minimum value of SMs that can be used in the current bridge arm. It can ensure a suitable charging current during the charging stage. Especially when transitioning to the controllable stage, it can gradually transfer the voltage on the current-limiting resistor to the SM with a smaller voltage by sorting, which reduces the inrush current.

It is important to note that, when the number of SMs is small, the output voltage level decreases, and the bridge arm current exhibits significant second-order harmonic components. These harmonics arise from power imbalance and the reduced equivalent switching frequency per SM, which becomes more pronounced as the number of SMs decreases. Such harmonic distortion can adversely affect the accuracy of state judgment based on current waveforms. Therefore, before the bridge arm current is used for state detection, it must be processed through a band-pass filter to suppress the second-order harmonics and extract the fundamental component essential for accurate analysis.

3.1.2. Input Reactive Current Compensation

Unlike the normal balancing process during M3C operation, an ideal charging process does not consume active power. Instead, it requires reactive power to be absorbed from the input grid and stored in the SM capacitors. To compensate for the reactive current during charging, this paper implements a control framework to achieve this goal, as shown in Figure 2. The energy absorbed by the capacitor during the charging process satisfies the following:

$$\left\{\begin{array}{l}{\displaystyle \frac{9N}{2}}C(U_c^2-U_{c1\_a}^2)=9N{\displaystyle {\int }_{t_1}^{t_2}{v}_c{i}_{sq\_ref}dt}\hfill \\ v_c=U_{c1}+k_1(t-t_1)\hfill \end{array}\right.$$

(12)

where k₁ is the slope of the given TCV ramp function.

To facilitate analysis, it is assumed that the reactive current i_{sq_ref} remains constant:

$$i_{sq\_ref}={\displaystyle \frac{C(U_c^2-U_{c1}^2)}{2(U_{c1}-k_1{t}_1)(t_2-t_1)+k_1(t_2^2-t_1^2)}}$$

(13)

In addition, the controls on the input and output sides are considered, all of which utilize a dq decoupling control scheme. The reference values for the output active current i_rd__ref and reactive current i_rq__ref are set to zero. The NLM strategy tracks the given ramp function to accomplish the pre-charging operation of M3C.

3.2. Proposed NLM Pre-Charging Strategy

3.2.1. Quick-Sorting Algorithm

As the number of SMs increases, the computational burden of the NLM-based pre-charging strategy also increases. The bubble sorting algorithm, with its slow performance, may struggle to accurately track signals. In contrast, the quick-sorting algorithm not only outpaces the bubble sorting algorithm in speed but also boasts superior average time complexity.

This paper employs the quick-sorting algorithm-based NLM to perform the pre-charging operation of the M3C. Figure 3 presents an example of the quick-sorting algorithm operation using ten SMs.

The indices of SM voltage are utilized, and the operation is carried out based on both their indices and values. The rules for the quick-sorting algorithm are specified as follows:

① Select the first SM as the pivot (Replace with “P” in the figure) and define two pointers, which are L and R. The L pointer points to U₁, and the R pointer points to U₁₀.

② Move the R pointer to the left first. If Value[R] ≤ Value[P], stop moving the R pointer. Move the L pointer to the right until Value[L] ≥ Value[P].

③ Swap the data referred to by the L and R pointers. Repeat the operation in ② until the L and R pointers point to the same position.

④ Swap the position of the pointer and the data pointed to by the pivot.

⑤ Use the pivot as the dividing line and repeat from ① to ④ recursively. Continue until the values on both sides are arranged in order.

3.2.2. The M3C Pre-Charging Based on Improved NLM Strategy

The M3C pre-charging stage progresses according to a specific procedure: The initial values of all SM capacitance voltages are set to zero, and all SMs are blocked for uncontrolled pre-charging. When the bridge arm voltage reaches U_c1 at the end of the uncontrolled stage, the NLM controllable stage begins. Firstly, the optimal number of SMs n_xy that can be permitted to enter the bridge arm is determined based on (11). Then, the capacitance voltages of the SMs currently collected are sorted using a quick sort algorithm from low to high. The charging and discharging states in this phase are determined in the same way as in bubble sorting. If the SM capacitance voltages are rated, M3C enters standby mode. Figure 4 shows the control signal flowchart during M3C pre-charging.

4. Simulation Analysis

4.1. Simulation Parameters

To verify the effectiveness of the proposed M3C pre-charging control strategy, we performed simulation analysis with MATLAB/Simulink. The simulation parameters are presented in

Table 1. Simulation parameters of M3C.

Parameter	Value
Input grid voltage vs/kV	11
Output grid voltage vr/kV	11
SM capacitance C/mF	50
Input inductance Ls/mH	8
Output inductance Lr/mH	8
Arm inductors Lb/mH	10
Sampling period Ts/µs	10
Input frequency fs/Hz	50
Output frequency fr/Hz	50/3
Rated value of SM Uc/V	2000
Number of SMs (per arm) N	20

.

Based on the simulation data, the cutoff frequency of the uncontrolled stage is determined as f₀ = 10.33 Hz, which is lower than the input frequency f_s. Figure 5 shows the range of the current-limiting resistor selection, with the optimal value shown on the line. In this paper, we selected a current-limiting resistor value of 10 Ω. Using Equation (9), the time t1 of the uncontrolled stage is calculated to be 0.336 s, and the inrush current is 425.84 A. The voltage U_c1 when the traditional uncontrolled stage of pre-charging ends is calculated to be 606.25 V. The time t₁ of the uncontrolled stage is calculated to be 0.336 s, and the inrush current is 425.84 A. The SM capacitance voltage is set to U_c = 2000 V, the value of i_{sq_ref} is set to 233 A, and the time for the controllable stage to increase voltage according to slope is set to 0.30 s.

The bridge arm inrush current in the uncontrollable stage, the bridge arm inrush current during switching, and the maximum bridge arm current in the controllable stage are represented by I₀, I_t, and I_cm, respectively. Similarly, the input inrush current in the uncontrollable stage, the input inrush current during switching, and the maximum input current in the controllable stage are represented by I_s0, I_st, and I_scm, respectively.

4.2. Pre-Charging of M3C Based on CPS-PWM Strategy

Figure 6a,b are the waveforms of the nine bridge arm voltages and currents using the CPS-PWM strategy. It can be seen that I₀ is about 469 A, which is close to 425.84 A. At 0.34 s, uncontrolled charging completion aligns with the theoretical value of 0.3395 s and enters the controllable stage of the CPS-PWM strategy. However, the CPS-PWM has a sudden increase in bridge arm voltage and bridge arm current. Specifically, at the switching moment, I_t is 1270.36 A, because the voltage across the current-limiting resistor is transferred to the SMs. It causes a voltage of 1159.00 V, with a voltage difference with respect to 40 kV, and I_cm is 1513.64 A. At 0.65 s, the charging reaches the rated value and enters the standby mode for normal operation of M3C. The controllable stage charging time is 0.31 s, which is close to the set value of 0.30 s.

Figure 6c shows the waveform of the capacitance voltage of 20 SMs on one bridge arm under the CPS-PWM strategy. During the charging process, the capacitance voltage of the bridge arm SMs increases synchronously, but there are notable fluctuations among the 20 SMs, with a range of approximately 11.80 V with respect to 2000 V. Figure 6d shows the waveform of the three-phase input current. I_st is about 3772.91 A on the input side during stage switching, which will have a significant impact on the converter.

4.3. Pre-Charging of M3C Based on NLM Strategy with Quick-Sorting Algorithm

Figure 7a,b shows the waveforms of the bridge arm voltage and current controlled by M3C pre-charging based on the NLM strategy with the quick-sorting algorithm. At the moment of switching to the controllable stage, I_t is 508.50 A. Additionally, the sub-converters maintain balance, only experiencing a 362.50 V swing with respect to 40 kV, and the fluctuation in CCV of 61.11 V is reduced compared to the bubble sort algorithm. Additionally, I_cm is 1275.35 A, which is reduced by 78.25 A compared to the bubble sorting. The M3C pre-charging stage finishes at 0.65 s, while the charging time of the controllable stage is 0.31 s.

Figure 7c shows the SM capacitance voltage waveform of 20 SMs on one bridge arm based on the NLM strategy with the quick-sorting algorithm. The synchronization of the SM capacitance on the bridge arm is significantly enhanced when compared to the bubble sort algorithm, with a maximum difference of 3.48 V with respect to 2000 V. The 20 SMs grow almost synchronously. Figure 7d shows the waveform of the three-phase input current, and I_st is 1492.90 A.

In this paper, from 100 to 2000 pieces of data are sorted, and the average time required to process the same data is compared between the quick-sorting algorithm and the bubble sorting algorithm for different amounts of data, and the time required is shown in Figure 8a. It is apparent that, when sorting data, particularly with substantial quantities of data, the quick-sorting algorithm requires significantly less time than the bubble sorting algorithm. Figure 8b shows the comparison of the state switching rate between the quick-sorting algorithm and the bubble sorting algorithm under different simulation time steps. The quick-sorting algorithm exhibits a higher number of state transitions under the three simulation time steps. Furthermore, the smaller the simulation time step, the larger the amount of data that needs to be processed. This indicates that the quick-sorting algorithm is faster than the bubble sorting algorithm in terms of sorting speed and has an advantage in processing larger amounts of data.

In summary, compared with the CPS-PWM, the NLM has been greatly reduced in terms of inrush current, bridge arm voltage fluctuation, maximum bridge arm current, and switching frequency during charging. Compared with the NLM based on the bubble sorting algorithm, the improvement effect of the bridge arm inrush current based on the quick-sorting NLM is relatively small. However, the advantage of the quick-sorting algorithm is to reduce the fluctuation of capacitor voltage, and the improvement effect on the fluctuation of the capacitor voltage between the phases and bridge arms is obvious.

5. Experiment Validation

To validate the effectiveness of the proposed NLM-based M3C pre-charging strategy, an experimental prototype was built with three SMs per bridge arm. The control system is composed of a dSPACE platform and an EP4CE10 FPGA, ensuring coordinated control and real-time response. The key experimental parameters are listed in

Table 2. Experimental parameters of M3C.

Parameters	Value
Input grid voltage vs/V	60
Output grid voltage vr/V	60
SM capacitance C/mF	22
Input inductance Ls/mH	10
Output inductance Lr/mH	10
Arm inductors Lb/mH	5
AC Y-connect Load Ro/Ω	15
Current-limiting resistor Rl/Ω	10
Input frequency fs/Hz	50
Output frequency fr/Hz	50/3
Number of SMs (per arm) N	3
Rated value of capacitor voltage in SM Uc/V	50
Controllable stage time t/s	0.3

.

Figure 9, Figure 10 and Figure 11 present the experimental results, which demonstrate a stable voltage rise, effective suppression of inrush current, and balanced capacitor charging, confirming the practicality of the proposed method. These results verify the feasibility of the proposed pre-charging method under practical conditions and confirm its suitability for a modular multilevel matrix converter.

5.1. M3C Pre-Charging Strategy Based on CPS-PWM Strategy

At a carrier frequency of 1 kHz, the modulation ratio is 1, and the controllable stage time is 0.30 s. Figure 9 shows the capacitance voltage of an SM on ch1 and the current of a bridge arm on ch2.

It can be observed that, at around 0.99 s, the uncontrollable pre-charging is completed, and the switch to CPS-PWM occurs. At 1.30 s, the pre-charging operation is completed, and the system enters the standby mode of normal M3C operation. In the experiment, I₀, I_t, and I_cm are 2.56 A, 5.88 A, and 6.95 A, respectively. The uncontrollable stage time t₁ and the inrush current I₀ are respectively in agreement with 0.984 s and 2.45 A. The controllable stage lasted for 0.31 s, which is essentially consistent with the set time of 0.30 s. The control effect is good.

5.2. Bubble Sorting Algorithm-Based NLM Strategy

The experimental results are shown in Figure 10. Keeping the control strategy unchanged during the uncontrollable stage, this strategy completes the uncontrollable pre-charging at 0.99 s and reaches the rated value at around 1.30 s.

The I_t and I_cm are 4.32 A and 6.77 A, respectively, which are reduced by 1.56 A and 0.18 A from CPS-PWM, respectively. Additionally, the switching frequency is low, around 0.72 kHz, representing an average value.

It is indicated that the NLM modulation strategy significantly reduces the inrush current during switching moments, as well as the bridge arm current during the controllable stage.

5.3. Quick-Sorting Algorithm-Based NLM Strategy

The experimental results of this strategy are shown in Figure 11. This strategy completes the uncontrollable pre-charging at 0.99 s and reaches the rated value at around 1.30 s.

The I_t and I_cm are 3.92 A and 6.72 A, respectively, which are reduced by 0.40 A and 0.05 A from the bubble sorting algorithm, respectively.

Compared to the NLM based on the bubble sorting algorithm, the quick-sorting algorithm not only generates smaller inrush currents during the switching moment but also exhibits significantly lower bridge arm currents during the charging process. This is due to the faster sorting of SM in the quick-sorting algorithm, especially in cases of high power and a larger number of SMs, where the superiority of the quick-sorting algorithm is even more evident.

6. Conclusions

This paper presents a closed-loop fast pre-charging strategy using NLM instead of the traditional PWM-based pre-charging strategy. This paper proposes an improved NLM strategy for M3C pre-charging by reducing the number of input sub-modules, which effectively decreases the inrush current during grid connection, and switching to the controllable stage, thereby ensuring converter safety. Furthermore, this paper discusses the injection of reactive current to ensure stable capacitor step-up. To minimize fluctuations in the cluster capacitor voltage and the sub-module capacitor voltage during the pre-charging process, the quick sort algorithm replaces the bubble sort algorithm. The feasibility and reliability of the pre-charging strategy have been verified through simulation analysis and experimental validation.