Comparison of Configurable Modular Two-Level and Three-Level Isolated Bidirectional DC–DC Converters for Super-Capacitor Charging in DC Shore Power Systems

Abstract

Compared to the AC counterpart, the DC shore power system provides a significant advantage of efficient power supply from renewable sources to ships and onshore loads. Super-capacitors serve as key energy storage units in such a system to buffer the power fluctuations and collect the regenerative energy. However, the ultra-wide voltage range of super-capacitors imposes a significant challenge in the topology selection and efficiency optimization of the interfacing isolated bidirectional DC–DC converter. To tackle this challenge, this paper analyzes and compares two promising converter topologies, which are a configurable modular two-level dual-active bridge (CM-2L-DAB) and a three-level dual-active bridge (3L-DAB). To facilitate an ultra-wide voltage range, extended phase-shift (EPS) modulation in conjunction with the topology reconfiguration is analyzed for the CM-2L-DAB, while a hybrid modulation scheme is proposed for the 3L-DAB. A unified design approach is provided for both topologies, which also yields to the power loss modeling. On this basis, the CM-2L-DAB and 3L-DAB are thoroughly compared in terms of the modulation schemes, current stress, soft-switching operation, power conversion efficiency, material usage, closed-loop control scheme, and reliability. A prominent conclusion can be drawn that the CM-2L-DAB provides a higher efficiency than the 3L-DAB over the whole voltage range, but it relies on additional relays to reconfigure its topology which results in lower reliability and dynamic performance than the 3L-DAB.

1. Introduction

Nowadays, the transportation sector has been a major source of greenhouse gas and carbon emission globally [1]. Taking the docked ships in the harbor for example, the shipboard power supply mostly relies on the diesel generator which consumes more fuel and produces more carbon emission than in the state of navigation [2]. This makes the shore-to-ship power technology, deploying the shore-based power, especially the renewables, to supply the docked ships, highly attractive to decarbonize shipping transportation [3,4]. Therefore, there is a high demand for a renewable and efficient shore power system that can integrate the public grid, photovoltaics (PV), wind turbines, shipboard energy storage, and loads in a single system, as illustrated in Figure 1. In such a system, the shore-based energy storage, such as a super-capacitor, also plays a key role in buffering the power fluctuation of the renewables and recycling the power from the regenerative loads [5]. Compared to the AC counterpart, the DC shore power system eliminates the additional DC–AC and AC–DC power conversion stages that are unnecessary for the DC-internal sources and loads, which reduces the investment cost and improves the system efficiency [6].

In the DC shore power system, the bidirectional isolated DC–DC converter is a key enabling component to interconnect the super-capacitor and the shipboard battery storage system to the DC bus. Among others, the dual-active bridge (DAB) converter and CLLC resonant converter stand out as the most popular topologies due to their bidirectional power transfer capability and soft-switching characteristic [7,8,9,10]. Compared to the CLLC, the DAB converter requires less passive components and has a wider voltage range and higher power rating [11,12,13]. Thus, the DAB converter is preferred in the super-capacitor charging application. However, the wide voltage range of a high-power super-capacitor imposes high-voltage stress on the semiconductor devices, which makes the conventional two-level DAB topology inappropriate.

To adapt to the wide voltage range with lower voltage switches, two multi-level DAB topologies are further considered. The configurable modular two-level DAB converter (CM-2L-DAB) is a promising topology that is proposed in [14]. It connects two DAB modules in either input-parallel output-series (IPOS) or input-parallel output-parallel (IPOP) using relays. Due to the reconfigurability, the topology can adapt to a very wide voltage range and maintain a high efficiency using the modulation scheme of the 2L-DAB converter [15,16,17,18]. However, the modular structure inevitably increases the number of components.

To keep a low number of components, the three-level DAB (3L-DAB) converter is proposed in [19,20], where the three-level neutral-point-clamped (3L-NPC) bridge is employed on the high-voltage side. Compared to the 2L-bridge, the 3L-NPC bridge provides an additional degree-of-freedom (DoF) in the modulation, which can be utilized to optimize the efficiency of the DAB converter [21,22,23,24,25]. However, the modulation strategy is more complicated especially considering the wide voltage range.

So far, there has been extensive research on the optimal modulation schemes on the 2L-DAB and 3L-DAB converter separately [26]. However, the different modulation characteristic of the CM-2L-DAB and the 3L-DAB have never been thoroughly compared considering the wide voltage range of the super-capacitor. Moreover, no unified design approach can be used for these two topologies to quantify the difference in the total rating of the switches and the passive components. Therefore, it is difficult to evaluate and compare their performance and select the more suitable topology for the targeted application.

This paper aims to fill in this gap by providing a comprehensive comparison between the two advanced isolated bidirectional DC–DC converters, namely CM-2L-DAB and 3L-DAB, for the super-capacitor charging application.

The main contributions of this paper are the following:

(1)

A novel hybrid modulation scheme of the 3L-DAB for wide-voltage operation;

(2)

A unified and step-by-step design procedure of the CM-2L-DAB and 3L-DAB;

(3)

Soft-switching analysis and power loss modeling of two topologies;

(4)

Comprehensive comparison and trade-off of CM-2L-DAB and 3L-DAB in terms of modulation schemes, current stress, soft-switching operation, power conversion efficiency, material usage, closed-loop control scheme, and reliability.

The remaining part of this paper is organized as follows: Section 2 illustrates the topology and modulation scheme of the CM-2L-DAB. In Section 3, the topology of the 3L-DAB is introduced, and a novel hybrid modulation scheme for wide voltage range operation is proposed. Section 4 introduces a unified design and power loss modeling for two topologies. The performance comparison is presented in Section 5, which is validated by both analytical and simulation results. Finally, Section 6 concludes this paper.

2. Topology and Modulation of CM-2L-DAB

2.1. Topology Description

The CM-2L-DAB converter consists of two 2L-DAB modules as shown in Figure 2. Each 2L-DAB module is composed of two H-bridges with 8 switches and diodes, one high-frequency (HF) transformer with a leakage inductance L_k and a turn ratio n, and two DC-link capacitors. The inputs of two modules are connected in parallel to interface the DC bus of the shore power system. The outputs of two modules are connected to the super-capacitor in a flexible manner via three relays, K₁, K₂, and K₃. When K₁ is closed and K₂ and K₃ are open, the two modules are in an IPOS configuration, which makes it suitable to withstand the high voltage of the super-capacitor. When K₁ is open and K₂ and K₃ are closed, the converter is reconfigured to IPOP, which can share the high current stress in the low-voltage operation.

Therefore, assuming a DC bus voltage V₁ and super-capacitor voltage V₂ ∈ V_2,min, V_2,max and power is equally shared between two modules, the operation of the CM-2L-DAB is classified into two modes.

HV mode: V₂ ∈ [(V_2,min + V_2,max)/2, V_2,max]

where CM-2L-DAB is in IPOS.

LV mode: V₂ ∈ [V_2,min, (V_2,min + V_2,max)/2]

where CM-2L-DAB is in IPOP.

2.2. Modulation Scheme

Due to the topology reconfiguration, the output voltage range of each 2L-DAB is essentially [V_2,min/2, V_2,max/2]. However, even with a reduced voltage range, the conventional single-phase-shift (SPS) modulation is still insufficient for a high efficiency operation of the CM-2L-DAB due to loss of soft-switching in the light-load condition. Therefore, to adapt to the output voltage range, each DAB module employs the extended-phase-shift (EPS) modulation [27].

The operation waveform of the EPS is shown in Figure 3. All switches operate with a 50% duty cycle over a switching period Ts. When V₁ > nV₂, the phase shift between S₁ and S₄ define the inner phase shift ratio D₁ ∈ [0, 0.5], and the phase shift between S₁ and Q₁ define the outer phase shift ratio D₂ ∈ [0, 0.5]. Depending on the relationship of D₁ and D₂, two modulation modes are derived for the EPS, where D₁ ≤ D₂ as shown in Figure 3a accounts for the heavy-load mode, and D₂ < D₁ as shown in Figure 3b accounts for the light-load mode.

The transferred power of the 2L-DAB module can be expressed as

$$P={\displaystyle \frac{2}{T_{\mathrm{s}}}}{\displaystyle {\int }_t^{t+\frac{T_{\mathrm{s}}}{2}}{i}_{{\mathrm{L}}_r}(t)\cdot v_{\mathrm{ab}}(t)dt}$$

(1)

Assuming a base power transfer of P_N = nU₁U₂/8f_sL_r, the per-unit transferred power of the 2L-DAB with the EPS modulation is

$$p={\displaystyle \frac{P}{P_{\mathrm{N}}}}=\{\begin{array}{l}4(-2D_1^2+4D_1{D}_2-D_1-4D_2^2+2D_2),\hspace{1em}{D}_1\le D_2\\ 4(2D_2+2D_1^2-4D_1{D}_2-D_1),\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em} D_1>D_2\end{array}$$

(2)

To reduce the conduction loss across the wide voltage range, a minimum RMS current method is applied to the EPS, resulting in optimal phase shift ratios as listed in

Table 1. Phase shift ratio of CM-2L-DAB.

p	D1	D2
${\displaystyle \frac{2k-2}{k^2}}\le p\le 1$	${\displaystyle \frac{k-1}{2}}\sqrt{{\displaystyle \frac{1-p}{k^2-2k+2}}}$	${\displaystyle \frac{1}{4}}+{\displaystyle \frac{k-2}{4}}\sqrt{{\displaystyle \frac{1-p}{k^2-2k+2}}}$
${\displaystyle \frac{2k-2}{{(3k-2)}^2}}\le p<{\displaystyle \frac{2k-2}{k^2}}$	${\displaystyle \frac{1}{2}}-{\displaystyle \frac{1}{2}}\sqrt{{\displaystyle \frac{p}{2(k-1)}}}$	${\displaystyle \frac{1}{4}}+{\displaystyle \frac{k-2}{4}}\sqrt{{\displaystyle \frac{p}{2(k-1)}}}$
$0\le p\le {\displaystyle \frac{2k-2}{{(3k-2)}^2}}$	${\displaystyle \frac{4k-3-\sqrt{1-(4k-2)p}}{4(2k-1)}}$	${\displaystyle \frac{3k-2-k\sqrt{1-(4k-2)p}}{4(2k-1)}}$

, where k = nV₂/V₁. It should be noticed that with the EPS modulation, all switches can realize zero-voltage switching (ZVS) in the full operating range.

3. Topology and Modulation of 3L-DAB

3.1. Topology Description

Compared to the conventional 2L-DAB converter, the 3L-DAB converter replaces an H-bridge with a 3L-NPC full bridge on the side of the super-capacitor, as shown in Figure 4. Therefore, it consists of 12 switches, 16 diodes, 1 HF transformer, and three DC-link capacitors in total. The 3L full bridge can generate 3 voltage levels, i.e., 0, ±V₂/2, and ±V₂, which provide a higher DoF than a 2L-bridge.

3.2. Modulation Scheme

To facilitate a wide voltage range, a hybrid modulation method is proposed for the 3L-DAB, which fully uses the additional voltage level of ±V₂/2. The proposed method is also divided into the HV mode and LV mode, which uses the output voltage V_2,bd as the boundary of two modes.

The operation waveform of the LV mode is shown in Figure 5a, where the primary side AC voltage v_ab is a 50% square wave and the secondary side AC voltage v_cd is an asymmetric 4-level square wave. In this mode, one DoF of the modulation is the interval of the voltage level ±V₂ equaling mT_s, respectively, where m ∈ [0, 0.5]. Moreover, the outer phase shift ratio D₂ ∈ [−0.5, 0.5] is also employed as the other DoF to control the direction and magnitude of the power flow.

As the output voltage increases, the value of m in the LV mode decreases and finally reaches zero following the voltage-second matching principle, which naturally transits to the HV mode with only ±V₂/2 and 0 voltage levels for v_cd, as shown in Figure 5b. In the HV mode, the interval of the voltage level ±V₂/2, i.e., mT_s, and the outer phase shift ratio D₂ are employed as two DoFs of the modulation. The value of m in the HV mode naturally decreases with an increasing output voltage.

The power transfer of the 3L-DAB depends on the relationship between m and D₂. Defining −0.5 ≤ D₂ < −m as Mode M1, −m ≤ D₂ < 0 as Mode M1, 0 ≤ D₂ < 0.5 − m as Mode M3, and 0.5 − m ≤ D₂ ≤ 0.5 as Mode M4, the per-unit transferred power of the LV mode is expressed as

$$p={\displaystyle \frac{P}{P_{\mathrm{N}}}}=\{\begin{array}{l}8 D_2^2-8 D_2 k+8 D_2-4 k^2+2 k, \mathrm{M}1\\ 16 D_2^2+8 D_2 k+4 k^2-6 k+2, \mathrm{M}2\\ -8 D_2^2+8 D_2 k+4 k^2-6 k+2, \mathrm{M}3\\ -16 D_2^2-8 D_2 k+16 D_2-4 k^2+10 k-6,\mathrm{M}4\end{array}$$

(3)

And the per-unit transferred power of the HV mode is

$$p={\displaystyle \frac{P}{P_{\mathrm{N}}}}=\{\begin{array}{l}-2 \left(2 k-1\right) \left(2 D_2+k\right), \mathrm{M}1\\ 8 D_2^2+8 D_2 k-4 D_2+4 k^2-6 k+2, \mathrm{M}2\\ 2 \left(2 k-1\right) \left(2 D_2+k-1\right), \mathrm{M}3\\ -8 D_2^2-8 D_2 k+12 D_2-4 k^2+10 k-6,\mathrm{M}4\end{array}$$

(4)

From (3) and (4), the phase shift ratio of the proposed hybrid modulation method is obtained, and the results are listed in

Table 2. Phase shift ratio of 3L-DAB.

HV Mode	LV Mode
0 < k < 1/2	1/2 < k < 2/3	2/3 < k < 1

. It should be noticed that the switches, except Q₂ and Q₃, can realize ZVS in all operation conditions.

From the perspective of the operation principle, it is clear that both the CM-2L-DAB and the 3L-DAB have an HV mode and an LV mode for a wide voltage range operation. The key difference is the mode transition of the CM-2L-DAB is realized by the operation of relays, which need to power off the converter temporarily. The mode transition of the 3L-DAB is realized by modulation schemes, which are fast and continuous.

4. Converter Design and Loss Modeling

In order to provide an effective comparison, the converter design and loss modeling procedures are presented in this section as a preliminary step. Moreover, for obtaining a fair comparison, it is assumed that the switching frequency, input and output voltage ranges, and the maximum magnetic density and winding wire diameter of the transformer are identical for the CM-2L-DAB and the 3L-DAB. In this design example, the rated power is set as 200 kW. The input voltage is 750 V, and the output voltage on the super-capacitor side is 300–1500 V.

4.1. Converter Design

4.1.1. Transformer

Higher switching frequency is beneficial for reducing the volume of passive elements, but it will increase the loss of the transformer core, causing heat accumulation. Moreover, a higher magnetic flux density of the transformer results in a smaller core loss, but it corresponds to more winding turns, leading to a larger winding loss. Therefore, the design of transformers should be carefully designed according to the multiple objectives.

• Leakage inductance: in order to reduce the converter size and avoid the auxiliary inductance, L_r is expected to be contributed to by the leakage inductance of the transformer. Its value is constrained by the transmission power. Define the output voltage corresponding to the rated power of 200 kW as V₂′. Since the CM-2L-DAB is equally shared by the two separate DAB converters, the rated power for each is P′ = 100 kW. The leakage inductance is

  $$L_r={\displaystyle \frac{n{V}_1{V}_2^{\prime }{p}^{\text{'}}}{8f_{\mathrm{s}}{P}^{\text{'}}}}$$

  (5)
• Core design: in order to reduce the volume and loss of the core, the U-shaped tape-wound core of nanocrystalline material with high saturation magnetic density and low coercivity is selected. The Area Product (AP) method can be employed to select the core parameters, in which the area product A_p is the product of the core winding window area A_w and cross-sectional area A_e, i.e,

  $$A_{\mathrm{p}}=A_{\mathrm{w}}{A}_{\mathrm{e}}={\displaystyle \frac{(P_{\mathrm{o}}+\frac{P_{\mathrm{o}}}{\eta })\times {10}^4}{K_{\mathrm{s}}{K}_{\mathrm{f}}{K}_{\mathrm{u}}{f}_{\mathrm{s}}{J}_{\mathrm{rms}}{B}_{\mathrm{m}}}}$$

  (6)

  where P_o represents the maximum output power, η is the transformer efficiency, K_s is the lamination coefficient of the strip winding core, K_f is the waveform coefficient, K_u is the core window utilization coefficient, and J_rms is the winding current density. f_s is the switching frequency, and B_m is the maximum magnetic density. Note that J_rms, f_s, and B_m should be selected with the tradeoff between volume and power loss. Here, as a rule of thumb, η is set as 0.99, and K_s = 0.75, K_f = 4, K_u = 0.4, J_rms = 400 A/cm², and f_s = 15 kHz are set as the initial values. If the power loss is unacceptable, they should be adjusted.
• Winding design: in order to avoid the surge of loss caused by the skin effect and proximity effect under high-frequency operation, the shaped copper litz wire was selected as the winding wire, and the radius of each strand was controlled within the skin depth. The skin depth of copper at 100 °C can be calculated as

  $${\delta }_{\mathrm{w}}={\displaystyle \frac{76.5}{\sqrt{f_{\mathrm{s}}}}}$$

  (7)

The winding diameter is the ratio of the maximum RMS current to the current density. As mentioned, the current density is set as J_rms = 400 A/cm². According to Figure 5, the maximum RMS current can be derived and thereby the winding diameter is

$$D_{winding}={\displaystyle \frac{i_{L_r\_\mathrm{rms}}}{J_{\mathrm{rms}}}}={\displaystyle \frac{1}{J_{\mathrm{rms}}}}\sqrt{{\displaystyle \frac{1}{t_3-t_0}}{\displaystyle \sum _{\mathrm{i}=0}^3\frac{\left(t_{\mathrm{i}+1}-t_{\mathrm{i}}\right)\left(i_{t_{\mathrm{i}}}^2+i_{t_{\mathrm{i}}}{i}_{t_{\mathrm{i}+1}}+i_{t_{\mathrm{i}+1}}^2\right)}{3}}}$$

(8)

The next step is to determine the number of windings turns, which is determined as

$$N={\displaystyle \frac{U_{\mathrm{m}}}{K_{\mathrm{f}}{f}_{\mathrm{s}}{A}_{\mathrm{e}}{B}_{\mathrm{m}}}}$$

(9)

where U_m is the maximum RMS voltage of winding. Basically, the smaller number of windings turns corresponds to less impact of the skin effect. But since it is limited by the window shape, N may also need to be iteratively adjusted.

Based on the above analysis, the transformer design flowchart is depicted in Figure 6. Following the design flow, the transformer parameters for the two types of converters are listed in

Table 3. Parameters of transformers.

Parameters	CM-2L-DAB	3L-DAB
Rated power P	200 kW	200 kW
Core window area Aw	49 cm2 * 2	38 cm2
Core cross-section area Ae	25 cm2 * 2	36 cm2
Mass of magnetic core mc	8.38 kg * 2	9.02 kg
Maximum RMS current Irms_m	(544 A * 2):(544 A * 2)	593 A:1483 A
Strand diameter of Litz wire dl	0.5 mm
Winding turns N	7:7	5:2
Winding layers Nl	1:1	1:1
Leakage inductance Lr	18.75 μH	21.75 μH
Peak flux density Bm	0.7 T
Frequency fs	15 kHz

.

4.1.2. Semiconductor Devices

The semiconductor devices include SiC MOSFETs, and Si diodes are selected based on the withstand voltage and current. Securing sufficient margin, the SiC MOSFET selected for the 2L-DAB is AIMZHN120R010M1T, and five SiC MOSFETs are connected in parallel as a switch. As for the 3L-DAB, AIMZHN120R010M1T SiC MOSFETs are also selected for S₁~S₄, Q₁ and Q₄, Q₆ and Q₇, and Q₅ and Q₈. The numbers of paralleled MOSFETs for them are 5, 10, 12, and 10, respectively; while Q₂ and Q₃ use IMBG65R007M2H SiC MOSFETs with 10 parallel connections; D₁ and D₂ and D₃ and D₄ use IDWD140E120D7 Si diodes with 12 and 10 parallel connections, respectively. The characteristics of the selected MOSFETs and diodes are presented in

Table 4. Parameters of semiconductor devices.

Parameter	SiC MOSFET		Si Diode
	AIMZHN120R010M1T	IMBG65R007M2H	IDWD140E120D7
Withstand voltage	VDSS = 1200 V	VDSS = 1200 V	VRRM = 1200 V
Withstand current	IDDC = 146~202 A	IDDC = 146~202 A	IF = 140~207 A
On-resistance	RDS(on) = 10.7 mΩ	RDS(on) = 7.3 mΩ	rD = 9.3 mΩ with VF0 = 1.4 V
Parasitic capacitances	Crss = 16 pF; Ciss = 5703 pF	Crss = 35 pF; Ciss = 6359 pF
Gate threshold voltage	Vth = 4.3 V; Vgp = 5.9 V	Vth = 4.5 V; Vgp = 7 V
Reverse recovery time			trr = 190 ns

.

4.1.3. Filter Capacitors

The value of the filter capacitor to smooth the output voltage is determined as

$$C={\displaystyle \frac{1}{\Delta V_{\mathrm{C}}}}{\displaystyle \int i_{\mathrm{C}}}dt$$

(10)

$$i_{\mathrm{C}}=i_{\mathrm{Ho}}-i_{\mathrm{R}}=i_{\mathrm{Ho}}-{\displaystyle \frac{P}{V_{\mathrm{o}}}}$$

(11)

where ΔV_C is the peak–peak voltage ripple, i_C is the capacitor current, i_Ho is the dc-side current of the H bridge, and i_R is the load current.

Suppose ΔV_C is 1% of the rated voltage and ensure sufficient margin. The filter capacitance is designed as 4.3 mF for the 2L-DAB; as for the 3L-DAB, the capacitance in the H1 bridge is 3.3 mF, and the capacitance in the H2 bridge is 8.8 mF. Considering that the voltage on the capacitor is high and the capacitance is large, the paralleled film capacitor with high withstand voltage is chosen.

4.2. Loss Modeling

The loss in the DAB converter mainly includes the following four parts: core loss and winding loss of the transformer and the conduction loss and switching loss of the semiconductor devices. The mathematical models of them are derived as follows.

4.2.1. Transformer Core Loss

The improved generalized Steinmetz equation (iGSE) can be used to calculate the transformer core loss [28]. The iGSE for DAB is

$$P_{\mathrm{m}}={\displaystyle \frac{k_{\mathrm{i}}{(\Delta B_{\max })}^{\mathrm{b}-\mathrm{a}}}{T_{\mathrm{s}}}}{\displaystyle \sum _{\mathrm{n}}{\left|\frac{B_{\mathrm{n}+1}-B_{\mathrm{n}}}{t_{\mathrm{n}+1}-t_{\mathrm{n}}}\right|}^{\mathrm{a}}}(t_{\mathrm{n}+1}-t_{\mathrm{n}})$$

(12)

where t_n and B_n are the segmentation instant and the magnetic flux density, respectively, and the expressions of k_i and ΔB are

$$k_{\mathrm{i}}={\displaystyle \frac{k_{\mathrm{c}}}{{(2\pi )}^{a-1}{\displaystyle {\int }_0^{2\mathsf{\pi }}|}\cos \theta {|}^a\cdot 2^{b-a}\mathrm{d}\theta }}$$

(13)

$$\Delta B={\displaystyle \frac{1}{N{A}_{\mathrm{c}}}}{\displaystyle {\int }_{t_{\mathrm{n}}}^{t_{\mathrm{n}+1}}vdt}$$

(14)

4.2.2. Transformer Winding Loss

The winding loss of the transformer can be calculated as

$$P_{\mathrm{w}}=R_{\mathrm{w}}{I_{\mathrm{rms}}}^2$$

(15)

where R_w is the AC resistance of the winding.

Due to the high frequency effect, the AC resistance is often several times the DC resistance. The ratio of AC resistance R_wAC to DC resistance R_wDC can be approximated with Dowell’s equation which is [29]

$${\displaystyle \frac{R_{\mathrm{wAC}}}{R_{\mathrm{wDC}}}}=A[{\displaystyle \frac{\sinh (2A)+\sin (2A)}{\cosh (2A)-\cos (2A)}}+{\displaystyle \frac{2(N_{\mathrm{l}}^2{k}_{\mathrm{l}}-1)}{3}}\cdot {\displaystyle \frac{\sinh (A)-\sin (A)}{\cosh (A)+\cos (A)}}]$$

(16)

where

$$A={\left({\displaystyle \frac{\pi }{4}}\right)}^{{\displaystyle \frac{3}{4}}}{\displaystyle \frac{d_{\mathrm{l}}}{{\delta }_{\mathrm{w}}}}\sqrt{\eta }$$

(17)

Therein, N_l is the number of winding layer, k_l is the number of litz wire strands in a single turn, d_l is the diameter of a single bare wire, δ_w is the skin depth, and η is laminar factor.

The DC resistance R_wDC can be obtained as

$$R_{\mathrm{wDC}}={\displaystyle \frac{4{\rho }_{\mathrm{w}}N{l}_{\mathrm{T}}}{k\pi d_{\mathrm{l}}^2}}$$

(18)

where ρ_w is the wire resistivity, N is the number of winding turns, and l_T is the average turn length of the winding, which can be estimated at 1.2 times the circumference of the magnetic column.

Combining (15)~(18), the winding loss of the transformer can be obtained.

4.2.3. Conduction Loss of the Semiconductor Devices

The conduction loss of the MOSFETs is expressed as

$$P_{\mathrm{cond}\_\mathrm{mos}}={\displaystyle \sum \frac{R_{\mathrm{DSon}}}{N_{\mathrm{sw}\_\mathrm{pl}}}\cdot {I_{\mathrm{sw}\_\mathrm{rms}}}^2}$$

(19)

where R_DSon is the on-resistance of MOSFET, N_{sw_pl} is the number of the paralleled MOSFETs, and I_{sw_rms} is the current flowing through the switching position.

Different with the MOSFET, the on-resistance of power diodes cannot be found in the datasheet, because its conduction characteristics are not linear due to conductance modulation effects. Therefore, the linear fitting method is employed here, defining V_D0 as the diode starting voltage and the forward voltage drop as v_D; fitting the slope as the on-resistance r_D, the conduction loss of the diode can be deduced as

$$P_{\mathrm{cond}\_\mathrm{Diode}}={\displaystyle \frac{1}{T_{\mathrm{s}}}}{\displaystyle {\int }_0^{T_{\mathrm{s}}}{v}_{\mathrm{D}}}{i}_{\mathrm{D}}dt={\displaystyle \frac{1}{T_{\mathrm{s}}}}{\displaystyle {\int }_0^{T_{\mathrm{s}}}(V_{\mathrm{D}0}+r_{\mathrm{D}}{i}_{\mathrm{D}})}{i}_{\mathrm{D}}dt=V_{\mathrm{D}0}{i}_{\mathrm{D}\_\mathrm{avg}}+r_{\mathrm{D}}{i}_{\mathrm{D}\_\mathrm{rms}}^2$$

(20)

4.2.4. Switching Loss of the Semiconductor Devices

The turn-on and turn-off losses of the MOS transistor are expressed as

$$p_{\mathrm{sw}\_\mathrm{MOS},\mathrm{on}}=\left|V_{\mathrm{on}}\cdot I_{\mathrm{on}}\right|\cdot {\displaystyle \frac{t_{\mathrm{vf}}+t_{\mathrm{ir}}}{2}}\cdot f_{\mathrm{s}}$$

(21)

$$p_{\mathrm{sw}\_\mathrm{MOS},\mathrm{off}}=\left|V_{\mathrm{off}}\cdot I_{\mathrm{off}}\right|\cdot {\displaystyle \frac{t_{\mathrm{vr}}+t_{\mathrm{if}}}{2}}\cdot f_{\mathrm{s}}$$

(22)

Notice that the turn-on and turn-off process of MOSTET is a symmetrical process of charging and discharging the parasitic capacitor. Taking the turning-off instant as an example, V_off and I_off are the corresponding voltage and current before turning off, respectively, and the t_vr and t_if represent the period of voltage rise and current drop, respectively, expressed as

$$t_{\mathrm{vr}}=R_{\mathrm{G}}\cdot C_{\mathrm{rss}}{\displaystyle \frac{V_{\mathrm{off}}}{V_{\mathrm{gp}}}}$$

(23)

$$t_{\mathrm{if}}=R_{\mathrm{G}}\cdot C_{\mathrm{iss}}\cdot \ln ({\displaystyle \frac{V_{\mathrm{gp}}}{V_{\mathrm{th}}}})$$

(24)

where R_G is driving resistance, C_rss and C_iss are the feedback capacitor and input capacitor, respectively, and V_th and V_gp are the threshold voltage and Miller plateau voltage, respectively. They can be obtained from the datasheet.

The switching loss of the diode mainly includes two parts: (1) the switching-off loss of the clamping diode, and (2) the reverse recovery loss of the diode connected in parallel with the MOS transistor, which occurs when the other MOS transistor in the same bridge arm is hard switching. Define V_RR, I_RRM, t_rr, and Q_rr as reverse recovery voltage, maximum current, time, and charge, respectively, and considering t_b = t_rr, the switching loss of the diode can be obtained as

$$p_{\mathrm{sw}\_\mathrm{Diod},\mathrm{off}}={\displaystyle \frac{1}{T_{\mathrm{s}}}}{\displaystyle {\int }_0^{t_{\mathrm{rr}}}{u}_{\mathrm{r}}}{i}_{\mathrm{r}}dt={\displaystyle \frac{1}{6}}{I}_{\mathrm{RRM}}{V}_{\mathrm{RR}}{t}_{\mathrm{rr}}{f}_{\mathrm{s}}$$

(25)

And the recovery loss of the paralleled diode is determined by the reverse recovery charge Q_rr, i.e,

$$p_{\mathrm{sw}\_\mathrm{rr}}={\displaystyle \frac{1}{3}}{V}_{\mathrm{RR}}{Q}_{\mathrm{rr}}{f}_{\mathrm{s}}={\displaystyle \frac{1}{3}}{V}_{\mathrm{RR}}\left({\displaystyle \frac{1}{2}}{I}_{\mathrm{RRM}}{t}_{\mathrm{rr}}\right)f_{\mathrm{s}}={\displaystyle \frac{1}{6}}{V}_{\mathrm{RR}}{I}_{\mathrm{RRM}}{t}_{\mathrm{rr}}{f}_{\mathrm{s}}$$

(26)

5. Performance Comparison of Topologies

In this section, the performance of the two previously designed converters will be compared in the six major domains, which are modulation strategy, soft-switching characteristic, current stress, power loss, material usage, and reliability. To cover different output voltages and power conditions, six operation points are selected which are a. V₂ = 500 V, P = 50 kW (low voltage and light load), b. V₂ = 500 V, P = 200 kW (low voltage and full load), c. V₂ = 900 V, P = 50kW (average voltage and light load), d. V₂ = 900 V, P = 200 kW (average voltage and full load), e. V₂ = 1300 V, P = 50 kW (high voltage and light load), and f. V₂ = 1300 V, P = 200 kW (high voltage and full load).

5.1. Comparison of Modulation Strategy

The EPS modulation of the CM-2L-DAB and the hybrid modulation of the 3L-DAB are validated via PLECS circuit simulation at the six operation points. The operation waveforms are shown in Figure 7. It is validated in Figure 7a that the CM-2L-DAB operates in the IPOP configuration and the EPS modulation with D₂ < D₁, while the 3L-DAB operates in the HV mode with 4 voltage levels. In Figure 7b, the CM-2L-DAB operates in the same LV mode but using other EPS modulation with D₁ < D₂, while the outer phase shift ratio D₂ of the 3L-DAB increases with the load. In Figure 7c,d, when V₂ increases to 900V, the CM-2L-DAB operates in the IPOS configuration and the EPS modulation, while the 3L-DAB operates in the HV mode with only two voltage levels. In Figure 7e,f, when V₂ further increases to 1300 V, the CM-2L-DAB remains in the IPOS configuration, but the inner phase shift ratio D₁ decreases, while the 3L-DAB remains in the HV mode but with a smaller m. The operation waveforms validate the effectiveness of the modulation strategies for both topologies.

5.2. Comparison of Soft-Switching Characteristic

The soft-switching condition of switches in 3L-DAB is determined by the instantaneous inductor current at each switching moment, which is listed in

Table 5. Instantaneous inductor current of 3L-DAB in p.u.

Mode	i(t0)	i(t1)	i(t2)
LV mode
M1	$-4D_{2}k$	$2-4D_{2}k-4k^2-2k$	$2D_2-2k+1$
M2	$-4D_{2}k$	$4D_2$	$4D_{2}k-6k+4k^2+2$
M3	$-2D_2$	$4D_{2}k$	$4D_{2}k-6k+4k^2+2$
M4	$2-2k-4D_2$	$4D_{2}k-2k+4k^2-2$	$4D_{2}k$
HV mode
M1	$-4D_{2}k$	$-2k\left(2D_2+2k+1\right)$	$-2k$
M2	$-4D_{2}k$	$2D_2$	$2k\left(2D_2+2k-1\right)$
M3	$0$	$4D_{2}k$	$2k\left(2D_2+2k-1\right)$
M4	$1-2k-2D_2$	$2k\left(2D_2+2k-1\right)$	$4D_{2}k$

, where the per-unit value i_N = nV₂/(4f_sL_r). According to the employed voltage-second matching principle, m = k − 0.5 in the LV mode, while m = k in the HV mode. The polarity of the switching currents in different modes is further derived. As shown in Table 5, the switching currents marked in green are always positive, the switching currents marked in red are always negative, and the switching currents in yellow can be either positive or negative.

According to the operation waveforms of the 3L-DAB in Figure 5, the ZVS conditions of all switches are listed in

Table 6. ZVS conditions of the 3L-DAB.

Switch	LV Mode				HV Mode
	M1	M2	M3	M4	M1	M2	M3	M4
S1~S4	it2 < 0	it1 < 0	it0 < 0	it0 < 0	it2 < 0	it1 < 0	it0 < 0	it0 < 0
Q1, Q4	it0 > 0	it0 > 0	it1 > 0	it2 > 0	\	\	\	\
Q2, Q3	it1 < 0	it2 < 0	it2 < 0	it1 > 0	\	\	\	\
Q5, Q8	it0 > 0	it0 > 0	it1 > 0	it2 > 0	it0 > 0	it0 > 0	it1 > 0	it2 > 0
Q6, Q7	it0 > 0	it0 > 0	it1 > 0	it2 > 0	it1 < 0	it2 < 0	it2 < 0	it1 > 0

. After checking the instantaneous inductor current in Table 4, all of the switches realize ZVS except for Q₂ and Q₃ in M1, M3, and M4 of the LV mode. Moreover, S₁–S₄ realize Zero-Current Switching (ZCS) in M3 of the HV mode.

The ZVS condition of the CM-2L-DAB is given in

Table 7. ZVS conditions of the CM-2L-DAB.

Switch	Mode
	0 ≤ D1 ≤ D2 ≤ 1	0 ≤ D2 < D1 ≤ 1
S1, S2	$k \left(D_1-1\right)-2 D_2+1<0$	$k \left(D_1-1\right)-2 D_2+1<0$
S3, S4	$2 D_1-2 D_2+k \left(D_1-1\right)+1<0$	$2 D_2-2 D_1+k \left(D_1-1\right)+1<0$
Q1~Q4	$1-k \left(D_1-2 D_2+1\right)>0$	$D_1 k-k+1>0$

. It is proved that with the proposed EPS modulation, all switches can realize ZVS in the CM-2L-DAB converter.

The switching conditions of all switches in both topologies are marked in the operation waveforms in Figure 7 and summarized in

Table 8. Comparison of soft-switching characteristics.

Operation Point	CM-2L-DAB			3L-DAB
	S1/S4	S2/S3	Q1~Q4	S1~S4	Q1/Q4	Q2/Q3	Q5/Q8	Q6/Q7
a	SS	SS	SS	SS	SS	HS	SS	SS
b	SS	SS	SS	SS	SS	HS	SS	SS
c	SS	SS	SS	SS			SS	SS
d	SS	SS	SS	SS			SS	SS
e	SS	SS	SS	SS			SS	SS
f	SS	SS	SS	SS			SS	SS

Note: Green: soft switching (SS); red: hard switching (HS); crossed: no switching action.

. It confirms that all switches of the CM-2L-DAB realize soft-switching under all operation conditions, whereas switches Q₂ and Q₃ of the 3L-DAB are hard switched in the low-voltage condition. It is also interesting to notice that despite two switches not always being soft switched in the 3L-DAB, switches Q₁ to Q₄ are normally on or off for the medium-to-high-voltage condition, which do not have any switching action.

5.3. Comparison of Current Stress

The transformer peak current of the 3L-DAB with the SPS modulation and the proposed hybrid modulation (HM) is firstly compared in Figure 8a. It is evident that the proposed hybrid modulation significantly reduces the current stress of the 3L-DAB at all voltage and load levels. A further comparison is made between the peak current of the CM-2L-DAB with the EPS and the 3L-DAB with the hybrid modulation in Figure 8b. It should be noted that peak current of the CM-2L-DAB represents only one DAB module. It is clear that the CM-2L-DAB has a lower transformer peak current than the 3L-DAB at most of the operation points.

5.4. Comparison of Power Loss

The power losses of two topologies are evaluated and compared using the loss models derived in Section 4. A bidirectional load range of [−200 kW, 200 kW] is scanned for three output voltage levels {500 V, 900 V, 1300 V}. The power loss breakdown is shown in Figure 9. Compared to the 3L-DAB, the CM-2L-DAB has a lower total power loss in nearly all conditions. The largest difference is shown under the low-voltage condition of V₂ = 500 V, where the IPOP configuration halves the device current stress of the CM-2L-DAB leading to a significantly lower device conduction loss and transformer winding loss. For the 3L-DAB, the high current at the low output voltage flows through the 3L-NPC bridge where switches are connected in series, leading to even higher conduction loss. In the low-to-medium-voltage condition, the conduction loss and winding loss are dominated at the heavy load for both topologies. It should also be noticed that the power loss of the CM-2L-DAB is symmetrically distributed under bidirectional load conditions, but for the 3L-DAB the power loss of the forward transmission is higher than the reverse mode under the low-voltage condition. This is due to the fact that the voltage waveforms and transferred power of the LV mode for the 3L-DAB are asymmetric regarding the bidirectional power.

The resulting conversion efficiency of the CM-2L-DAB and the 3L-DAB are compared in Figure 10. The peak efficiency of the CM-2L-DAB is 98.81% at V₂=1300 V and P = ±190 kW, whereas the lowest efficiency is 95.92% at V₂ = 1300 V and P = ±50 kW. The peak efficiency of the 3L-DAB is 98.37% at V₂ = 500 V and P= −90 kW, whereas the lowest efficiency is 89.67% at V₂ = 1300 V and P = ±50 kW. It is shown that both converters can achieve a peak efficiency higher than 98%, but the light load efficiency of the CM-2L-DAB is much higher than the 3L-DAB.

5.5. Comparison of Material Usage

The material usage of the CM-2L-DAB and the 3L-DAB is compared using the design results of Section 4. The comparison includes both semiconductor devices and passive components, which is summarized in

Table 9. Converter material usage.

Parameter	CM-2L-DAB	3L-DAB
Mass of magnetic core	8.38 kg * 2	9.02 kg
Mass of windings	5.21 kg * 2	4.82 kg
Number of MOSFETs	80	104
Number of diodes	80	148
Rating of capacitors	4.84 kVA	5.88 kVA
Number of relays	3	0

. It is shown that the CM-2L-DAB uses nearly doubled magnetic core and winding material than the 3L-DAB and 36% less semiconductor devices. Due to the requirement of the split capacitor for the 3L-NPC bridge, the 3L-DAB has a 21% larger capacitor rating than the CM-2L-DAB. Moreover, the CM-2L-DAB requires three additional power relays for the topology reconfiguration.

5.6. Closed-Loop Control Scheme

As shown in Figure 11, in the CM-2L-DAB, each submodule employs a closed-loop output power regulator with a reference to the equally shared power. It should be noticed that a feedforward control parameter calculation can be implemented based on the analytical solution of the EPS modulation. On top of the submodule-level control, a system-level mode selection module is implemented based on the output voltage to control the power relays.

As shown in Figure 12, the output power control of the 3L-DAB is implemented with a proportional-integral (PI) regulator with feedforward parameter calculation. The hybrid modulation mode is selected based on the output voltage and another PI regulator is used to balance the DC-link capacitor voltages.

By comparing the closed-loop control scheme of the CM-2L-DAB and 3L-DAB converters, it is found that both topologies can use feedforward parameter calculation to improve the transient performance, and they both use a closed-loop regulator to balance the DC-link capacitor voltages. However, an essential difference is that the CM-2L-DAB requires distributed control hardware architecture, while the 3L-DAB only needs a single control unit.

5.7. Reliability

Reliability is another important domain to compare two topologies, which involves many aspects such as semiconductor devices, passive components, a cooling system, and converter control and operation. This section will not cover all these factors but only point out the key differences and concerns between the CM-2L-DAB and the 3L-DAB.

For the 3L-DAB, the switching characteristic of switches in 3L-NPC bridges is different as shown in Table 8, which will lead to unequal power loss distribution and a deviated aging speed of devices. This may affect the reliability of the 3L-DAB converter.

For the CM-2L-DAB, the major reliability concern is the usage of power relays. When the converter operates in a wide voltage range, the power relays need to be frequently switched. This increases risks of failure that will significantly decrease the reliability of the CM-2L-DAB converter. Therefore, from the perspective of reliability, the topology of the CM-2L-DAB converter should not be frequently reconfigured.

6. Conclusions and Outlook

This paper compares the CM-2L-DAB and the 3L-DAB converters for super-capacitor charging applications. To tackle the challenge of the wide voltage range, the EPS modulation in conjunction with the topology reconfiguration is analyzed for the CM-2L-DAB, while a hybrid modulation method is proposed for the 3L-DAB. Moreover, a unified design approach is proposed for two topologies, which also provides power loss models. A comprehensive comparison of two topologies yields the following conclusions:

(1)

The CM-2L-DAB can realize soft-switching of all switches over a wide voltage range, while two switches of the 3L-DAB cannot realize soft-switching in low-voltage conditions;

(2)

The CM-2L-DAB is more efficient than the 3L-DAB in most operation points, since it employs semiconductor devices more effectively, i.e., series connection for high voltage and parallel connection for high current. Thus, the current stress of the CM-2L-DAB is considerably lower;

(3)

The CM-2L-DAB uses 36% less semiconductor devices and 21% smaller capacitors than the 3L-DAB, but the usage of the magnetic material is nearly doubled, and three power relays are necessary;

(4)

The CM-2L-DAB has a more critical reliability concern than the 3L-DAB due to the additional power relays;

(5)

The CM-2L-DAB needs to be powered off when the power relays are reconfigured, which decreases the dynamic performance.

To summarize, a trade-off can be made based on the voltage characteristic of the load profile: (1) When the load voltage does not switch back and forth between the high-voltage and low-voltage ranges/modes very frequently, the CM-2L-DAB converter is a preferred topology, since it offers a higher efficiency, and the reliability and dynamics are acceptable. (2) However, when the load voltage frequently and dynamically changes between the high-voltage and low-voltage ranges/modes, the 3L-DAB converter would outperform, since it allows smooth and online mode transition.

Potential advancements of the CM-2L-DAB converter can be realized by replacing the power relays with bidirectional solid-state switches, especially the emerging monolithic bidirectional switches, which allow for fast topology reconfiguration with improved reliability and dynamic performance. However, it should be noted that no matter which bidirectional solid-state switch topology is employed, an IGBT with at least another diode is in the conduction loop, resulting in higher power loss. This may offset the inherent advantage of the CM-2L-DAB in efficiency. Advanced modulation schemes using both phase-shift angles and duty cycles can further reduce the power loss of the CM-2L-DAB and 3L-DAB converter, and intelligence algorithm such as pareto-optimization and artificial neural networks can be employed in the parameter design to yield an optimal trade-off between the efficiency, power density, reliability, and costs. Moreover, with advances in the performance of the wide band-gap devices, SiC MOSFETs and IGBTs with higher voltage and current rating can be used in bidirectional DC–DC converters to further simply the topology and improve the efficiency.