Concept of Enabling Over-Current Capability of Silicon-Carbide-Based Power Converters with Gate Voltage Augmentation

Abstract

Various methods have been discussed in the literature regarding enabling the over-current (OC) capability of silicon carbide (SiC) MOSFETs. SiC MOSFETs can operate at up to 250 °C without failure. One of their features is to permit transient operation at elevated temperatures. This is possible if the stress on the gate oxide and packaging can be kept to a level that can be handled. This paper, instead, investigates the potential of enabling the OC capability of SiC MOSFETs by modifying the gate-source voltage. Since the on-state resistance ($R_{DS\left(on\right)}$) of SiC MOSFETs decreases with an increase in the gate voltage ($V_{GS}$), the conduction losses can be decreased by increasing the $V_{GS}$. Experiments and simulations have been performed to predict the $R_{DS\left(on\right)}$ with the increase in $V_{GS}$. It is found that the simulation models provided by manufacturers can be used to predict $R_{DS\left(on\right)}$ accurately even outside the specifications, hence facilitating the precise estimation of conduction losses. It is also concluded that $V_{GS}$ can be increased during OCs in order to keep the conduction losses within the safety limits. A simple concept for implementing this function on a gate driver is also proposed with the additional functionality of increasing the $V_{GS}$ during OC by measuring the on-state voltage of the MOSFET.

1. Introduction

In the process towards a de-carbonized society with continuously more generation units having a power-electronics-based interface to the grid [1], the over-current (OC) capability of grid-connected generation units is foreseen to become a common requirement in grid codes [2]. There are several reasons for this, such as the requirements in terms of the capability to provide fault currents such that protection systems can operate correctly, and providing services to the grid in order to improve the stability [3,4], especially with intermittent and uncertain renewables [5,6]. An even more demanding example for the OC capability requirement is power converters operating in series with transmission lines [7]. These are either flexible alternating current transmission system (FACTS) devices in the case of AC grids [8] or power flow controllers in high-voltage direct current (HVDC) grids [9]. In these two cases, the power converter should be able to ride through various OC events, and, in serious cases, it must have the ability to sustain the current until a bypass switch has been activated [10]. The amount of OC and the duration may vary depending on the application [4]. As already pointed out in [4], silicon carbide (SiC) metal-oxide semiconductor field-effect transistors (MOSFETs) seem to be excellent candidate power semiconductor devices for providing OC capability, especially if the power converter is designed to have very high efficiency [11]. The operation of power converters with high efficiency is associated with operation at low temperatures during normal operation. This provides a substantial margin to the maximum temperature of the device, in particular if the package of the device is designed to withstand occasional high temperatures [12]. Various cooling methods close to the chip have been investigated for SiC devices, such as microchannel cooling [13] and the application of heat-absorbing materials [14,15], for enabling the OC capability. However, these methods require the modification of the power module design. One method that would not require modifying the power module is augmenting the gate voltage. As the on-state resistance ($R_{DS\left(on\right)}$) of a SiC MOSFET depends on the gate voltage, where $R_{DS\left(on\right)}$ monotonically reduces as the gate voltage increases [16,17,18,19,20,21,22,23,24,25,26,27], it is not far-fetched to assume that high gate voltages may save the SiC MOSFET from over-heating during OC events. The problem with this is that the estimated remaining lifetime of the oxide layer may be reduced [28,29]. As gate-oxide failure is one of the major failure mechanisms in SiC MOSFETs [30,31,32], it may seem unwise to expose the device to high gate voltages. However, the gate voltage ($V_{GS}$) has to be elevated only during an OC event, and this may occur only a few times per year [33,34]. In such a scenario, it is not obvious that the remaining lifetime of the SiC MOSFET will be reduced because another failure mechanism may be the decisive one. Obviously, from a thermal point of view, the higher the gate voltage the better. This would imply going far beyond the maximum gate voltage specified by the manufacturer during the OC event. The question is how much can be gained concerning the reduction in $R_{DS\left(on\right)}$ and how much the margin is with the gate voltage before a single-event burnout of the oxide is caused.

To fill the above research gap, this paper proposes to enhance the OC capability of SiC MOSFETs by modifying the gate-source voltage during transients. The outline of this paper is as follows. First, in Section 2, an experimental investigation is performed regarding how far the gate voltage can be increased without creating a single-event burnout while monitoring the reduction in on-state voltage. Next, it is investigated whether such an operation with gate voltages exceeding the maximum values can be described by common simulation software, especially regarding the capability to predict $R_{DS\left(on\right)}$ at extreme gate voltages. In Section 3, a simple implementation of a gate driver is proposed that can facilitate OC capability by increasing the gate voltage transiently. Section 4 briefly discusses the reliability aspect. Section 5 concludes the article.

2. Simulation and Experiment

This section discusses the impact of $V_{GS}$ on $R_{DS\left(on\right)}$ of SiC MOSFETs. As discussed in the introduction, $R_{DS\left(on\right)}$ decreases with an increase in $V_{GS}$ [35,36,37]. This would result in decreased conduction losses of the MOSFETs for a fixed value of current.

The SiC MOSFET tested and simulated is TO-247 NTHL080N120SC1A from OnSemi [38]. The MOSFETs are tested in the lab with $V_{GS}$ from 20 V (recommended) to 50 V with a constant drain current ($I_d$) of 20 A for 1 s (Figure 1). It was observed that a single event burnout took place at $V_{GS}=50$ V with a single clicking sound, and all three terminals of the MOSFET became shorted. The measured values of $R_{DS\left(on\right)}$ are shown in Figure 2 by the red curve.

LTspice models (version (X64):24.0.9) for the SiC MOSFETs are obtained from Onsemi [39]. There are two LTspice models available for simulations [40]. First is the 3-terminal model, which assumes no self-heating of the device. The terminals available with this model are drain (D), source (S), and gate (G). The 3-terminal model does not consider the self-heating of the devices; i.e., the die is maintained at a constant temperature or it is tested with an infinite small pulse. Second are the 5-terminal devices, which assume self-heating of the device, and the measurements are performed on a DC pulse. However, the datasheet uses 250 $\mathsf{\mu }$s, and the authors have taken the values for the same from LTspice models for comparison. Apart from the three physical terminals (D, S, and G), the other two terminals available in the model are for junction temperature ($t_j$) and case temperature ($t_{case}$). Terminal $t_{case}$ should be connected to a voltage source of 25 V in order to set ambient temperature of 25 °C, while the terminal $t_j$ can be left floating or can be connected to a resistor >1 M$\Omega$. The variation in $R_{DS\left(on\right)}$ with $V_{GS}$ in the simulations for both the simulation models is shown in Figure 2.

Table 1. Values of $R_{DS\left(on\right)}$ using experiments and simulations.

	Methods
	Experiments		3-Terminal Model		5-Terminal Model
${\mathit{V}}_{\mathit{GS}}$ (V)	${\mathit{R}}_{\mathit{DS}\left(\mathit{on}\right)}$ (m$\Omega$)	$\Delta {\mathit{R}}_{\mathit{DSon}}$(in %) w.r.t ${\mathit{R}}_{\mathit{DSon}}$ at ${\mathit{V}}_{\mathit{GS}}$ = 20 V	${\mathit{R}}_{\mathit{DS}\left(\mathit{on}\right)}$ (m$\Omega$)	${\mathit{R}}_{\mathit{DSon}}$ Deviation from Experiments (in %)	${\mathit{R}}_{\mathit{DS}\left(\mathit{on}\right)}$ (m$\Omega$)	${\mathit{R}}_{\mathit{DSon}}$ Deviation from Experiments (in %)
20	92	-	80.5	−12.5	82	−10.87
25	76	−17.4	69	−9.2	71	−6.58
30	70	−29.0	63	−10	64.5	−7.86
35	65	−38.6	59	−9.2	61	−6.15
40	60	−49.2	56.6	−5.67	58	−3.33
45	58	−56.7	54.5	−6.03	56	−3.45
50	57	−60.3	53	−7.02	54	−5.26

shows the differences among values obtained in experiments and simulations. It can be observed that the obtained $R_{DS\left(on\right)}$ values in experiments and simulations are close to each other, and the simulation models for the SiC MOSFETs provided by the manufacturer are able to provide the $R_{DS\left(on\right)}$ characteristic even outside the specifications of the datasheet. Since the 5-terminal model assumes self-heating of the device, the resistance values obtained from the 5-terminal model are slightly higher than those from the 3-terminal model. Hence, simulation models for MOSFETs can be used to predict $R_{DS\left(on\right)}$ during OCs and keep the conduction losses within safe thermal limits by varying the gate voltage.

Table 2. Reduction in conduction losses for $I_d=20$ A.

${\mathit{V}}_{\mathit{GS}}$ (V)	${\mathit{V}}_{\mathit{DS}}$ (V)	Conduction Losses (W)	% Reduction w.r.t Losses at ${\mathit{V}}_{\mathit{GS}}=20$ V
20	1.84	36.8	−
25	1.52	30.4	−17.4
30	1.4	28	−23.9
35	1.3	26	−29.4
40	1.2	24	−34.8
45	1.16	23.2	−37.0
50	1.14	22.8	−38.0

shows the conduction losses and the percent reduction in conduction losses by varying $V_{GS}$ for a fixed value of current, $I_d=20$ A, during the experiments. It can be observed from Table 2 that the conduction losses are decreased with an increase in the value of $V_{GS}$ due to the decreased value of $R_{DS\left(on\right)}$. The percent reduction in conduction losses for $V_{GS}=45$ V as compared to $V_{GS}=20$ V is 37%. Hence, $V_{GS}$ can be augmented depending on the reduction needed in the conduction losses.

The LTspice models can also be used for current values higher than the rated ones as shown in

Table 3. Values of $R_{DS\left(on\right)}$ using LTspice models for $I_d=62$ A.

	Methods
	3-Terminal Model		5-Terminal Model
${\mathit{V}}_{\mathit{GS}}$ (V)	${\mathit{R}}_{\mathit{DS}\left(\mathit{on}\right)}$ (m$\Omega$)	$\Delta {\mathit{R}}_{\mathit{DSon}}$(in %) w.r.t ${\mathit{R}}_{\mathit{DSon}}$ at ${\mathit{V}}_{\mathit{GS}}=\mathbf{20}$ V	${\mathit{R}}_{\mathit{DS}\left(\mathit{on}\right)}$ (m$\Omega$)	${\mathit{R}}_{\mathit{DSon}}$ Deviation from Experiments (in %)
20	97.02	-	101.73	-
25	77.11	−20.67	81.92	−19.5
30	68.11	−29.93	72.52	−28.7
35	62.78	−35.41	66.990	−34.2
40	59.30	−38.99	63.14	−37.9
45	56.81	−41.56	60.45	−40.6
50	54.94	−43.48	58.4387	−42.6

and Figure 3. The estimated value of $R_{DS\left(on\right)}$ at 62 A for $V_{GS}=20$ V from the datasheet (Figures 1 and 2 of the datasheet) in [38] is 101 m$\Omega$. The LTspice models have been tested for 62 A (i.e., two times the rated value, which is 31 A) to calculate the $R_{DS\left(on\right)}$ values with the same pulse as that of the datasheet (250 $\mathsf{\mu }$s pulse). The $R_{DS\left(on\right)}$ values with 3-terminal and 5-terminal models are 97.20 m$\Omega$ and 101.73 m$\Omega$, respectively. The deviations in $R_{DS\left(on\right)}$ with respect to the value at $V_{GS}=20$ V for 3-terminal and 5-terminal models are 3.75% and 0.72%, respectively. It can be concluded that the LTspice models can be used to predict $R_{DS\left(on\right)}$ values precisely, even outside the range of the datasheet, consequently estimating the conduction losses.

3. Proposed Driver

As elaborated on in Section 2, increasing $V_{GS}$ may have the potential to enable OC capability by reducing or keeping the conduction losses within limits. This section proposes and discusses a gate driver in order to facilitate transient operation with an elevated gate voltage. A simple implementation of a gate driver with this capability is proposed. In Figure 4, a simplified schematic diagram of the proposed gate driver is shown. The proposed design is in no way optimized. The purpose of showing an example implementation of a driver capable of transiently augmenting the gate voltage is just to show that this does not necessarily imply that the gate driver becomes excessively complicated. Other alternative designs may be both more cost-effective and have better performance than the proposed design. On the left-hand side, the optical on/off signal is transmitted to the gate driver. During normal operation, this signal is conveyed to the standard output stage of the driver. This stage will then provide normal gate voltages for the on and off states via the resistors, $R_{on}$ and $R_{off}$. In order to implement the function to augment the gate voltage, the on-state voltage drop of the SiC MOSFET is measured in the same way as for a desaturation-type short-circuit protection [41]. This is performed in the block “Clamp. Meas. Logic”. If the on-state voltage exceeds a predefined value, a signal is provided to the block “OPTO INTERFACE & DECODING”, which in turn turns on the switch that provides the augmented gate voltage $V_{OC}$ to the gate via the resistor $R_{OC}$. When the current reduces below a predefined value, the gate driver switches back to normal operation. It should be noted that all the used blocks in the proposed gate driver have been shown to work in commercially available gate drivers. The only difference compared to a commercial driver with desaturation detection is the additional upper branch of a driver totem-pole with a higher supply voltage.

An alternative implementation would be to omit the measurement of the gate voltage and instead measure the current elsewhere and decide when to operate at an augmented gate voltage through a separate optical channel to the gate driver. This channel could either be a separate fiber (or optocoupler) or a modified protocol on a single fiber.

4. Discussion

Section 2 showed that the conduction losses can be reduced for a fixed value of $I_d$. With the same explanation, the conduction can be kept constant by increasing the $V_{GS}$ during an OC. The switching losses can be reduced during an OC by reducing the switching frequency, as discussed in [4]. By combining the two mentioned methods for conduction and switching losses, it is possible to maintain the losses within safe limits even during an OC.

A continuously increased $V_{GS}$ has a detrimental impact on the lifetime [42]. However, it would be worth investigating the impact of an occasionally increased gate voltage on the gate oxide degradation for short pulses with the same procedure as the one investigated in [28]. To some extent, this investigation has already been performed in [28]. A closer analysis of the results reveals that an increase in the gate voltage by 5 V yields a lifetime reduction of approximately 100 times for all three investigated manufacturers. In other words, this can be interpreted such that, if the gate voltage is augmented by 5 V during an OC event of one second, the lifetime of the device would be reduced by 100 s. Similarly, an increase in the gate voltage of 10 V would cause a reduction in the lifetime by 10,000 times, and 15 V one million times. This can be interpreted such that, if the gate voltage is augmented by 5 V during an OC event of one second, the lifetime of the device would be reduced by 100 s, and one-second augmentations of 10 V and 15 V would cause reductions in lifetime of 2.8 h and 278 h, respectively. Such reductions in lifetime may be acceptable from an application point of view provided that the OC events are not too frequent. Nevertheless, a more detailed experimental investigation would be necessary before the development of a product could be initiated.

5. Conclusions

The paper investigated the idea and vision of enabling the OC capability of SiC MOSFETs by increasing the gate voltage during OCs. The values of $R_{DS\left(on\right)}$ matched closely with the experiments and simulations. It is also concluded that the simulation models provided by manufacturers can be used to predict the $R_{DS\left(on\right)}$ values even outside the specifications of the datasheet. A simple implementation of a gate driver that facilitates the proposed gate voltage augmentation is also proposed. The results show that a thorough investigation is needed to determine the impact of occasional increased gate voltage on gate oxide degradation.